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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9D1.mail.protection.outlook.com (10.167.241.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6521.23 via Frontend Transport; Wed, 21 Jun 2023 23:56:05 +0000 Received: from ruby-95f9host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Wed, 21 Jun 2023 18:55:59 -0500 From: Suravee Suthikulpanit To: , , CC: , , , , , , , , , , , , , , , "Suravee Suthikulpanit" Subject: [RFC PATCH 18/21] iommu/amd: Introduce vIOMMU ioctl for handling guest MMIO accesses Date: Wed, 21 Jun 2023 18:55:05 -0500 Message-ID: <20230621235508.113949-19-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> References: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D1:EE_|SJ0PR12MB5502:EE_ X-MS-Office365-Filtering-Correlation-Id: f86a63b5-5a58-47bc-4a1d-08db72b3134a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 23:56:05.0311 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f86a63b5-5a58-47bc-4a1d-08db72b3134a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D1.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5502 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This ioctl interface is used for handling guest MMIO read / write to IOMMU MMIO registers. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/viommu.c | 250 +++++++++++++++++++++++++++++++++++++ 1 file changed, 250 insertions(+) diff --git a/drivers/iommu/amd/viommu.c b/drivers/iommu/amd/viommu.c index 1bcb895cffbf..9ddbdbec4a75 100644 --- a/drivers/iommu/amd/viommu.c +++ b/drivers/iommu/amd/viommu.c @@ -744,3 +744,253 @@ int amd_viommu_device_update(struct amd_viommu_dev_in= fo *data, bool is_set) return 0; } EXPORT_SYMBOL(amd_viommu_device_update); + +int amd_viommu_guest_mmio_read(struct amd_viommu_mmio_data *data) +{ + u8 __iomem *vfctrl, *vf; + u64 val, tmp =3D 0; + int gid =3D data->gid; + struct amd_iommu *iommu =3D get_amd_iommu_from_devid(data->iommu_id); + + if (!iommu) + return -ENODEV; + + vf =3D VIOMMU_VF_MMIO_BASE(iommu, gid); + vfctrl =3D VIOMMU_VFCTRL_MMIO_BASE(iommu, gid); + + switch (data->offset) { + case MMIO_CONTROL_OFFSET: + { + /* VFCTRL offset 20h */ + val =3D readq(vfctrl + 0x20); + tmp |=3D SET_CTRL_BITS(val, 8, CONTROL_CMDBUF_EN, 1); // [12] + tmp |=3D SET_CTRL_BITS(val, 9, CONTROL_COMWAIT_EN, 1); // [4] + + /* VFCTRL offset 28h */ + val =3D readq(vfctrl + 0x28); + tmp |=3D SET_CTRL_BITS(val, 8, CONTROL_EVT_LOG_EN, 1); // [2] + tmp |=3D SET_CTRL_BITS(val, 9, CONTROL_EVT_INT_EN, 1); // [3] + tmp |=3D SET_CTRL_BITS(val, 10, CONTROL_DUALEVTLOG_EN, 3); // [33:32] + + /* VFCTRL offset 30h */ + val =3D readq(vfctrl + 0x30); + tmp |=3D SET_CTRL_BITS(val, 8, CONTROL_PPRLOG_EN, 1); // [13] + tmp |=3D SET_CTRL_BITS(val, 9, CONTROL_PPRINT_EN, 1); // [14] + tmp |=3D SET_CTRL_BITS(val, 10, CONTROL_PPR_EN, 1); // [15] + tmp |=3D SET_CTRL_BITS(val, 11, CONTROL_DUALPPRLOG_EN, 3); // [31:30] + tmp |=3D SET_CTRL_BITS(val, 13, CONTROL_PPR_AUTO_RSP_EN, 1); // [39] + tmp |=3D SET_CTRL_BITS(val, 14, CONTROL_BLKSTOPMRK_EN, 1); // [41] + tmp |=3D SET_CTRL_BITS(val, 15, CONTROL_PPR_AUTO_RSP_AON, 1); // [42] + + data->value =3D tmp; + break; + } + case MMIO_CMD_BUF_OFFSET: + { + val =3D readq(vfctrl + 0x20); + /* CmdLen [59:56] */ + tmp |=3D SET_CTRL_BITS(val, 0, 56, 0xF); + data->value =3D tmp; + break; + } + case MMIO_EVT_BUF_OFFSET: + { + val =3D readq(vfctrl + 0x28); + /* EventLen [59:56] */ + tmp |=3D SET_CTRL_BITS(val, 0, 56, 0xF); + data->value =3D tmp; + break; + } + case MMIO_EVTB_LOG_OFFSET: + { + val =3D readq(vfctrl + 0x28); + /* EventLenB [59:56] */ + tmp |=3D SET_CTRL_BITS(val, 4, 56, 0xF); + data->value =3D tmp; + break; + } + case MMIO_PPR_LOG_OFFSET: + { + val =3D readq(vfctrl + 0x30); + /* PPRLogLen [59:56] */ + tmp |=3D SET_CTRL_BITS(val, 0, 56, 0xF); + data->value =3D tmp; + break; + } + case MMIO_PPRB_LOG_OFFSET: + { + val =3D readq(vfctrl + 0x30); + /* PPRLogLenB [59:56] */ + tmp |=3D SET_CTRL_BITS(val, 4, 56, 0xF); + data->value |=3D tmp; + break; + } + case MMIO_CMD_HEAD_OFFSET: + { + val =3D readq(vf + 0x0); + data->value =3D (val & 0x7FFF0); + break; + } + case MMIO_CMD_TAIL_OFFSET: + { + val =3D readq(vf + 0x8); + data->value =3D (val & 0x7FFF0); + break; + } + case MMIO_EXT_FEATURES: + { + amd_iommu_build_efr(&data->value, NULL); + break; + } + default: + break; + } + + pr_debug("%s: iommu_id=3D%#x, gid=3D%u, offset=3D%#x, value=3D%#llx, mmio= _size=3D%u, is_write=3D%u\n", + __func__, data->iommu_id, gid, data->offset, + data->value, data->mmio_size, data->is_write); + return 0; +} +EXPORT_SYMBOL(amd_viommu_guest_mmio_read); + +/* Note: + * This function maps the guest MMIO write to AMD IOMMU MMIO registers + * into vIOMMU VFCTRL register bits. + */ +int amd_viommu_guest_mmio_write(struct amd_viommu_mmio_data *data) +{ + u8 __iomem *vfctrl, *vf; + int gid =3D data->gid; + u64 val, tmp, ctrl =3D data->value; + struct amd_iommu *iommu =3D get_amd_iommu_from_devid(data->iommu_id); + + if (!iommu) + return -ENODEV; + + pr_debug("%s: iommu_id=3D%#x, gid=3D%u, offset=3D%#x, value=3D%#llx, mmio= _size=3D%u, is_write=3D%u\n", + __func__, data->iommu_id, gid, data->offset, + ctrl, data->mmio_size, data->is_write); + + vf =3D VIOMMU_VF_MMIO_BASE(iommu, gid); + vfctrl =3D VIOMMU_VFCTRL_MMIO_BASE(iommu, gid); + + switch (data->offset) { + case MMIO_CONTROL_OFFSET: + { + /* VFCTRL offset 20h */ + val =3D readq(vfctrl + 0x20); + val &=3D ~(0x3ULL << 8); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_CMDBUF_EN, 1); // [12] + val |=3D (tmp << 8); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_COMWAIT_EN, 1); // [4] + val |=3D (tmp << 9); + writeq(val, vfctrl + 0x20); + + /* VFCTRL offset 28h */ + val =3D readq(vfctrl + 0x28); + val &=3D ~(0xFULL << 8); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_EVT_LOG_EN, 1); // [2] + val |=3D (tmp << 8); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_EVT_INT_EN, 1); // [3] + val |=3D (tmp << 9); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_DUALEVTLOG_EN, 3); // [33:32] + val |=3D (tmp << 10); + writeq(val, vfctrl + 0x28); + + /* VFCTRL offset 30h */ + val =3D readq(vfctrl + 0x30); + val &=3D ~(0xFFULL << 8); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_PPRLOG_EN, 1); // [13] + val |=3D (tmp << 8); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_PPRINT_EN, 1); // [14] + val |=3D (tmp << 9); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_PPR_EN, 1); // [15] + val |=3D (tmp << 10); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_DUALPPRLOG_EN, 3); // [31:30] + val |=3D (tmp << 11); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_PPR_AUTO_RSP_EN, 1); // [39] + val |=3D (tmp << 13); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_BLKSTOPMRK_EN, 1); // [41] + val |=3D (tmp << 14); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_PPR_AUTO_RSP_AON, 1); // [42] + val |=3D (tmp << 15); + writeq(val, vfctrl + 0x30); + break; + } + case MMIO_CMD_BUF_OFFSET: + { + val =3D readq(vfctrl + 0x20); + val &=3D ~(0xFULL); + /* CmdLen [59:56] */ + tmp =3D GET_CTRL_BITS(ctrl, 56, 0xF); + val |=3D tmp; + writeq(val, vfctrl + 0x20); + break; + } + case MMIO_EVT_BUF_OFFSET: + { + val =3D readq(vfctrl + 0x28); + val &=3D ~(0xFULL); + /* EventLen [59:56] */ + tmp =3D GET_CTRL_BITS(ctrl, 56, 0xF); + val |=3D tmp; + writeq(val, vfctrl + 0x28); + break; + } + case MMIO_EVTB_LOG_OFFSET: + { + val =3D readq(vfctrl + 0x28); + val &=3D ~(0xF0ULL); + /* EventLenB [59:56] */ + tmp =3D GET_CTRL_BITS(ctrl, 56, 0xF); + val |=3D (tmp << 4); + writeq(val, vfctrl + 0x28); + break; + } + case MMIO_PPR_LOG_OFFSET: + { + val =3D readq(vfctrl + 0x30); + val &=3D ~(0xFULL); + /* PPRLogLen [59:56] */ + tmp =3D GET_CTRL_BITS(ctrl, 56, 0xF); + val |=3D tmp; + writeq(val, vfctrl + 0x30); + break; + } + case MMIO_PPRB_LOG_OFFSET: + { + val =3D readq(vfctrl + 0x30); + val &=3D ~(0xF0ULL); + /* PPRLogLenB [59:56] */ + tmp =3D GET_CTRL_BITS(ctrl, 56, 0xF); + val |=3D (tmp << 4); + writeq(val, vfctrl + 0x30); + break; + } + case MMIO_CMD_HEAD_OFFSET: + { + val =3D readq(vf + 0x0); + val &=3D ~(0x7FFFULL << 4); + tmp =3D GET_CTRL_BITS(ctrl, 4, 0x7FFF); + val |=3D (tmp << 4); + writeq(val, vf + 0x0); + break; + } + case MMIO_CMD_TAIL_OFFSET: + { + val =3D readq(vf + 0x8); + val &=3D ~(0x7FFFULL << 4); + tmp =3D GET_CTRL_BITS(ctrl, 4, 0x7FFF); + val |=3D (tmp << 4); + writeq(val, vf + 0x8); + break; + } + default: + break; + } + + pr_debug("%s: offset=3D%#x, val=3D%#llx, ctrl=3D%#llx\n", + __func__, data->offset, val, ctrl); + return 0; +} +EXPORT_SYMBOL(amd_viommu_guest_mmio_write); --=20 2.34.1