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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9CD.mail.protection.outlook.com (10.167.241.140) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6521.24 via Frontend Transport; Wed, 21 Jun 2023 23:55:44 +0000 Received: from ruby-95f9host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Wed, 21 Jun 2023 18:55:42 -0500 From: Suravee Suthikulpanit To: , , CC: , , , , , , , , , , , , , , , "Suravee Suthikulpanit" Subject: [RFC PATCH 01/21] iommu/amd: Declare helper functions as extern Date: Wed, 21 Jun 2023 18:54:48 -0500 Message-ID: <20230621235508.113949-2-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> References: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CD:EE_|IA1PR12MB7568:EE_ X-MS-Office365-Filtering-Correlation-Id: 3efdd915-31d2-4947-eabf-08db72b306ff X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 23:55:44.4267 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3efdd915-31d2-4947-eabf-08db72b306ff X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7568 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To allow reuse from other files. There is no functional change. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 18 ++++++++++++++++++ drivers/iommu/amd/init.c | 6 +++--- drivers/iommu/amd/io_pgtable.c | 18 +++++++++--------- drivers/iommu/amd/iommu.c | 14 +++++++------- 4 files changed, 37 insertions(+), 19 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index e98f20a9bdd8..827d065bbe8e 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -11,6 +11,24 @@ =20 #include "amd_iommu_types.h" =20 +extern void iommu_feature_enable(struct amd_iommu *iommu, u8 bit); +extern void iommu_feature_disable(struct amd_iommu *iommu, u8 bit); +extern u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end); +extern void set_dte_entry(struct amd_iommu *iommu, u16 devid, + struct protection_domain *domain, + bool ats, bool ppr); +extern int iommu_flush_dte(struct amd_iommu *iommu, u16 devid); +extern struct protection_domain *to_pdomain(struct iommu_domain *dom); +extern struct iommu_domain *amd_iommu_domain_alloc(unsigned int type); +extern void amd_iommu_domain_free(struct iommu_domain *dom); +extern int amd_iommu_v1_map_pages(struct io_pgtable_ops *ops, unsigned lon= g iova, + phys_addr_t paddr, size_t pgsize, size_t pgcount, + int prot, gfp_t gfp, size_t *mapped); +extern unsigned long amd_iommu_v1_unmap_pages(struct io_pgtable_ops *ops, + unsigned long iova, + size_t pgsize, size_t pgcount, + struct iommu_iotlb_gather *gather); + extern irqreturn_t amd_iommu_int_thread(int irq, void *data); extern irqreturn_t amd_iommu_int_handler(int irq, void *data); extern void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid); diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 329a406cc37d..886cf55e75e2 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -432,7 +432,7 @@ static void iommu_set_device_table(struct amd_iommu *io= mmu) } =20 /* Generic functions to enable/disable certain features of the IOMMU. */ -static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) +void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) { u64 ctrl; =20 @@ -441,7 +441,7 @@ static void iommu_feature_enable(struct amd_iommu *iomm= u, u8 bit) writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); } =20 -static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) +void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) { u64 ctrl; =20 @@ -490,7 +490,7 @@ static void iommu_disable(struct amd_iommu *iommu) * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMM= U in * the system has one. */ -static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end) +u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end) { if (!request_mem_region(address, end, "amd_iommu")) { pr_err("Can not reserve memory region %llx-%llx for mmio\n", diff --git a/drivers/iommu/amd/io_pgtable.c b/drivers/iommu/amd/io_pgtable.c index 1b67116882be..9b398673208d 100644 --- a/drivers/iommu/amd/io_pgtable.c +++ b/drivers/iommu/amd/io_pgtable.c @@ -360,9 +360,9 @@ static void free_clear_pte(u64 *pte, u64 pteval, struct= list_head *freelist) * supporting all features of AMD IOMMU page tables like level skipping * and full 64 bit address spaces. */ -static int iommu_v1_map_pages(struct io_pgtable_ops *ops, unsigned long io= va, - phys_addr_t paddr, size_t pgsize, size_t pgcount, - int prot, gfp_t gfp, size_t *mapped) +int amd_iommu_v1_map_pages(struct io_pgtable_ops *ops, unsigned long iova, + phys_addr_t paddr, size_t pgsize, size_t pgcount, + int prot, gfp_t gfp, size_t *mapped) { struct protection_domain *dom =3D io_pgtable_ops_to_domain(ops); LIST_HEAD(freelist); @@ -435,10 +435,10 @@ static int iommu_v1_map_pages(struct io_pgtable_ops *= ops, unsigned long iova, return ret; } =20 -static unsigned long iommu_v1_unmap_pages(struct io_pgtable_ops *ops, - unsigned long iova, - size_t pgsize, size_t pgcount, - struct iommu_iotlb_gather *gather) +unsigned long amd_iommu_v1_unmap_pages(struct io_pgtable_ops *ops, + unsigned long iova, + size_t pgsize, size_t pgcount, + struct iommu_iotlb_gather *gather) { struct amd_io_pgtable *pgtable =3D io_pgtable_ops_to_data(ops); unsigned long long unmapped; @@ -524,8 +524,8 @@ static struct io_pgtable *v1_alloc_pgtable(struct io_pg= table_cfg *cfg, void *coo cfg->oas =3D IOMMU_OUT_ADDR_BIT_SIZE, cfg->tlb =3D &v1_flush_ops; =20 - pgtable->iop.ops.map_pages =3D iommu_v1_map_pages; - pgtable->iop.ops.unmap_pages =3D iommu_v1_unmap_pages; + pgtable->iop.ops.map_pages =3D amd_iommu_v1_map_pages; + pgtable->iop.ops.unmap_pages =3D amd_iommu_v1_unmap_pages; pgtable->iop.ops.iova_to_phys =3D iommu_v1_iova_to_phys; =20 return &pgtable->iop; diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 4a314647d1f7..bbd10698851f 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -177,7 +177,7 @@ static struct amd_iommu *rlookup_amd_iommu(struct devic= e *dev) return __rlookup_amd_iommu(seg, PCI_SBDF_TO_DEVID(devid)); } =20 -static struct protection_domain *to_pdomain(struct iommu_domain *dom) +struct protection_domain *to_pdomain(struct iommu_domain *dom) { return container_of(dom, struct protection_domain, domain); } @@ -450,7 +450,7 @@ static void amd_iommu_uninit_device(struct device *dev) * *************************************************************************= ***/ =20 -static void dump_dte_entry(struct amd_iommu *iommu, u16 devid) +void dump_dte_entry(struct amd_iommu *iommu, u16 devid) { int i; struct dev_table_entry *dev_table =3D get_dev_table(iommu); @@ -1192,7 +1192,7 @@ static int iommu_completion_wait(struct amd_iommu *io= mmu) return ret; } =20 -static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) +int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) { struct iommu_cmd cmd; =20 @@ -1553,8 +1553,8 @@ static void free_gcr3_table(struct protection_domain = *domain) free_page((unsigned long)domain->gcr3_tbl); } =20 -static void set_dte_entry(struct amd_iommu *iommu, u16 devid, - struct protection_domain *domain, bool ats, bool ppr) +void set_dte_entry(struct amd_iommu *iommu, u16 devid, + struct protection_domain *domain, bool ats, bool ppr) { u64 pte_root =3D 0; u64 flags =3D 0; @@ -2118,7 +2118,7 @@ static struct protection_domain *protection_domain_al= loc(unsigned int type) return NULL; } =20 -static struct iommu_domain *amd_iommu_domain_alloc(unsigned type) +struct iommu_domain *amd_iommu_domain_alloc(unsigned int type) { struct protection_domain *domain; =20 @@ -2140,7 +2140,7 @@ static struct iommu_domain *amd_iommu_domain_alloc(un= signed type) return &domain->domain; } =20 -static void amd_iommu_domain_free(struct iommu_domain *dom) +void amd_iommu_domain_free(struct iommu_domain *dom) { struct protection_domain *domain; =20 --=20 2.34.1 From nobody Sun Feb 8 05:19:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D64BCC001B3 for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9CD.mail.protection.outlook.com (10.167.241.140) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6521.24 via Frontend Transport; Wed, 21 Jun 2023 23:55:45 +0000 Received: from ruby-95f9host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Wed, 21 Jun 2023 18:55:43 -0500 From: Suravee Suthikulpanit To: , , CC: , , , , , , , , , , , , , , , "Suravee Suthikulpanit" Subject: [RFC PATCH 02/21] iommu/amd: Clean up spacing in amd_iommu_ops declaration Date: Wed, 21 Jun 2023 18:54:49 -0500 Message-ID: <20230621235508.113949-3-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> References: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CD:EE_|MN2PR12MB4270:EE_ X-MS-Office365-Filtering-Correlation-Id: 4d6000db-7afa-41b2-4769-08db72b3077e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 23:55:45.2392 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4d6000db-7afa-41b2-4769-08db72b3077e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4270 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Preparing for additional iommu_ops. There is no functional change. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/iommu.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index bbd10698851f..356e52f478f1 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2423,17 +2423,17 @@ static bool amd_iommu_enforce_cache_coherency(struc= t iommu_domain *domain) } =20 const struct iommu_ops amd_iommu_ops =3D { - .capable =3D amd_iommu_capable, - .domain_alloc =3D amd_iommu_domain_alloc, - .probe_device =3D amd_iommu_probe_device, - .release_device =3D amd_iommu_release_device, - .probe_finalize =3D amd_iommu_probe_finalize, - .device_group =3D amd_iommu_device_group, - .get_resv_regions =3D amd_iommu_get_resv_regions, - .is_attach_deferred =3D amd_iommu_is_attach_deferred, - .pgsize_bitmap =3D AMD_IOMMU_PGSIZES, - .def_domain_type =3D amd_iommu_def_domain_type, - .default_domain_ops =3D &(const struct iommu_domain_ops) { + .capable =3D amd_iommu_capable, + .domain_alloc =3D amd_iommu_domain_alloc, + .probe_device =3D amd_iommu_probe_device, + .release_device =3D amd_iommu_release_device, + .probe_finalize =3D amd_iommu_probe_finalize, + .device_group =3D amd_iommu_device_group, + .get_resv_regions =3D amd_iommu_get_resv_regions, + .is_attach_deferred =3D amd_iommu_is_attach_deferred, + .pgsize_bitmap =3D AMD_IOMMU_PGSIZES, + .def_domain_type =3D amd_iommu_def_domain_type, + .default_domain_ops =3D &(const struct iommu_domain_ops) { .attach_dev =3D amd_iommu_attach_device, .map_pages =3D amd_iommu_map_pages, .unmap_pages =3D amd_iommu_unmap_pages, --=20 2.34.1 From nobody Sun Feb 8 05:19:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1D3FEB64DD for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 23:55:46.0048 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a91cc3b1-4731-47c8-1a86-08db72b307f3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6068 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Clean up and reorder them according to the bit index. There is no functional change. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu_types.h | 13 +++++++------ drivers/iommu/amd/init.c | 10 +++++----- 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 2ddbda3a4374..09df25779fe9 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -93,18 +93,19 @@ #define FEATURE_GA (1ULL<<7) #define FEATURE_HE (1ULL<<8) #define FEATURE_PC (1ULL<<9) -#define FEATURE_GATS_SHIFT (12) -#define FEATURE_GATS_MASK (3ULL) #define FEATURE_GAM_VAPIC (1ULL<<21) #define FEATURE_GIOSUP (1ULL<<48) #define FEATURE_EPHSUP (1ULL<<50) #define FEATURE_SNP (1ULL<<63) =20 -#define FEATURE_PASID_SHIFT 32 -#define FEATURE_PASID_MASK (0x1fULL << FEATURE_PASID_SHIFT) +#define FEATURE_GATS_SHIFT 12 +#define FEATURE_GATS_MASK (0x03ULL << FEATURE_GATS_SHIFT) =20 -#define FEATURE_GLXVAL_SHIFT 14 -#define FEATURE_GLXVAL_MASK (0x03ULL << FEATURE_GLXVAL_SHIFT) +#define FEATURE_GLX_SHIFT 14 +#define FEATURE_GLX_MASK (0x03ULL << FEATURE_GLX_SHIFT) + +#define FEATURE_PASMAX_SHIFT 32 +#define FEATURE_PASMAX_MASK (0x1FULL << FEATURE_PASMAX_SHIFT) =20 /* Extended Feature 2 Bits */ #define FEATURE_SNPAVICSUP_SHIFT 5 diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 886cf55e75e2..6a045a187971 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -310,7 +310,7 @@ static bool check_feature_on_all_iommus(u64 mask) =20 static inline int check_feature_gpt_level(void) { - return ((amd_iommu_efr >> FEATURE_GATS_SHIFT) & FEATURE_GATS_MASK); + return ((amd_iommu_efr && FEATURE_GATS_MASK) >> FEATURE_GATS_SHIFT); } =20 /* @@ -2039,16 +2039,16 @@ static int __init iommu_init_pci(struct amd_iommu *= iommu) u32 max_pasid; u64 pasmax; =20 - pasmax =3D iommu->features & FEATURE_PASID_MASK; - pasmax >>=3D FEATURE_PASID_SHIFT; + pasmax =3D iommu->features & FEATURE_PASMAX_MASK; + pasmax >>=3D FEATURE_PASMAX_SHIFT; max_pasid =3D (1 << (pasmax + 1)) - 1; =20 amd_iommu_max_pasid =3D min(amd_iommu_max_pasid, max_pasid); =20 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK); =20 - glxval =3D iommu->features & FEATURE_GLXVAL_MASK; - glxval >>=3D FEATURE_GLXVAL_SHIFT; + glxval =3D iommu->features & FEATURE_GLX_MASK; + glxval >>=3D FEATURE_GLX_SHIFT; =20 if (amd_iommu_max_glx_val =3D=3D -1) amd_iommu_max_glx_val =3D glxval; --=20 2.34.1 From nobody Sun Feb 8 05:19:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47049EB64DD for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 23:55:46.5517 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9e9241bf-7f61-4604-8cb9-08db72b30846 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6936 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To preparation for subsequent changes. There is no functional change. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 2 +- drivers/iommu/amd/iommu.c | 14 +++++++------- drivers/iommu/amd/iommu_v2.c | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 827d065bbe8e..5d2eed07a1fa 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -70,7 +70,7 @@ extern int amd_iommu_pc_set_reg(struct amd_iommu *iommu, = u8 bank, u8 cntr, extern int amd_iommu_register_ppr_notifier(struct notifier_block *nb); extern int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb); extern void amd_iommu_domain_direct_map(struct iommu_domain *dom); -extern int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids= ); +extern int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids= , bool giov); extern int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid, u64 address); extern void amd_iommu_update_and_flush_device_table(struct protection_doma= in *domain); diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 356e52f478f1..6017fce8d7fd 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -79,7 +79,7 @@ struct iommu_cmd { struct kmem_cache *amd_iommu_irq_cache; =20 static void detach_device(struct device *dev); -static int domain_enable_v2(struct protection_domain *domain, int pasids); +static int domain_enable_v2(struct protection_domain *domain, int pasids, = bool giov); =20 /*************************************************************************= *** * @@ -2051,11 +2051,9 @@ static int protection_domain_init_v2(struct protecti= on_domain *domain) return -ENOMEM; INIT_LIST_HEAD(&domain->dev_list); =20 - domain->flags |=3D PD_GIOV_MASK; - domain->domain.pgsize_bitmap =3D AMD_IOMMU_PGSIZES_V2; =20 - if (domain_enable_v2(domain, 1)) { + if (domain_enable_v2(domain, 1, true)) { domain_id_free(domain->id); return -ENOMEM; } @@ -2484,7 +2482,7 @@ void amd_iommu_domain_direct_map(struct iommu_domain = *dom) EXPORT_SYMBOL(amd_iommu_domain_direct_map); =20 /* Note: This function expects iommu_domain->lock to be held prior calling= the function. */ -static int domain_enable_v2(struct protection_domain *domain, int pasids) +static int domain_enable_v2(struct protection_domain *domain, int pasids, = bool giov) { int levels; =20 @@ -2501,13 +2499,15 @@ static int domain_enable_v2(struct protection_domai= n *domain, int pasids) =20 domain->glx =3D levels; domain->flags |=3D PD_IOMMUV2_MASK; + if (giov) + domain->flags |=3D PD_GIOV_MASK; =20 amd_iommu_domain_update(domain); =20 return 0; } =20 -int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) +int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids, bool = giov) { struct protection_domain *pdom =3D to_pdomain(dom); unsigned long flags; @@ -2525,7 +2525,7 @@ int amd_iommu_domain_enable_v2(struct iommu_domain *d= om, int pasids) goto out; =20 if (!pdom->gcr3_tbl) - ret =3D domain_enable_v2(pdom, pasids); + ret =3D domain_enable_v2(pdom, pasids, giov); =20 out: spin_unlock_irqrestore(&pdom->lock, flags); diff --git a/drivers/iommu/amd/iommu_v2.c b/drivers/iommu/amd/iommu_v2.c index 864e4ffb6aa9..0ddd10953d41 100644 --- a/drivers/iommu/amd/iommu_v2.c +++ b/drivers/iommu/amd/iommu_v2.c @@ -784,7 +784,7 @@ int amd_iommu_init_device(struct pci_dev *pdev, int pas= ids) dev_state->domain->type =3D IOMMU_DOMAIN_IDENTITY; amd_iommu_domain_direct_map(dev_state->domain); =20 - ret =3D amd_iommu_domain_enable_v2(dev_state->domain, pasids); + ret =3D amd_iommu_domain_enable_v2(dev_state->domain, pasids, false); if (ret) goto out_free_domain; =20 --=20 2.34.1 From nobody Sun Feb 8 05:19:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 442A4EB64DC for ; Wed, 21 Jun 2023 23:56:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230005AbjFUX4L (ORCPT ); Wed, 21 Jun 2023 19:56:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37828 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229999AbjFUXzv (ORCPT ); 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Wed, 21 Jun 2023 18:55:46 -0500 From: Suravee Suthikulpanit To: , , CC: , , , , , , , , , , , , , , , "Suravee Suthikulpanit" Subject: [RFC PATCH 05/21] iommu/amd: Refactor set_dte_entry() helper function Date: Wed, 21 Jun 2023 18:54:52 -0500 Message-ID: <20230621235508.113949-6-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> References: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D4:EE_|IA0PR12MB7625:EE_ X-MS-Office365-Filtering-Correlation-Id: dd94c437-1e02-4831-622e-08db72b3090d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: GHCHekY8JjVpha0ypVrIWbrwQ0gPLCWww0oL2WuoWGHlR8hVjblKKbySoMGiHzhT1aGfDh4oizSa3Qt6qdR5M3rje0q/7MLmKTQrVimjVdpFP1wlb6uxaCdFblMe4M95aucRvhvTErYZLOdpGXoGvRWHFaZtH5aJNbszWaSPqv3chyEkdhe1+eRcG1/sDhM00KNkY+6QnSdhUf5a/iHWkGKthioh1eUWngv9RVvqS3Yx48XN/0e9ejDgWM3RC0i22He2TuvOoNfZ5N1M50Fdfb76mnyWDFBGluZIoOoMClCPNxr1clqdihkBb3vseYUmwd2nxPXUa+ZJQ9knatwtRxOxPkVskDOAHegxpdo5dDfxJp1YvRnz3WtrOZll4zJUsnUO2ZQCFtoMLR4rnp7EUj0t3tLoEqjS5CRbiBFw30xM1VTDrbd2LYPk+O1zJhBaiME+rgdArxy/RrhgShoZUGHGhrZNr3vj8ZCltO8/+rpt/oRiWCFF/C++yySLerbD76KarIGDnVaipEvS1DrhpmmLrhQgNEV2wiXBeosf1PZwC4ikxE5gD8zl6kkTIH+I5l5Mu5zw1/aw2odonJOiHQJvaCwGBFcguzBv8hme+XXDXSARJHIxNXs/ggzb+wnp1I3HqU2f2iLpWKY4qei31GX1UXpcmbXwgp4+pAa3DteTV9HdyiNRygXkGL2mkyeH4+BRQ5v884+OZwDEBXdt0JuplItAC8SCX9wiXyrK5Y5cxbw85nkm2PBGA+HCrWCcHu2Cm6nTDolIrjhH+1zC1w== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(396003)(346002)(39860400002)(376002)(136003)(451199021)(36840700001)(40470700004)(46966006)(356005)(81166007)(36756003)(82740400003)(40480700001)(86362001)(40460700003)(82310400005)(70586007)(2616005)(41300700001)(8936002)(316002)(8676002)(478600001)(4326008)(70206006)(44832011)(47076005)(426003)(83380400001)(1076003)(336012)(7416002)(5660300002)(6666004)(7696005)(16526019)(186003)(54906003)(110136005)(26005)(36860700001)(2906002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 23:55:47.8547 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dd94c437-1e02-4831-622e-08db72b3090d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7625 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To separate logic for IOMMU guest (v2) page table into another helper function in preparation for subsequent changes. There is no functional change. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/iommu.c | 72 ++++++++++++++++++++++----------------- 1 file changed, 41 insertions(+), 31 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 6017fce8d7fd..3b31ecde0122 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -1553,6 +1553,42 @@ static void free_gcr3_table(struct protection_domain= *domain) free_page((unsigned long)domain->gcr3_tbl); } =20 +static void set_dte_entry_v2(struct amd_iommu *iommu, + struct protection_domain *domain, + u64 *gcr3_tbl, u64 *pte_root, u64 *flags) +{ + u64 gcr3 =3D iommu_virt_to_phys(gcr3_tbl); + u64 glx =3D domain->glx; + u64 tmp; + + if (!(domain->flags & PD_IOMMUV2_MASK)) + return; + + if ((domain->flags & PD_GIOV_MASK) && + iommu_feature(iommu, FEATURE_GIOSUP)) + *pte_root |=3D DTE_FLAG_GIOV; + + *pte_root |=3D DTE_FLAG_GV; + *pte_root |=3D (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; + + /* First mask out possible old values for GCR3 table */ + tmp =3D DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; + *flags &=3D ~tmp; + + tmp =3D DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; + *flags &=3D ~tmp; + + /* Encode GCR3 table into DTE */ + tmp =3D DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; + *pte_root |=3D tmp; + + tmp =3D DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; + *flags |=3D tmp; + + tmp =3D DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; + *flags |=3D tmp; +} + void set_dte_entry(struct amd_iommu *iommu, u16 devid, struct protection_domain *domain, bool ats, bool ppr) { @@ -1586,38 +1622,12 @@ void set_dte_entry(struct amd_iommu *iommu, u16 dev= id, pte_root |=3D 1ULL << DEV_ENTRY_PPR; } =20 - if (domain->flags & PD_IOMMUV2_MASK) { - u64 gcr3 =3D iommu_virt_to_phys(domain->gcr3_tbl); - u64 glx =3D domain->glx; - u64 tmp; - - pte_root |=3D DTE_FLAG_GV; - pte_root |=3D (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; - - /* First mask out possible old values for GCR3 table */ - tmp =3D DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; - flags &=3D ~tmp; - - tmp =3D DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; - flags &=3D ~tmp; - - /* Encode GCR3 table into DTE */ - tmp =3D DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; - pte_root |=3D tmp; - - tmp =3D DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; - flags |=3D tmp; - - tmp =3D DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; - flags |=3D tmp; - - if (amd_iommu_gpt_level =3D=3D PAGE_MODE_5_LEVEL) { - dev_table[devid].data[2] |=3D - ((u64)GUEST_PGTABLE_5_LEVEL << DTE_GPT_LEVEL_SHIFT); - } + set_dte_entry_v2(iommu, domain, domain->gcr3_tbl, &pte_root, &flags); =20 - if (domain->flags & PD_GIOV_MASK) - pte_root |=3D DTE_FLAG_GIOV; + if ((domain->flags & PD_IOMMUV2_MASK) && + amd_iommu_gpt_level =3D=3D PAGE_MODE_5_LEVEL) { + dev_table[devid].data[2] |=3D + ((u64)GUEST_PGTABLE_5_LEVEL << DTE_GPT_LEVEL_SHIFT); } =20 flags &=3D ~DEV_DOMID_MASK; --=20 2.34.1 From nobody Sun Feb 8 05:19:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 809ECEB64DC for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9D4.mail.protection.outlook.com (10.167.241.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6521.21 via Frontend Transport; Wed, 21 Jun 2023 23:55:48 +0000 Received: from ruby-95f9host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Wed, 21 Jun 2023 18:55:47 -0500 From: Suravee Suthikulpanit To: , , CC: , , , , , , , , , , , , , , , "Suravee Suthikulpanit" Subject: [RFC PATCH 06/21] iommu/amd: Modify set_dte_entry() to add gcr3 input parameter Date: Wed, 21 Jun 2023 18:54:53 -0500 Message-ID: <20230621235508.113949-7-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> References: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D4:EE_|DM6PR12MB5008:EE_ X-MS-Office365-Filtering-Correlation-Id: 9cac8257-46cc-4cc0-e63e-08db72b30992 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 23:55:48.7297 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9cac8257-46cc-4cc0-e63e-08db72b30992 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB5008 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To preparation for subsequent changes. There is no functional change. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 1 + drivers/iommu/amd/iommu.c | 10 ++++++---- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 5d2eed07a1fa..dbfc70556220 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -16,6 +16,7 @@ extern void iommu_feature_disable(struct amd_iommu *iommu= , u8 bit); extern u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end); extern void set_dte_entry(struct amd_iommu *iommu, u16 devid, struct protection_domain *domain, + u64 *gcr3_tbl, bool ats, bool ppr); extern int iommu_flush_dte(struct amd_iommu *iommu, u16 devid); extern struct protection_domain *to_pdomain(struct iommu_domain *dom); diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 3b31ecde0122..4728929657f5 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -1590,7 +1590,9 @@ static void set_dte_entry_v2(struct amd_iommu *iommu, } =20 void set_dte_entry(struct amd_iommu *iommu, u16 devid, - struct protection_domain *domain, bool ats, bool ppr) + struct protection_domain *domain, + u64 *gcr3_tbl, + bool ats, bool ppr) { u64 pte_root =3D 0; u64 flags =3D 0; @@ -1622,7 +1624,7 @@ void set_dte_entry(struct amd_iommu *iommu, u16 devid, pte_root |=3D 1ULL << DEV_ENTRY_PPR; } =20 - set_dte_entry_v2(iommu, domain, domain->gcr3_tbl, &pte_root, &flags); + set_dte_entry_v2(iommu, domain, gcr3_tbl, &pte_root, &flags); =20 if ((domain->flags & PD_IOMMUV2_MASK) && amd_iommu_gpt_level =3D=3D PAGE_MODE_5_LEVEL) { @@ -1686,7 +1688,7 @@ static void do_attach(struct iommu_dev_data *dev_data, domain->dev_cnt +=3D 1; =20 /* Update device table */ - set_dte_entry(iommu, dev_data->devid, domain, + set_dte_entry(iommu, dev_data->devid, domain, domain->gcr3_tbl, ats, dev_data->iommu_v2); clone_aliases(iommu, dev_data->dev); =20 @@ -1965,7 +1967,7 @@ static void update_device_table(struct protection_dom= ain *domain) =20 if (!iommu) continue; - set_dte_entry(iommu, dev_data->devid, domain, + set_dte_entry(iommu, dev_data->devid, domain, domain->gcr3_tbl, dev_data->ats.enabled, dev_data->iommu_v2); clone_aliases(iommu, dev_data->dev); } --=20 2.34.1 From nobody Sun Feb 8 05:19:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7304EB64D8 for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 23:55:50.3860 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 75a552d4-1f28-4ec4-a08f-08db72b30a8f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5469 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" When setting up IOMMU page table in nested mode, the host (v1) table is managed by the hypervisor, while the guest (v2) table is managed by the guest kernel. In this case, IOMMU driver needs to program IOMMU device table entry (DTE) using the set_dte_entry() helper function with guest table information (i.e. gcr3 table, glx, max pasid), which is stored in the user domain. There is no functional change. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 1 + drivers/iommu/amd/iommu.c | 9 ++++++--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index dbfc70556220..d36a39796c2f 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -16,6 +16,7 @@ extern void iommu_feature_disable(struct amd_iommu *iommu= , u8 bit); extern u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end); extern void set_dte_entry(struct amd_iommu *iommu, u16 devid, struct protection_domain *domain, + struct protection_domain *udomain, u64 *gcr3_tbl, bool ats, bool ppr); extern int iommu_flush_dte(struct amd_iommu *iommu, u16 devid); diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 4728929657f5..333c8a4831be 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -1591,9 +1591,11 @@ static void set_dte_entry_v2(struct amd_iommu *iommu, =20 void set_dte_entry(struct amd_iommu *iommu, u16 devid, struct protection_domain *domain, + struct protection_domain *udomain, u64 *gcr3_tbl, bool ats, bool ppr) { + struct protection_domain *dom; u64 pte_root =3D 0; u64 flags =3D 0; u32 old_domid; @@ -1624,7 +1626,8 @@ void set_dte_entry(struct amd_iommu *iommu, u16 devid, pte_root |=3D 1ULL << DEV_ENTRY_PPR; } =20 - set_dte_entry_v2(iommu, domain, gcr3_tbl, &pte_root, &flags); + dom =3D udomain ? udomain : domain; + set_dte_entry_v2(iommu, dom, gcr3_tbl, &pte_root, &flags); =20 if ((domain->flags & PD_IOMMUV2_MASK) && amd_iommu_gpt_level =3D=3D PAGE_MODE_5_LEVEL) { @@ -1688,7 +1691,7 @@ static void do_attach(struct iommu_dev_data *dev_data, domain->dev_cnt +=3D 1; =20 /* Update device table */ - set_dte_entry(iommu, dev_data->devid, domain, domain->gcr3_tbl, + set_dte_entry(iommu, dev_data->devid, domain, NULL, domain->gcr3_tbl, ats, dev_data->iommu_v2); clone_aliases(iommu, dev_data->dev); =20 @@ -1967,7 +1970,7 @@ static void update_device_table(struct protection_dom= ain *domain) =20 if (!iommu) continue; - set_dte_entry(iommu, dev_data->devid, domain, domain->gcr3_tbl, + set_dte_entry(iommu, dev_data->devid, domain, NULL, domain->gcr3_tbl, dev_data->ats.enabled, dev_data->iommu_v2); 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Wed, 21 Jun 2023 23:55:50 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9D4.mail.protection.outlook.com (10.167.241.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6521.21 via Frontend Transport; Wed, 21 Jun 2023 23:55:50 +0000 Received: from ruby-95f9host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Wed, 21 Jun 2023 18:55:49 -0500 From: Suravee Suthikulpanit To: , , CC: , , , , , , , , , , , , , , , "Suravee Suthikulpanit" Subject: [RFC PATCH 08/21] iommu/amd: Allow nested IOMMU page tables Date: Wed, 21 Jun 2023 18:54:55 -0500 Message-ID: <20230621235508.113949-9-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> References: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D4:EE_|BL1PR12MB5302:EE_ X-MS-Office365-Filtering-Correlation-Id: f84711e7-3783-4837-3b31-08db72b30acb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 23:55:50.7766 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f84711e7-3783-4837-3b31-08db72b30acb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5302 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The GCR3 table contains guest CR3 registers, and it is used to setup guest page tables. Current logic only allow guest CR3 table setup only when the host table is not setup (i.e. PAGE_MODE_NONE). Therefore, only 1-level page translation is allowed (e.g. host only vs. guest only). Remove this restriction to allow nested page table setup. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/iommu.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 333c8a4831be..c23f99ebdffc 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2531,12 +2531,12 @@ int amd_iommu_domain_enable_v2(struct iommu_domain = *dom, int pasids, bool giov) spin_lock_irqsave(&pdom->lock, flags); =20 /* - * Save us all sanity checks whether devices already in the - * domain support IOMMUv2. Just force that the domain has no - * devices attached when it is switched into IOMMUv2 mode. + * With nested page table, we can enable * v2 (i.e GCR3) + * on a existing domain. Therefore, only check if domain + * already enable v2. */ ret =3D -EBUSY; - if (pdom->dev_cnt > 0 || pdom->flags & PD_IOMMUV2_MASK) + if (pdom->flags & PD_IOMMUV2_MASK) goto out; =20 if (!pdom->gcr3_tbl) @@ -2688,9 +2688,6 @@ static int __set_gcr3(struct protection_domain *domai= n, u32 pasid, { u64 *pte; =20 - if (domain->iop.mode !=3D PAGE_MODE_NONE) - return -EINVAL; - pte =3D __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); if (pte =3D=3D NULL) return -ENOMEM; --=20 2.34.1 From nobody Sun Feb 8 05:19:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A6FFEB64D8 for ; Wed, 21 Jun 2023 23:56:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229729AbjFUX4T (ORCPT ); Wed, 21 Jun 2023 19:56:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230089AbjFUXz6 (ORCPT ); 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Wed, 21 Jun 2023 18:55:50 -0500 From: Suravee Suthikulpanit To: , , CC: , , , , , , , , , , , , , , , "Suravee Suthikulpanit" Subject: [RFC PATCH 09/21] iommu/amd: Add support for hw_info for iommu capability query Date: Wed, 21 Jun 2023 18:54:56 -0500 Message-ID: <20230621235508.113949-10-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> References: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D4:EE_|BY5PR12MB4163:EE_ X-MS-Office365-Filtering-Correlation-Id: 9555c499-7111-4111-4358-08db72b30bd6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: SXdP8JRmtUCCodN7DF4QalKVNOFfxQ+icg6IrcJPCynEHNz4BBYDrEkJGO5GQj/768kgIrb5pdbJt+olgH0SPhhdHv13+K0gKBM7r5p5PK31Uqyl1STutqV08QcLxGwZZGqIPOM4huBqLMMPQZHVglHQjNN6TEPxv/Z9pfZYrLbE8pbUKhtAwCqBoAC34Yroa/h0kO03SYzyxU8AGwqnO/H30w13wx2QOXQnzCxk3Qep5hFRULKWh8PSmBetZlTj6a8UPs+yOfI7JrxgbQEeFRwVBfnLGv0uNgY+hti5dfUhv0E0p1/ZKeD+1v7ar3LctHqMHFVy7XW3azNGd6uh4aHrHCtQAaVXAWoNxsqPYk7xxM8lUPNeMYS7EzXeH+EhMF8u0PwinThm2oUlrUtdCQcu8tIGOLMHeZNxmTf3nCJk06wQJYScZX5mmepXRepvkeP0pgqxTAkpDiv/A4OTZ9eNQXfYVcG/rlHHp7YmlBqMqMKnHmKK9z6/9aQq5iLVyGsnUcLYcrsdTOHHRQkHzfDn1LyRdkUmNjqyRfpfXYe1upa6lpGGYzLflLoyu+Lp1PN5iC+AUh6nsLmfoJwoKdYPAP4xkf9wplbFeOEHGb4PCasEbDv+DuK4VnRD788HJ49PB6P9sw85nFxZ2mUNOvobxq/vXKaFzWblfpeIrEF5s5nlb48TKsk0+m+xsz4z4qW4LqMYGuAFkcVpRphN5IR/M7OHOjwrnnpqezqE+4yBHoHj9OQ2MiQTRKR2DD6W7Y4F6pEaTRDuFA8ByKoulg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(396003)(136003)(376002)(346002)(451199021)(40470700004)(46966006)(36840700001)(36860700001)(36756003)(82310400005)(40460700003)(81166007)(356005)(70206006)(5660300002)(44832011)(7416002)(41300700001)(8936002)(86362001)(4326008)(8676002)(316002)(40480700001)(82740400003)(70586007)(47076005)(426003)(26005)(1076003)(2616005)(16526019)(186003)(2906002)(7696005)(336012)(478600001)(110136005)(54906003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 23:55:52.5267 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9555c499-7111-4111-4358-08db72b30bd6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4163 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" AMD IOMMU Extended Feature(2) Register (EFR/EFR2) specifies features supported by each IOMMU hardware instance. The IOMMU driver checks each feature-specific bits before enabling each feature at run time. For hardware-assisted vIOMMU, the hypervisor determines which IOMMU features to supported in the guest, and communicates this information to user-space (e.g. QEMU) via iommufd IOMMU_DEVICE_GET_HW_INFO ioctl. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 2 ++ drivers/iommu/amd/amd_iommu_types.h | 3 +++ drivers/iommu/amd/iommu.c | 37 +++++++++++++++++++++++++++++ include/uapi/linux/iommufd.h | 11 +++++++++ 4 files changed, 53 insertions(+) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index d36a39796c2f..c9dfa4734801 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -84,6 +84,8 @@ extern int amd_iommu_domain_set_gcr3(struct iommu_domain = *dom, u32 pasid, unsigned long cr3); extern int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid= ); =20 +extern void amd_iommu_build_efr(u64 *efr, u64 *efr2); + #ifdef CONFIG_IRQ_REMAP extern int amd_iommu_create_irq_domain(struct amd_iommu *iommu); #else diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 09df25779fe9..8830f511bee4 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -98,12 +98,15 @@ #define FEATURE_EPHSUP (1ULL<<50) #define FEATURE_SNP (1ULL<<63) =20 +#define FEATURE_GATS_5LEVEL 1ULL #define FEATURE_GATS_SHIFT 12 #define FEATURE_GATS_MASK (0x03ULL << FEATURE_GATS_SHIFT) =20 +#define FEATURE_GLX_3LEVEL 0ULL #define FEATURE_GLX_SHIFT 14 #define FEATURE_GLX_MASK (0x03ULL << FEATURE_GLX_SHIFT) =20 +#define FEATURE_PASMAX_16 0xFULL #define FEATURE_PASMAX_SHIFT 32 #define FEATURE_PASMAX_MASK (0x1FULL << FEATURE_PASMAX_SHIFT) =20 diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index c23f99ebdffc..4a42af85664e 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2435,8 +2435,45 @@ static bool amd_iommu_enforce_cache_coherency(struct= iommu_domain *domain) return true; } =20 +void amd_iommu_build_efr(u64 *efr, u64 *efr2) +{ + if (efr) { + *efr =3D (FEATURE_GT | FEATURE_GIOSUP); + + /* 5-level v2 page table support */ + *efr |=3D ((FEATURE_GATS_5LEVEL << FEATURE_GATS_SHIFT) & + FEATURE_GATS_MASK); + + /* 3-level GCR3 table support */ + *efr |=3D ((FEATURE_GLX_3LEVEL << FEATURE_GLX_SHIFT) & + FEATURE_GLX_MASK); + + /* 16-bit PASMAX support */ + *efr |=3D ((FEATURE_PASMAX_16 << FEATURE_PASMAX_SHIFT) & + FEATURE_PASMAX_MASK); + } + + if (efr2) + *efr2 =3D 0; +} + +static void *amd_iommu_hw_info(struct device *dev, u32 *length) +{ + struct iommu_hw_info_amd *hwinfo; + + hwinfo =3D kzalloc(sizeof(*hwinfo), GFP_KERNEL); + if (!hwinfo) + return ERR_PTR(-ENOMEM); + + *length =3D sizeof(*hwinfo); + + amd_iommu_build_efr(&hwinfo->efr, &hwinfo->efr2); + return hwinfo; +} + const struct iommu_ops amd_iommu_ops =3D { .capable =3D amd_iommu_capable, + .hw_info =3D amd_iommu_hw_info, .domain_alloc =3D amd_iommu_domain_alloc, .probe_device =3D amd_iommu_probe_device, .release_device =3D amd_iommu_release_device, diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index ec870e2d32fd..f8ea9faf6770 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -508,6 +508,17 @@ struct iommu_hw_info_smmuv3 { __u32 idr[6]; }; =20 +/** + * struct iommu_hw_info_amd - AMD IOMMU device info + * + * @efr : Value of AMD IOMMU Extended Feature Register (EFR) + * @efr2: Value of AMD IOMMU Extended Feature 2 Register (EFR2) + */ +struct iommu_hw_info_amd { + __u64 efr; + __u64 efr2; +}; + /** * enum iommu_hw_info_type - IOMMU Hardware Info Types * @IOMMU_HW_INFO_TYPE_INTEL_VTD: Intel VT-d iommu info type --=20 2.34.1 From nobody Sun Feb 8 05:19:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E28BEB64D8 for ; Wed, 21 Jun 2023 23:56:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230128AbjFUX4e (ORCPT ); Wed, 21 Jun 2023 19:56:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230107AbjFUXz7 (ORCPT ); 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Wed, 21 Jun 2023 18:55:51 -0500 From: Suravee Suthikulpanit To: , , CC: , , , , , , , , , , , , , , , "Suravee Suthikulpanit" Subject: [RFC PATCH 10/21] iommu/amd: Introduce vIOMMU-specific events and event info Date: Wed, 21 Jun 2023 18:54:57 -0500 Message-ID: <20230621235508.113949-11-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> References: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D4:EE_|CY8PR12MB7337:EE_ X-MS-Office365-Filtering-Correlation-Id: 1a412335-fbd6-45bd-5fd5-08db72b30cd5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Xa18HEMfdNdkm+uq4BS9+eAkt9R6wUNH//HHw4LsXJYrwRnMfP0nABxVHjdDhazqu8Hth09N95IS1pQIH9z2aigxeLFa+F9/yBokBYN5PfgJWUJzCLY8tHuyntZCIR3vUkl5O4UX6y0KqK1dYYIeozoVkWpd3Y5wUNi2mBVYB8DZuh9i6K1Or3CwdC+6ZQogOdZLi7frjpU7vuRV9fByrYo4f1OCExSkKrffdrZNlCSI87s74TwatCPiakzKLdWhy2x8w/+y1qYeH3Jp4YuM3xfY8Z9z0+2lniV/pP5O3RuTo9C5/q9VcG+msLgjmSh7GDSU6w7DHvDZ4BS+7SlMv9wnkMuUhd+4OizGUMmIdDaXw0qtdWwwKhNkV1UwF/UW4E/IbBpSvAbbPyW412aM8aO5DcZTCJQgj/aFh9AL4AxIvnpl3V/jAckLrN84N45gQHkWvPMgkuvcv25Ck8/CiU7nRhIg8uOr8WkkpxCKUeCFlZNMMMZHJjJN+B7VNLIRJHZ/odhVjyuejCPIlXzj8gMc2ad3pJL3mCtqBeMgjnoSDLsM1ZTNuiyjfLdcBYQBWetYBB2jZ/7VinkY8pwGPg1zKnA1OyOEbuLkQe2we9GXJ66m1O+3K0fzQpoTEJdNXYP/OsDCv5IyajFp84Hjana2lJ5VHsvmefPGc/beZwb/eDmyxiSZyh6L4UsWZmd3mM8PUxodsj+zja1GXtWnQYtydbInD5ncVoTKNkZ6FwSR0PsrpcwYt8YFlRmHP0/eduKAFwTuaqHTzSGFrLZQrA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(396003)(136003)(376002)(346002)(451199021)(40470700004)(36840700001)(46966006)(54906003)(7696005)(478600001)(110136005)(70206006)(70586007)(16526019)(26005)(186003)(1076003)(2906002)(82310400005)(8676002)(4326008)(41300700001)(5660300002)(44832011)(8936002)(7416002)(316002)(356005)(81166007)(82740400003)(86362001)(36756003)(40460700003)(47076005)(336012)(83380400001)(2616005)(36860700001)(40480700001)(426003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 23:55:54.1986 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1a412335-fbd6-45bd-5fd5-08db72b30cd5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7337 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Adding support for new vIOMMU events: * Guest Event Fault event * vIOMMU Hardware Error event Also, adding support for the additional vIOMMU related flags in existing events. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu_types.h | 3 ++ drivers/iommu/amd/iommu.c | 58 ++++++++++++++++++++++------- 2 files changed, 48 insertions(+), 13 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 8830f511bee4..d832e0c36a21 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -145,6 +145,9 @@ #define EVENT_TYPE_IOTLB_INV_TO 0x7 #define EVENT_TYPE_INV_DEV_REQ 0x8 #define EVENT_TYPE_INV_PPR_REQ 0x9 +#define EVENT_TYPE_GUEST_EVENT_FAULT 0xb +#define EVENT_TYPE_VIOMMU_HW_ERR 0xc + #define EVENT_TYPE_RMP_FAULT 0xd #define EVENT_TYPE_RMP_HW_ERR 0xe #define EVENT_DEVID_MASK 0xffff diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 4a42af85664e..efced59ba8a5 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -541,7 +541,7 @@ static void amd_iommu_report_rmp_fault(struct amd_iommu= *iommu, volatile u32 *ev =20 static void amd_iommu_report_page_fault(struct amd_iommu *iommu, u16 devid, u16 domain_id, - u64 address, int flags) + u64 address, int flags, u8 vflags) { struct iommu_dev_data *dev_data =3D NULL; struct pci_dev *pdev; @@ -576,13 +576,13 @@ static void amd_iommu_report_page_fault(struct amd_io= mmu *iommu, } =20 if (__ratelimit(&dev_data->rs)) { - pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=3D0x%04x address=3D0x= %llx flags=3D0x%04x]\n", - domain_id, address, flags); + pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=3D0x%04x address=3D0x= %llx flags=3D0x%04x vflags=3D%#x]\n", + domain_id, address, flags, vflags); } } else { - pr_err_ratelimited("Event logged [IO_PAGE_FAULT device=3D%04x:%02x:%02x.= %x domain=3D0x%04x address=3D0x%llx flags=3D0x%04x]\n", + pr_err_ratelimited("Event logged [IO_PAGE_FAULT device=3D%04x:%02x:%02x.= %x domain=3D0x%04x address=3D0x%llx flags=3D0x%04x vflags=3D%#x]\n", iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid= ), - domain_id, address, flags); + domain_id, address, flags, vflags); } =20 out: @@ -618,28 +618,41 @@ static void iommu_print_event(struct amd_iommu *iommu= , void *__evt) } =20 if (type =3D=3D EVENT_TYPE_IO_FAULT) { - amd_iommu_report_page_fault(iommu, devid, pasid, address, flags); + u8 vflags =3D (event[0] >> 27) & 0x1F; + + amd_iommu_report_page_fault(iommu, devid, pasid, address, flags, vflags); return; } =20 switch (type) { case EVENT_TYPE_ILL_DEV: - dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=3D%04x:%02x:%= 02x.%x pasid=3D0x%05x address=3D0x%llx flags=3D0x%04x]\n", + { + u8 vflags =3D (event[0] >> 27) & 0x1F; + + dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY deice=3D%04x:%02x:%0= 2x.%x pasid=3D0x%05x address=3D0x%llx flags=3D0x%04x vflags=3D%#x]\n", iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid= ), - pasid, address, flags); + pasid, address, flags, vflags); dump_dte_entry(iommu, devid); break; + } case EVENT_TYPE_DEV_TAB_ERR: - dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=3D%04x:%02x:%0= 2x.%x " - "address=3D0x%llx flags=3D0x%04x]\n", + { + u8 vflags =3D (event[0] >> 27) & 0x1F; + + dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=3D%04x:%02x:%0= 2x.%x address=3D%#llx flags=3D%#04x vlfags=3D%#x]\n", iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid= ), - address, flags); + address, flags, vflags); break; + } case EVENT_TYPE_PAGE_TAB_ERR: - dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=3D%04x:%02x:%= 02x.%x pasid=3D0x%04x address=3D0x%llx flags=3D0x%04x]\n", + { + u8 vflags =3D (event[0] >> 27) & 0x1F; + + dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=3D%04x:%02x:%= 02x.%x pasid=3D0x%04x address=3D0x%llx flags=3D0x%04x vflags=3D%#x]\n", iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid= ), - pasid, address, flags); + pasid, address, flags, vflags); break; + } case EVENT_TYPE_ILL_CMD: dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=3D0x%llx]\n", = address); dump_command(address); @@ -671,6 +684,25 @@ static void iommu_print_event(struct amd_iommu *iommu,= void *__evt) iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid= ), pasid, address, flags, tag); break; + case EVENT_TYPE_GUEST_EVENT_FAULT: + { + u8 gid =3D event[1] & 0xFFFF; + u8 vflags =3D (event[0] >> 27) & 0x1F; + + dev_err(dev, "Event logged [GUEST_EVENT_FAULT gid=3D#%x flags=3D0x%04x v= flags=3D%#x]\n", + gid, flags, vflags); + break; + } + case EVENT_TYPE_VIOMMU_HW_ERR: + { + u16 gid =3D event[0] & 0xFFFF; + u8 src =3D (event[0] >> 16) & 0x3; + u8 vflags =3D (event[0] >> 27) & 0x1F; + + dev_err(dev, "Event logged [VIOMMU_HW_ERR gid=3D%#x address=3D%#llx src= =3D%#x flags=3D%#x vflags=3D%#x]\n", + gid, address, src, flags, vflags); + break; + } default: dev_err(dev, "Event logged [UNKNOWN event[0]=3D0x%08x event[1]=3D0x%08x = event[2]=3D0x%08x event[3]=3D0x%08x\n", event[0], event[1], event[2], event[3]); --=20 2.34.1 From nobody Sun Feb 8 05:19:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31A45EB64D7 for ; Wed, 21 Jun 2023 23:56:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229692AbjFUX4c (ORCPT ); Wed, 21 Jun 2023 19:56:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230106AbjFUXz7 (ORCPT ); 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Wed, 21 Jun 2023 18:55:52 -0500 From: Suravee Suthikulpanit To: , , CC: , , , , , , , , , , , , , , , "Suravee Suthikulpanit" Subject: [RFC PATCH 11/21] iommu/amd: Introduce Reset vMMIO Command Date: Wed, 21 Jun 2023 18:54:58 -0500 Message-ID: <20230621235508.113949-12-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> References: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D4:EE_|SJ0PR12MB5485:EE_ X-MS-Office365-Filtering-Correlation-Id: 9087e2a9-a382-4fbe-7ff5-08db72b30d77 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: YQtQyBvuxD49C4F+5hqCn4CWDuqFS6AnbNSPrSiqboIWpw8tjxTqpoOO1Vy8Rot+p6blqnaUQrTYMobO6Z0DR7UeQPCAdCNP9jmhoSxBWZ9ElSqamYGTym/6Xrw8coeULIqTyNMYzlxelxcWfwaejiHn1bbwNWVgBhn3qVRIW1Jgl0HInzDADGs3jPdSvb9FhF5nUb85GdbWF8WM27StfgjbCloe3drgpk9CyZYypE4B1D+/yP4xHnE49ONDqwH5P+SKZQUyaIauS7WDY2OAn7cEapfqJ8tpBmBYfGE6xbmEO2ZptQdGiX3Mo4ydjxpcr3pDkrii8U9gmsTtAbrM0QesWY33Zl3E+gKGe6ibc+PVJbYY3sieViVkpSyg+jvJc2T/YgIxB9y31TxATq3udvjhysCN+5KUFFVF4o2x3yDlRmeyTzgum3eFrW9q/Ymvn5Fjr09g26xDtU9vWf3GH4bvtH3VPs7UxoqYKaCfn+N3xgOHeZLEGrxxW7hlk/EheGJf2y5wCjjfye22dLMVkfbk2qZodQ6HurXNoQbOgFWyTYkt7BK8zD8tNjPvPoyzN3zxSIhWzqKa0C2tbQzazJK7JQs4/QhmwlmvuAuv0wqvP1EKZcLA+D9OuEHmhPOq4rY3tUA4V6Gy7FGXVxX3YccLgU7U35IfEGLoibYbsopCEZPEVjvjb5jGq+h4W0I8sbxxRCSOqPKejcFZxQvtw6z9ScoQzy6z+v5SeBTGbI0fkZFxzGl72Xa2c0yBHHYk7KRTVM4sLoDRXVAykojTJg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(396003)(39860400002)(346002)(136003)(451199021)(46966006)(36840700001)(40470700004)(40480700001)(7696005)(110136005)(478600001)(26005)(54906003)(4326008)(36860700001)(186003)(1076003)(16526019)(82310400005)(70586007)(70206006)(41300700001)(356005)(5660300002)(7416002)(8936002)(8676002)(44832011)(82740400003)(81166007)(316002)(40460700003)(86362001)(47076005)(426003)(336012)(2616005)(36756003)(2906002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 23:55:55.2611 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9087e2a9-a382-4fbe-7ff5-08db72b30d77 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5485 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce new IOMMU commands for vIOMMU for resetting virtualized MMIO registers of a particular guest. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu_types.h | 1 + drivers/iommu/amd/iommu.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index d832e0c36a21..aa16a7079b5c 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -200,6 +200,7 @@ #define CMD_INV_IRT 0x05 #define CMD_COMPLETE_PPR 0x07 #define CMD_INV_ALL 0x08 +#define CMD_RESET_VMMIO 0x0A =20 #define CMD_COMPL_WAIT_STORE_MASK 0x01 #define CMD_COMPL_WAIT_INT_MASK 0x02 diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index efced59ba8a5..b5c62bc8249c 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -1133,6 +1133,18 @@ static void build_inv_irt(struct iommu_cmd *cmd, u16= devid) CMD_SET_TYPE(cmd, CMD_INV_IRT); } =20 +static void build_reset_vmmio(struct iommu_cmd *cmd, u16 guestId, + bool vcmd, bool all) +{ + memset(cmd, 0, sizeof(*cmd)); + cmd->data[0] =3D guestId; + if (all) + cmd->data[0] |=3D (1 << 28); + if (vcmd) + cmd->data[0] |=3D (1 << 31); + CMD_SET_TYPE(cmd, CMD_RESET_VMMIO); +} + /* * Writes the command to the IOMMUs command buffer and informs the * hardware about the new command. @@ -1315,6 +1327,16 @@ void iommu_flush_all_caches(struct amd_iommu *iommu) } } =20 +void iommu_reset_vmmio(struct amd_iommu *iommu, u16 guestId) +{ + struct iommu_cmd cmd; + + build_reset_vmmio(&cmd, guestId, 1, 1); + + iommu_queue_command(iommu, &cmd); + iommu_completion_wait(iommu); +} + /* * Command send function for flushing on-device TLB */ --=20 2.34.1 From nobody Sun Feb 8 05:19:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFEB3EB64D7 for ; Wed, 21 Jun 2023 23:56:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229943AbjFUX4i (ORCPT ); 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Wed, 21 Jun 2023 18:55:53 -0500 From: Suravee Suthikulpanit To: , , CC: , , , , , , , , , , , , , , , "Suravee Suthikulpanit" Subject: [RFC PATCH 12/21] iommu/amd: Introduce AMD vIOMMU-specific UAPI Date: Wed, 21 Jun 2023 18:54:59 -0500 Message-ID: <20230621235508.113949-13-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> References: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D4:EE_|SA0PR12MB4560:EE_ X-MS-Office365-Filtering-Correlation-Id: 65208709-462b-44ff-9034-08db72b30dc8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ky6UDFtn0ptih9xO7AaC5pH083ReWvflDIojiTAbYoWtzrFM5V45f/DwauxL2imB+Loy5Qdf3JWo3MqWgajdX65kSLpeP7k20cWfTZXxxQsjcproKInUTerGNZl/UQemiuPP0qI3t21AkV8ZP5JRqjeCnaOEi2HWV2Qq+2guaqYsGyYajTWXCI8eZd/yHIUtZeQ8cv35b6j8d3qtKP29/PD3KWWIZPRmKv6bJDKwpjxPKvRR1FXwAGPxlDam+E4cnOs35fcYoDQVyWSLA6/rAfbcZk9eZsMfMH9MYyWeEatiy5t/6i3rZu6o5GVP0NmqXOtqmOgCzP6Ij5CzkxQmKBouOuq2ekwyP2WQeNbUDzqflds3vFexyn95B1bBdXnWPmJ2/Gj5VQqnB6c8YazsFwJa5l2CnPiRl7g+LQ/SGfer73ZGBtaAvU/YosWUpPtUjhkm9qRMnOojVbGJ/cTe+pT3OlpGc+koN1pRIysH0d74xuxfBbftU8Z6THGn378TefzIiaOHxNQ0pZeINkhk35rh76NUOy/Ye5gBxZQzwkDlzic2WyJF7vZPbJpwRLgq6ohKadoJe3kJ+Zkws/KyXRdQAwdy/Cwm+yn5LtbKq/7TG0J8nsprwykyU0AgMwrnJrku3ELtHPvsp2Jg64yLLmfvdg/ryorQM8WWYmHPrQIE+6quats8juhJ9khk/3eoU7aBER9ERDK5MrZm9XiRl60hfGps9Rtn+dpnGPLMRDzqooCd6s2hpeC5jSwz7H3HdFNvQ0Y9kGPV6nhpcxA7MtZ8kSd41R6pnWlunYz90E+ivpi9Fc/WJbVOMixIr5Bu X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(39860400002)(396003)(346002)(136003)(451199021)(36840700001)(40470700004)(46966006)(54906003)(110136005)(478600001)(4326008)(26005)(16526019)(186003)(1076003)(70586007)(2906002)(82310400005)(7696005)(41300700001)(7416002)(8936002)(70206006)(8676002)(44832011)(5660300002)(316002)(82740400003)(356005)(81166007)(2616005)(86362001)(36756003)(40480700001)(47076005)(426003)(336012)(83380400001)(36860700001)(40460700003)(71600200004)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 23:55:55.7923 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 65208709-462b-44ff-9034-08db72b30dc8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4560 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To handle various operations necessary for setting up the vIOMMU hardware. These operations are specific to AMD hardware. Signed-off-by: Suravee Suthikulpanit --- include/uapi/linux/amd_viommu.h | 145 ++++++++++++++++++++++++++++++++ 1 file changed, 145 insertions(+) create mode 100644 include/uapi/linux/amd_viommu.h diff --git a/include/uapi/linux/amd_viommu.h b/include/uapi/linux/amd_viomm= u.h new file mode 100644 index 000000000000..f4a91ecd5dc2 --- /dev/null +++ b/include/uapi/linux/amd_viommu.h @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * AMD Hardwaer Accelerated Virtualized IOMMU (HW-vIOMMU) + * + * Copyright (c) 2023, Advanced Micro Devices, Inc. + * + */ +#ifndef _UAPI_AMD_VIOMMU_H_ +#define _UAPI_AMD_VIOMMU_H_ + +#include +#include + +/** + * The ioctl interfaces in this file are specific for AMD HW-vIOMMU. + * They are an extension of extend the IOMMUFD ioctl interfaces. + * Please see include/uapi/linux/iommufd.h for more detail. + */ +#include + +enum iommufd_viommu_cmd { + IOMMUFD_VIOMMU_CMD_BASE =3D 0x60, + IOMMUFD_CMD_IOMMU_INIT =3D IOMMUFD_VIOMMU_CMD_BASE, + IOMMUFD_CMD_IOMMU_DESTROY, + IOMMUFD_CMD_DEVICE_ATTACH, + IOMMUFD_CMD_DEVICE_DETACH, + IOMMUFD_CMD_DOMAIN_ATTACH, + IOMMUFD_CMD_DOMAIN_DETACH, + IOMMUFD_CMD_MMIO_ACCESS, + IOMMUFD_CMD_CMDBUF_UPDATE, +}; + +/** + * struct amd_viommu_iommu_info - ioctl(VIOMMU_IOMMU_[INIT|DESTROY]) + * @size: sizeof(struct amd_viommu_iommu_info) + * @iommu_id: PCI device ID of the AMD IOMMU instance + * @gid: guest ID + * + * Initialize and destroy AMD HW-vIOMMU instances for the specified + * guest ID. + */ +struct amd_viommu_iommu_info { + __u32 size; + __u32 iommu_id; + __u32 gid; +}; +#define VIOMMU_IOMMU_INIT _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOMMU_INIT) +#define VIOMMU_IOMMU_DESTROY _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOMMU_DESTROY) + +/** + * struct amd_viommu_dev_info - ioctl(VIOMMU_DEVICE_[ATTACH|DETACH]) + * @size: sizeof(struct amd_viommu_dev_info) + * @iommu_id: PCI device ID of the AMD IOMMU instance + * @gid: guest ID + * @hdev_id: host PCI device ID + * @gdev_id: guest PCI device ID + * @queue_id: guest PCI device queue ID + * + * Attach / Detach PCI device to a HW-vIOMMU instance, and program + * the IOMMU Device ID mapping table for the specified guest. + */ +struct amd_viommu_dev_info { + __u32 size; + __u32 iommu_id; + __u32 gid; + __u16 hdev_id; + __u16 gdev_id; + __u16 queue_id; +}; + +#define VIOMMU_DEVICE_ATTACH _IO(IOMMUFD_TYPE, IOMMUFD_CMD_DEVICE_ATTACH) +#define VIOMMU_DEVICE_DETACH _IO(IOMMUFD_TYPE, IOMMUFD_CMD_DEVICE_DETACH) + +/** + * struct amd_viommu_dom_info - ioctl(VIOMMU_DOMAIN_[ATTACH|DETACH]) + * @size: sizeof(struct amd_viommu_dom_info) + * @iommu_id: PCI device ID of the AMD IOMMU instance + * @gid: guest ID + * @hdev_id: host PCI device ID + * @gdev_id: guest PCI device ID + * @gdom_id: guest domain ID + * + * Attach / Detach domain of a PCI device to a HW-vIOMMU instance, and pro= gram + * the IOMMU Domain ID mapping table for the specified guest. + */ +struct amd_viommu_dom_info { + __u32 size; + __u32 iommu_id; + __u32 gid; + __u16 gdev_id; + __u16 gdom_id; +}; + +#define VIOMMU_DOMAIN_ATTACH _IO(IOMMUFD_TYPE, IOMMUFD_CMD_DOMAIN_ATTACH) +#define VIOMMU_DOMAIN_DETACH _IO(IOMMUFD_TYPE, IOMMUFD_CMD_DOMAIN_DETACH) + +/** + * struct amd_viommu_mmio_data- ioctl(VIOMMU_MMIO_ACCESS) + * @size: sizeof(struct amd_viommu_mmio_data) + * @iommu_id: PCI device ID of the AMD IOMMU instance + * @gid: guest ID + * @offset: specify MMIO offset + * @value: specify MMIO write value or retrieving MMIO read value + * @mmio_size: specify MMIO size + * @is_write: specify MMIO read (0) / write (1) + * + * - Trap guest IOMMU MMIO write to program HW-vIOMMU for the specified + * guest. + * - Trap guest IOMMU MMIO read to emulate return value for the specified + * guest. + */ +struct amd_viommu_mmio_data { + __u32 size; + __u32 iommu_id; + __u32 gid; + __u32 offset; + __u64 value; + __u32 mmio_size; + __u8 is_write; +}; + +#define VIOMMU_MMIO_ACCESS _IO(IOMMUFD_TYPE, IOMMUFD_CMD_MMIO_ACCESS) + +/** + * struct amd_viommu_cmdbuf_data - ioctl(VIOMMU_CMDBUF_UPDATE) + * @size: sizeof(struct amd_viommu_cmdbuf_data) + * @iommu_id: PCI device ID of the AMD IOMMU instance + * @gid: guest ID + * @gcmdbuf_size: guest command buffer size + * @hva: host virtual address for the guest command buffer + * + * Trap guest command buffer initialization to setup HW-vIOMMU command buf= fer + * for the specified guest. + */ +struct amd_viommu_cmdbuf_data { + __u32 size; + __u32 iommu_id; + __u32 gid; + __u32 cmdbuf_size; + __u64 hva; +}; + +#define VIOMMU_CMDBUF_UPDATE _IO(IOMMUFD_TYPE, IOMMUFD_CMD_CMDBUF_UPDATE) + +#endif --=20 2.34.1 From nobody Sun Feb 8 05:19:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 793DBEB64D7 for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9D4.mail.protection.outlook.com (10.167.241.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6521.21 via Frontend Transport; Wed, 21 Jun 2023 23:55:56 +0000 Received: from ruby-95f9host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Wed, 21 Jun 2023 18:55:54 -0500 From: Suravee Suthikulpanit To: , , CC: , , , , , , , , , , , , , , , "Suravee Suthikulpanit" Subject: [RFC PATCH 13/21] iommu/amd: Introduce vIOMMU command-line option Date: Wed, 21 Jun 2023 18:55:00 -0500 Message-ID: <20230621235508.113949-14-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> References: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D4:EE_|MN2PR12MB4285:EE_ X-MS-Office365-Filtering-Correlation-Id: 906e513c-5a50-4fcc-3e1e-08db72b30e17 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 23:55:56.3080 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 906e513c-5a50-4fcc-3e1e-08db72b30e17 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4285 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To disable vIOMMU feature, specify option "amd_iommu=3Dviommu_disable". Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 2 ++ drivers/iommu/amd/amd_iommu_types.h | 1 + drivers/iommu/amd/init.c | 10 ++++++++++ 3 files changed, 13 insertions(+) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index c9dfa4734801..a65d22384ab8 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -46,6 +46,8 @@ void amd_iommu_debugfs_setup(struct amd_iommu *iommu); static inline void amd_iommu_debugfs_setup(struct amd_iommu *iommu) {} #endif =20 +extern bool amd_iommu_viommu; + /* Needed for interrupt remapping */ extern int amd_iommu_prepare(void); extern int amd_iommu_enable(void); diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index aa16a7079b5c..019a9182df87 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -96,6 +96,7 @@ #define FEATURE_GAM_VAPIC (1ULL<<21) #define FEATURE_GIOSUP (1ULL<<48) #define FEATURE_EPHSUP (1ULL<<50) +#define FEATURE_VIOMMU (1ULL<<55) #define FEATURE_SNP (1ULL<<63) =20 #define FEATURE_GATS_5LEVEL 1ULL diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 6a045a187971..4dd9f09e16c4 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -194,6 +194,9 @@ bool amdr_ivrs_remap_support __read_mostly; =20 bool amd_iommu_force_isolation __read_mostly; =20 +/* VIOMMU enabling flag */ +bool amd_iommu_viommu =3D true; + /* * AMD IOMMU allows up to 2^16 different protection domains. This is a bit= map * to know which ones are already in use. @@ -2154,6 +2157,9 @@ static void print_iommu_info(void) if (iommu->features & FEATURE_SNP) pr_cont(" SNP"); =20 + if (iommu->features & FEATURE_VIOMMU) + pr_cont(" vIOMMU"); + pr_cont("\n"); } } @@ -2166,6 +2172,8 @@ static void print_iommu_info(void) pr_info("V2 page table enabled (Paging mode : %d level)\n", amd_iommu_gpt_level); } + if (amd_iommu_viommu) + pr_info("AMD-Vi: vIOMMU enabled\n"); } =20 static int __init amd_iommu_init_pci(void) @@ -3402,6 +3410,8 @@ static int __init parse_amd_iommu_options(char *str) amd_iommu_pgtable =3D AMD_IOMMU_V1; } else if (strncmp(str, "pgtbl_v2", 8) =3D=3D 0) { amd_iommu_pgtable =3D AMD_IOMMU_V2; + } else if (strncmp(str, "viommu_disable", 14) =3D=3D 0) { + amd_iommu_viommu =3D false; } else { pr_notice("Unknown option - '%s'\n", str); } --=20 2.34.1 From nobody Sun Feb 8 05:19:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2514EB64D8 for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 23:55:57.0267 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ab321304-2be8-4053-eaa2-08db72b30e84 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR12MB5460 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Initialing vIOMMU private address space regions includes parsing PCI vendor-specific capability (VSC), and use information to setup vIOMMU private address space regions. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/Makefile | 2 +- drivers/iommu/amd/amd_iommu_types.h | 40 +++++ drivers/iommu/amd/amd_viommu.h | 57 +++++++ drivers/iommu/amd/init.c | 3 + drivers/iommu/amd/viommu.c | 227 ++++++++++++++++++++++++++++ 5 files changed, 328 insertions(+), 1 deletion(-) create mode 100644 drivers/iommu/amd/amd_viommu.h create mode 100644 drivers/iommu/amd/viommu.c diff --git a/drivers/iommu/amd/Makefile b/drivers/iommu/amd/Makefile index 773d8aa00283..89c045716448 100644 --- a/drivers/iommu/amd/Makefile +++ b/drivers/iommu/amd/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_AMD_IOMMU) +=3D iommu.o init.o quirks.o io_pgtable.o io_pgtab= le_v2.o +obj-$(CONFIG_AMD_IOMMU) +=3D iommu.o init.o quirks.o io_pgtable.o io_pgtab= le_v2.o viommu.o obj-$(CONFIG_AMD_IOMMU_DEBUGFS) +=3D debugfs.o obj-$(CONFIG_AMD_IOMMU_V2) +=3D iommu_v2.o diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 019a9182df87..5cb5a709b31b 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -34,6 +34,17 @@ #define MMIO_RANGE_OFFSET 0x0c #define MMIO_MISC_OFFSET 0x10 =20 +/* vIOMMU Capability offsets (from IOMMU Capability Header) */ +#define MMIO_VSC_HDR_OFFSET 0x00 +#define MMIO_VSC_INFO_OFFSET 0x00 +#define MMIO_VSC_VF_BAR_LO_OFFSET 0x08 +#define MMIO_VSC_VF_BAR_HI_OFFSET 0x0c +#define MMIO_VSC_VF_CNTL_BAR_LO_OFFSET 0x10 +#define MMIO_VSC_VF_CNTL_BAR_HI_OFFSET 0x14 + +#define IOMMU_VSC_INFO_REV(x) ((x >> 16) & 0xFF) +#define IOMMU_VSC_INFO_ID(x) (x & 0xFFFF) + /* Masks, shifts and macros to parse the device range capability */ #define MMIO_RANGE_LD_MASK 0xff000000 #define MMIO_RANGE_FD_MASK 0x00ff0000 @@ -61,12 +72,15 @@ #define MMIO_PPR_LOG_OFFSET 0x0038 #define MMIO_GA_LOG_BASE_OFFSET 0x00e0 #define MMIO_GA_LOG_TAIL_OFFSET 0x00e8 +#define MMIO_PPRB_LOG_OFFSET 0x00f0 +#define MMIO_EVTB_LOG_OFFSET 0x00f8 #define MMIO_MSI_ADDR_LO_OFFSET 0x015C #define MMIO_MSI_ADDR_HI_OFFSET 0x0160 #define MMIO_MSI_DATA_OFFSET 0x0164 #define MMIO_INTCAPXT_EVT_OFFSET 0x0170 #define MMIO_INTCAPXT_PPR_OFFSET 0x0178 #define MMIO_INTCAPXT_GALOG_OFFSET 0x0180 +#define MMIO_VIOMMU_STATUS_OFFSET 0x0190 #define MMIO_EXT_FEATURES2 0x01A0 #define MMIO_CMD_HEAD_OFFSET 0x2000 #define MMIO_CMD_TAIL_OFFSET 0x2008 @@ -180,8 +194,16 @@ #define CONTROL_GAM_EN 25 #define CONTROL_GALOG_EN 28 #define CONTROL_GAINT_EN 29 +#define CONTROL_DUALPPRLOG_EN 30 +#define CONTROL_DUALEVTLOG_EN 32 + +#define CONTROL_PPR_AUTO_RSP_EN 39 +#define CONTROL_BLKSTOPMRK_EN 41 +#define CONTROL_PPR_AUTO_RSP_AON 48 #define CONTROL_XT_EN 50 #define CONTROL_INTCAPXT_EN 51 +#define CONTROL_VCMD_EN 52 +#define CONTROL_VIOMMU_EN 53 #define CONTROL_SNPAVIC_EN 61 =20 #define CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT) @@ -414,6 +436,13 @@ =20 #define DTE_GPT_LEVEL_SHIFT 54 =20 +/* vIOMMU bit fields */ +#define DTE_VIOMMU_EN_SHIFT 15 +#define DTE_VIOMMU_GUESTID_SHIFT 16 +#define DTE_VIOMMU_GUESTID_MASK 0xFFFF +#define DTE_VIOMMU_GDEVICEID_SHIFT 32 +#define DTE_VIOMMU_GUESTID_MASK 0xFFFF + #define GCR3_VALID 0x01ULL =20 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL) @@ -694,6 +723,17 @@ struct amd_iommu { */ u16 cap_ptr; =20 + /* Vendor-Specific Capability (VSC) pointer. */ + u16 vsc_offset; + + /* virtual addresses of vIOMMU VF/VF_CNTL BAR */ + u8 __iomem *vf_base; + u8 __iomem *vfctrl_base; + + struct protection_domain *viommu_pdom; + void *guest_mmio; + void *cmdbuf_dirty_mask; + /* pci domain of this IOMMU */ struct amd_iommu_pci_seg *pci_seg; =20 diff --git a/drivers/iommu/amd/amd_viommu.h b/drivers/iommu/amd/amd_viommu.h new file mode 100644 index 000000000000..c1dbc2e37eab --- /dev/null +++ b/drivers/iommu/amd/amd_viommu.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023 Advanced Micro Devices, Inc. + * Author: Suravee Suthikulpanit + */ + +#ifndef AMD_VIOMMU_H +#define AMD_VIOMMU_H + +#define VIOMMU_MAX_GUESTID (1 << 16) + +#define VIOMMU_VF_MMIO_ENTRY_SIZE 4096 +#define VIOMMU_VFCTRL_MMIO_ENTRY_SIZE 64 + +#define VIOMMU_VFCTRL_GUEST_DID_MAP_CONTROL0_OFFSET 0x00 +#define VIOMMU_VFCTRL_GUEST_DID_MAP_CONTROL1_OFFSET 0x08 +#define VIOMMU_VFCTRL_GUEST_MISC_CONTROL_OFFSET 0x10 + +#define VIOMMU_VFCTRL_GUEST_CMD_CONTROL_OFFSET 0x20 +#define VIOMMU_VFCTRL_GUEST_EVT_CONTROL_OFFSET 0x28 +#define VIOMMU_VFCTRL_GUEST_PPR_CONTROL_OFFSET 0x30 + +#define VIOMMU_VF_MMIO_BASE(iommu, guestId) \ + (iommu->vf_base + (guestId * VIOMMU_VF_MMIO_ENTRY_SIZE)) +#define VIOMMU_VFCTRL_MMIO_BASE(iommu, guestId) \ + (iommu->vfctrl_base + (guestId * VIOMMU_VFCTRL_MMIO_ENTRY_SIZE)) + +#define VIOMMU_GUEST_MMIO_BASE 0 +#define VIOMMU_GUEST_MMIO_SIZE (64 * VIOMMU_MAX_GUESTID) + +#define VIOMMU_CMDBUF_DIRTY_STATUS_BASE 0x400000ULL +#define VIOMMU_CMDBUF_DIRTY_STATUS_SIZE 0x2000 + +#define VIOMMU_DEVID_MAPPING_BASE 0x1000000000ULL +#define VIOMMU_DEVID_MAPPING_ENTRY_SIZE (1 << 20) + +#define VIOMMU_DOMID_MAPPING_BASE 0x2000000000ULL +#define VIOMMU_DOMID_MAPPING_ENTRY_SIZE (1 << 19) + +#define VIOMMU_GUEST_CMDBUF_BASE 0x2800000000ULL +#define VIOMMU_GUEST_CMDBUF_SIZE (1 << 19) + +#define VIOMMU_GUEST_PPR_LOG_BASE 0x3000000000ULL +#define VIOMMU_GUEST_PPR_LOG_SIZE (1 << 19) + +#define VIOMMU_GUEST_PPR_B_LOG_BASE 0x3800000000ULL +#define VIOMMU_GUEST_PPR_B_LOG_SIZE (1 << 19) + +#define VIOMMU_GUEST_EVT_LOG_BASE 0x4000000000ULL +#define VIOMMU_GUEST_EVT_LOG_SIZE (1 << 19) + +#define VIOMMU_GUEST_EVT_B_LOG_BASE 0x4800000000ULL +#define VIOMMU_GUEST_EVT_B_LOG_SIZE (1 << 19) + +extern int iommu_init_viommu(struct amd_iommu *iommu); + +#endif /* AMD_VIOMMU_H */ diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 4dd9f09e16c4..48aa71fe76dc 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -34,6 +34,7 @@ #include =20 #include "amd_iommu.h" +#include "amd_viommu.h" #include "../irq_remapping.h" =20 /* @@ -2068,6 +2069,8 @@ static int __init iommu_init_pci(struct amd_iommu *io= mmu) if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu)) return -ENOMEM; =20 + iommu_init_viommu(iommu); + if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) { pr_info("Using strict mode due to virtualization\n"); iommu_set_dma_strict(); diff --git a/drivers/iommu/amd/viommu.c b/drivers/iommu/amd/viommu.c new file mode 100644 index 000000000000..18036d03c747 --- /dev/null +++ b/drivers/iommu/amd/viommu.c @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Advanced Micro Devices, Inc. + * Author: Suravee Suthikulpanit + */ + +#define pr_fmt(fmt) "AMD-Vi: " fmt +#define dev_fmt(fmt) pr_fmt(fmt) + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "amd_iommu.h" +#include "amd_iommu_types.h" +#include "amd_viommu.h" + +#define GET_CTRL_BITS(reg, bit, msk) (((reg) >> (bit)) & (ULL(msk))) +#define SET_CTRL_BITS(reg, bit1, bit2, msk) \ + ((((reg) >> (bit1)) & (ULL(msk))) << (bit2)) + +LIST_HEAD(viommu_devid_map); + +struct amd_iommu *get_amd_iommu_from_devid(u16 devid) +{ + struct amd_iommu *iommu; + + for_each_iommu(iommu) + if (iommu->devid =3D=3D devid) + return iommu; + return NULL; +} + +static void viommu_enable(struct amd_iommu *iommu) +{ + if (!amd_iommu_viommu) + return; + iommu_feature_enable(iommu, CONTROL_VCMD_EN); + iommu_feature_enable(iommu, CONTROL_VIOMMU_EN); +} + +static int viommu_init_pci_vsc(struct amd_iommu *iommu) +{ + iommu->vsc_offset =3D pci_find_capability(iommu->dev, PCI_CAP_ID_VNDR); + if (!iommu->vsc_offset) + return -ENODEV; + + DUMP_printk("device:%s, vsc offset:%04x\n", + pci_name(iommu->dev), iommu->vsc_offset); + return 0; +} + +static int __init viommu_vf_vfcntl_init(struct amd_iommu *iommu) +{ + u32 lo, hi; + u64 vf_phys, vf_cntl_phys; + + /* Setting up VF and VF_CNTL MMIOs */ + pci_read_config_dword(iommu->dev, iommu->vsc_offset + MMIO_VSC_VF_BAR_LO_= OFFSET, &lo); + pci_read_config_dword(iommu->dev, iommu->vsc_offset + MMIO_VSC_VF_BAR_HI_= OFFSET, &hi); + vf_phys =3D hi; + vf_phys =3D (vf_phys << 32) | lo; + if (!(vf_phys & 1)) { + pr_err(FW_BUG "vf_phys disabled\n"); + return -EINVAL; + } + + pci_read_config_dword(iommu->dev, iommu->vsc_offset + MMIO_VSC_VF_CNTL_BA= R_LO_OFFSET, &lo); + pci_read_config_dword(iommu->dev, iommu->vsc_offset + MMIO_VSC_VF_CNTL_BA= R_HI_OFFSET, &hi); + vf_cntl_phys =3D hi; + vf_cntl_phys =3D (vf_cntl_phys << 32) | lo; + if (!(vf_cntl_phys & 1)) { + pr_err(FW_BUG "vf_cntl_phys disabled\n"); + return -EINVAL; + } + + if (!vf_phys || !vf_cntl_phys) { + pr_err(FW_BUG "AMD-Vi: Unassigned VF resources.\n"); + return -ENOMEM; + } + + /* Mapping 256MB of VF and 4MB of VF_CNTL BARs */ + vf_phys &=3D ~1ULL; + iommu->vf_base =3D iommu_map_mmio_space(vf_phys, 0x10000000); + if (!iommu->vf_base) { + pr_err("Can't reserve vf_base\n"); + return -ENOMEM; + } + + vf_cntl_phys &=3D ~1ULL; + iommu->vfctrl_base =3D iommu_map_mmio_space(vf_cntl_phys, 0x400000); + + if (!iommu->vfctrl_base) { + pr_err("Can't reserve vfctrl_base\n"); + return -ENOMEM; + } + + pr_debug("%s: IOMMU device:%s, vf_base:%#llx, vfctrl_base:%#llx\n", + __func__, pci_name(iommu->dev), vf_phys, vf_cntl_phys); + return 0; +} + +static void *alloc_private_region(struct amd_iommu *iommu, + u64 base, size_t size) +{ + int ret; + void *region; + + region =3D (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, + get_order(size)); + if (!region) + return NULL; + + ret =3D set_memory_uc((unsigned long)region, size >> PAGE_SHIFT); + if (ret) + goto err_out; + + if (amd_iommu_v1_map_pages(&iommu->viommu_pdom->iop.iop.ops, base, + iommu_virt_to_phys(region), PAGE_SIZE, (size / PAGE_SIZE), + IOMMU_PROT_IR | IOMMU_PROT_IW, GFP_KERNEL, NULL)) + goto err_out; + + pr_debug("%s: base=3D%#llx, size=3D%#lx\n", __func__, base, size); + + return region; + +err_out: + free_pages((unsigned long)region, get_order(size)); + return NULL; +} + +static int viommu_private_space_init(struct amd_iommu *iommu) +{ + u64 pte_root =3D 0; + struct iommu_domain *dom; + struct protection_domain *pdom; + + /* + * Setup page table root pointer, Guest MMIO and + * Cmdbuf Dirty Status regions. + */ + dom =3D amd_iommu_domain_alloc(IOMMU_DOMAIN_UNMANAGED); + if (!dom) + goto err_out; + + pdom =3D to_pdomain(dom); + iommu->viommu_pdom =3D pdom; + set_dte_entry(iommu, iommu->devid, pdom, NULL, pdom->gcr3_tbl, + false, false); + + iommu->guest_mmio =3D alloc_private_region(iommu, + VIOMMU_GUEST_MMIO_BASE, + VIOMMU_GUEST_MMIO_SIZE); + if (!iommu->guest_mmio) + goto err_out; + + iommu->cmdbuf_dirty_mask =3D alloc_private_region(iommu, + VIOMMU_CMDBUF_DIRTY_STATUS_BASE, + VIOMMU_CMDBUF_DIRTY_STATUS_SIZE); + if (!iommu->cmdbuf_dirty_mask) + goto err_out; + + pte_root =3D iommu_virt_to_phys(pdom->iop.root); + pr_debug("%s: devid=3D%#x, pte_root=3D%#llx(%#llx), guest_mmio=3D%#llx(%#= llx), cmdbuf_dirty_mask=3D%#llx(%#llx)\n", + __func__, iommu->devid, (unsigned long long)pdom->iop.root, pte_root, + (unsigned long long)iommu->guest_mmio, iommu_virt_to_phys(iommu->guest_= mmio), + (unsigned long long)iommu->cmdbuf_dirty_mask, + iommu_virt_to_phys(iommu->cmdbuf_dirty_mask)); + + return 0; +err_out: + if (iommu->guest_mmio) + free_pages((unsigned long)iommu->guest_mmio, get_order(VIOMMU_GUEST_MMIO= _SIZE)); + + if (dom) + amd_iommu_domain_free(dom); + return -ENOMEM; +} + +/* + * When IOMMU Virtualization is enabled, host software must: + * - allocate system memory for IOMMU private space + * - program IOMMU as an I/O device in Device Table + * - maintain the I/O page table for IOMMU private addressing to SPA trans= lations. + * - specify the base address of the IOMMU Virtual Function MMIO and + * IOMMU Virtual Function Control MMIO region. + * - enable Guest Virtual APIC enable (MMIO Offset 0x18[GAEn]). + */ +int __init iommu_init_viommu(struct amd_iommu *iommu) +{ + int ret =3D -EINVAL; + + if (!amd_iommu_viommu) + return 0; + + if (!iommu_feature(iommu, FEATURE_VIOMMU)) + goto err_out; + + ret =3D viommu_init_pci_vsc(iommu); + if (ret) + goto err_out; + + ret =3D viommu_vf_vfcntl_init(iommu); + if (ret) + goto err_out; + + ret =3D viommu_private_space_init(iommu); + if (ret) + goto err_out; + + viommu_enable(iommu); + + return ret; + +err_out: + amd_iommu_viommu =3D false; + return ret; +} --=20 2.34.1 From nobody Sun Feb 8 05:19:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0833CEB64DC for ; Wed, 21 Jun 2023 23:57:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230354AbjFUX47 (ORCPT ); Wed, 21 Jun 2023 19:56:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229602AbjFUX4R (ORCPT ); Wed, 21 Jun 2023 19:56:17 -0400 Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam02on2081.outbound.protection.outlook.com [40.107.212.81]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8AE4D1BF9; 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Wed, 21 Jun 2023 23:55:57 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9D4.mail.protection.outlook.com (10.167.241.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6521.21 via Frontend Transport; Wed, 21 Jun 2023 23:55:57 +0000 Received: from ruby-95f9host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Wed, 21 Jun 2023 18:55:56 -0500 From: Suravee Suthikulpanit To: , , CC: , , , , , , , , , , , , , , , "Suravee Suthikulpanit" Subject: [RFC PATCH 15/21] iommu/amd: Introduce vIOMMU vminit and vmdestroy ioctl Date: Wed, 21 Jun 2023 18:55:02 -0500 Message-ID: <20230621235508.113949-16-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> References: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D4:EE_|CY5PR12MB6227:EE_ X-MS-Office365-Filtering-Correlation-Id: cbf2ec24-0f7d-40a0-fabb-08db72b30ed5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 23:55:57.5580 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cbf2ec24-0f7d-40a0-fabb-08db72b30ed5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6227 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" These ioctl interfaces are called when QEMU initialize and destroy VMs. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 2 + drivers/iommu/amd/iommu.c | 4 +- drivers/iommu/amd/viommu.c | 294 ++++++++++++++++++++++++++++++++++ 3 files changed, 298 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index a65d22384ab8..fccae07e8c9f 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -85,6 +85,8 @@ extern int amd_iommu_flush_tlb(struct iommu_domain *dom, = u32 pasid); extern int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid, unsigned long cr3); extern int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid= ); +extern void amd_iommu_iotlb_sync(struct iommu_domain *domain, + struct iommu_iotlb_gather *gather); =20 extern void amd_iommu_build_efr(u64 *efr, u64 *efr2); =20 diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index b5c62bc8249c..f22b2a5a8bfc 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2447,8 +2447,8 @@ static void amd_iommu_flush_iotlb_all(struct iommu_do= main *domain) spin_unlock_irqrestore(&dom->lock, flags); } =20 -static void amd_iommu_iotlb_sync(struct iommu_domain *domain, - struct iommu_iotlb_gather *gather) +void amd_iommu_iotlb_sync(struct iommu_domain *domain, + struct iommu_iotlb_gather *gather) { struct protection_domain *dom =3D to_pdomain(domain); unsigned long flags; diff --git a/drivers/iommu/amd/viommu.c b/drivers/iommu/amd/viommu.c index 18036d03c747..2bafa5102ffa 100644 --- a/drivers/iommu/amd/viommu.c +++ b/drivers/iommu/amd/viommu.c @@ -12,6 +12,7 @@ =20 #include #include +#include #include #include #include @@ -28,8 +29,25 @@ #define SET_CTRL_BITS(reg, bit1, bit2, msk) \ ((((reg) >> (bit1)) & (ULL(msk))) << (bit2)) =20 +#define VIOMMU_MAX_GDEVID 0xFFFF +#define VIOMMU_MAX_GDOMID 0xFFFF + +#define VIOMMU_GID_HASH_BITS 16 +static DEFINE_HASHTABLE(viommu_gid_hash, VIOMMU_GID_HASH_BITS); +static DEFINE_SPINLOCK(viommu_gid_hash_lock); +static u32 viommu_next_gid; +static bool next_viommu_gid_wrapped; + LIST_HEAD(viommu_devid_map); =20 +struct amd_iommu_vminfo { + u16 gid; + bool init; + struct hlist_node hnode; + u64 *devid_table; + u64 *domid_table; +}; + struct amd_iommu *get_amd_iommu_from_devid(u16 devid) { struct amd_iommu *iommu; @@ -138,6 +156,50 @@ static void *alloc_private_region(struct amd_iommu *io= mmu, return NULL; } =20 +static int alloc_private_vm_region(struct amd_iommu *iommu, u64 **entry, + u64 base, size_t size, u16 guestId) +{ + int ret; + u64 addr =3D base + (guestId * size); + + *entry =3D (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, get_order(si= ze)); + + ret =3D set_memory_uc((unsigned long)*entry, size >> PAGE_SHIFT); + if (ret) + return ret; + + pr_debug("%s: entry=3D%#llx(%#llx), addr=3D%#llx\n", __func__, + (unsigned long long)*entry, iommu_virt_to_phys(*entry), addr); + + ret =3D amd_iommu_v1_map_pages(&iommu->viommu_pdom->iop.iop.ops, addr, + iommu_virt_to_phys(*entry), PAGE_SIZE, (size / PAGE_SIZE), + IOMMU_PROT_IR | IOMMU_PROT_IW, GFP_KERNEL, NULL); + + return ret; +} + +static void free_private_vm_region(struct amd_iommu *iommu, u64 **entry, + u64 base, size_t size, u16 guestId) +{ + size_t ret; + struct iommu_iotlb_gather gather; + u64 addr =3D base + (guestId * size); + + pr_debug("entry=3D%#llx(%#llx), addr=3D%#llx\n", + (unsigned long long)*entry, + iommu_virt_to_phys(*entry), addr); + + if (!iommu || iommu->viommu_pdom) + return; + ret =3D amd_iommu_v1_unmap_pages(&iommu->viommu_pdom->iop.iop.ops, + addr, PAGE_SIZE, (size / PAGE_SIZE), &gather); + if (ret) + amd_iommu_iotlb_sync(&iommu->viommu_pdom->domain, &gather); + + free_pages((unsigned long)*entry, get_order(size)); + *entry =3D NULL; +} + static int viommu_private_space_init(struct amd_iommu *iommu) { u64 pte_root =3D 0; @@ -225,3 +287,235 @@ int __init iommu_init_viommu(struct amd_iommu *iommu) amd_iommu_viommu =3D false; return ret; } + +static void viommu_uninit_one(struct amd_iommu *iommu, struct amd_iommu_vm= info *vminfo, u16 guestId) +{ + free_private_vm_region(iommu, &vminfo->devid_table, + VIOMMU_DEVID_MAPPING_BASE, + VIOMMU_DEVID_MAPPING_ENTRY_SIZE, + guestId); + free_private_vm_region(iommu, &vminfo->domid_table, + VIOMMU_DOMID_MAPPING_BASE, + VIOMMU_DOMID_MAPPING_ENTRY_SIZE, + guestId); +} + +/* + * Clear the DevID via VFCTRL registers + * This function will be called during VM destroy via VFIO. + */ +static void clear_device_mapping(struct amd_iommu *iommu, u16 hDevId, u16 = guestId, + u16 queueId, u16 gDevId) +{ + u64 val, tmp1, tmp2; + u8 __iomem *vfctrl; + + /* + * Clear the DevID in VFCTRL registers + */ + tmp1 =3D gDevId; + tmp1 =3D ((tmp1 & 0xFFFFULL) << 46); + tmp2 =3D hDevId; + tmp2 =3D ((tmp2 & 0xFFFFULL) << 14); + val =3D tmp1 | tmp2 | 0x8000000000000001ULL; + vfctrl =3D VIOMMU_VFCTRL_MMIO_BASE(iommu, guestId); + writeq(val, vfctrl + VIOMMU_VFCTRL_GUEST_DID_MAP_CONTROL0_OFFSET); +} + +/* + * Clear the DomID via VFCTRL registers + * This function will be called during VM destroy via VFIO. + */ +static void clear_domain_mapping(struct amd_iommu *iommu, u16 hDomId, u16 = guestId, u16 gDomId) +{ + u64 val, tmp1, tmp2; + u8 __iomem *vfctrl =3D VIOMMU_VFCTRL_MMIO_BASE(iommu, guestId); + + tmp1 =3D gDomId; + tmp1 =3D ((tmp1 & 0xFFFFULL) << 46); + tmp2 =3D hDomId; + tmp2 =3D ((tmp2 & 0xFFFFULL) << 14); + val =3D tmp1 | tmp2 | 0x8000000000000001UL; + writeq(val, vfctrl + VIOMMU_VFCTRL_GUEST_DID_MAP_CONTROL1_OFFSET); +} + +static void viommu_clear_mapping(struct amd_iommu *iommu, u16 guestId) +{ + int i; + + for (i =3D 0; i <=3D VIOMMU_MAX_GDEVID; i++) + clear_device_mapping(iommu, 0, guestId, 0, i); + + for (i =3D 0; i <=3D VIOMMU_MAX_GDOMID; i++) + clear_domain_mapping(iommu, 0, guestId, i); +} + +static void viommu_clear_dirty_status_mask(struct amd_iommu *iommu, unsign= ed int gid) +{ + u32 offset, index, bits; + u64 *group, val; + + if (gid >=3D 256 * 256) + return; + + group =3D (u64 *)(iommu->cmdbuf_dirty_mask + + (((gid & 0xFF) << 4) | (((gid >> 13) & 0x7) << 2))); + offset =3D (gid >> 8) & 0x1F; + index =3D offset >> 6; + bits =3D offset & 0x3F; + + val =3D READ_ONCE(group[index]); + val &=3D ~(1ULL << bits); + WRITE_ONCE(group[index], val); +} + +/* + * Allocate pages for the following regions: + * - Guest MMIO + * - DeviceID/DomainId Mapping Table + * - Cmd buffer + * - Event/PRR (A/B) logs + */ +static int viommu_init_one(struct amd_iommu *iommu, struct amd_iommu_vminf= o *vminfo) +{ + int ret; + + ret =3D alloc_private_vm_region(iommu, &vminfo->devid_table, + VIOMMU_DEVID_MAPPING_BASE, + VIOMMU_DEVID_MAPPING_ENTRY_SIZE, + vminfo->gid); + if (ret) + goto err_out; + + ret =3D alloc_private_vm_region(iommu, &vminfo->domid_table, + VIOMMU_DOMID_MAPPING_BASE, + VIOMMU_DOMID_MAPPING_ENTRY_SIZE, + vminfo->gid); + if (ret) + goto err_out; + + viommu_clear_mapping(iommu, vminfo->gid); + viommu_clear_dirty_status_mask(iommu, vminfo->gid); + + return 0; +err_out: + viommu_uninit_one(iommu, vminfo, vminfo->gid); + return -ENOMEM; +} + +int viommu_gid_alloc(struct amd_iommu *iommu, struct amd_iommu_vminfo *vmi= nfo) +{ + u32 gid; + struct amd_iommu_vminfo *tmp; + unsigned long flags; + + spin_lock_irqsave(&viommu_gid_hash_lock, flags); +again: + gid =3D viommu_next_gid =3D (viommu_next_gid + 1) & 0xFFFF; + + if (gid =3D=3D 0) { /* id is 1-based, zero is not allowed */ + next_viommu_gid_wrapped =3D 1; + goto again; + } + /* Is it still in use? Only possible if wrapped at least once */ + if (next_viommu_gid_wrapped) { + hash_for_each_possible(viommu_gid_hash, tmp, hnode, gid) { + if (tmp->gid =3D=3D gid) + goto again; + } + } + + pr_debug("%s: gid=3D%u\n", __func__, gid); + vminfo->gid =3D gid; + hash_add(viommu_gid_hash, &vminfo->hnode, vminfo->gid); + spin_unlock_irqrestore(&viommu_gid_hash_lock, flags); + return 0; +} + +static void viommu_gid_free(struct amd_iommu *iommu, + struct amd_iommu_vminfo *vminfo) +{ + unsigned long flags; + + pr_debug("%s: gid=3D%u\n", __func__, vminfo->gid); + spin_lock_irqsave(&viommu_gid_hash_lock, flags); + hash_del(&vminfo->hnode); + spin_unlock_irqrestore(&viommu_gid_hash_lock, flags); +} + +struct amd_iommu_vminfo *get_vminfo(struct amd_iommu *iommu, int gid) +{ + unsigned long flags; + struct amd_iommu_vminfo *tmp, *ptr =3D NULL; + + spin_lock_irqsave(&viommu_gid_hash_lock, flags); + hash_for_each_possible(viommu_gid_hash, tmp, hnode, gid) { + if (tmp->gid =3D=3D gid) { + ptr =3D tmp; + break; + } + } + if (!ptr) + pr_debug("%s : gid=3D%u not found\n", __func__, gid); + spin_unlock_irqrestore(&viommu_gid_hash_lock, flags); + return ptr; +} + +int amd_viommu_iommu_init(struct amd_viommu_iommu_info *data) +{ + int ret; + struct amd_iommu_vminfo *vminfo; + unsigned int iommu_id =3D data->iommu_id; + struct amd_iommu *iommu =3D get_amd_iommu_from_devid(iommu_id); + + if (!iommu) + return -ENODEV; + + vminfo =3D kzalloc(sizeof(*vminfo), GFP_KERNEL); + if (!vminfo) + return -ENOMEM; + + ret =3D viommu_gid_alloc(iommu, vminfo); + if (ret) + goto err_out; + + ret =3D viommu_init_one(iommu, vminfo); + if (ret) + goto err_out; + + vminfo->init =3D true; + data->gid =3D vminfo->gid; + pr_debug("%s: iommu_id=3D%#x, gid=3D%#x\n", __func__, + pci_dev_id(iommu->dev), vminfo->gid); + + return ret; + +err_out: + viommu_gid_free(iommu, vminfo); + kfree(vminfo); + return ret; +} +EXPORT_SYMBOL(amd_viommu_iommu_init); + +int amd_viommu_iommu_destroy(struct amd_viommu_iommu_info *data) +{ + unsigned int gid =3D data->gid; + struct amd_iommu_vminfo *vminfo; + unsigned int iommu_id =3D data->iommu_id; + struct amd_iommu *iommu =3D get_amd_iommu_from_devid(iommu_id); + + if (!iommu) + return -ENODEV; + + vminfo =3D get_vminfo(iommu, gid); + if (!vminfo) + return -EINVAL; + + viommu_uninit_one(iommu, vminfo, gid); + + if (vminfo->init) + vminfo->init =3D false; + return 0; + +} +EXPORT_SYMBOL(amd_viommu_iommu_destroy); --=20 2.34.1 From nobody Sun Feb 8 05:19:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83C88EB64D7 for ; Wed, 21 Jun 2023 23:56:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230341AbjFUX4u (ORCPT ); Wed, 21 Jun 2023 19:56:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37962 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230253AbjFUX4R (ORCPT ); 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Wed, 21 Jun 2023 18:55:57 -0500 From: Suravee Suthikulpanit To: , , CC: , , , , , , , , , , , , , , , "Suravee Suthikulpanit" Subject: [RFC PATCH 16/21] iommu/amd: Introduce vIOMMU ioctl for updating device mapping table Date: Wed, 21 Jun 2023 18:55:03 -0500 Message-ID: <20230621235508.113949-17-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> References: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D1:EE_|BL1PR12MB5127:EE_ X-MS-Office365-Filtering-Correlation-Id: def41212-f7b6-4b3a-ecbe-08db72b30f7f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: z26dcwE+uIJSfxzi+AN7yEXhrF3IhSX7ILeOHg3L+cQiyWc8s+l/43BJMYfMe3ROH8J0wtDZDkSVcaMVvcSFHJvpoDeDajkhPGHUTdnfZYoF+YQxgxciMqfR4hrjAIpUb6D0d2/fsGkc0X1cZsgcVac7z4sJ7U3LL6imxGiSRQIjibvAOs2/xJduu7R8jRYD6zgfla7ZJvGMXEy+MKmb3b1wiRadk4giSrq+6mNLGbu2Euld1MGRebYO813qFqGqaIlq0z2xYYumGsXwEVALnsiR45axAIAMkBwDz5fq3U89sbaV5ncCRdUy/Npn+0buKBJYdjOa196QHJZtffv6Vu2lETO7/+AqzDrIVMH7/BcLsa8DoBomOIOprcMgqVjzgMiHVmanq2HDtKNbrj8aga5Knb5QeRjvd8RHTg4ITDI4zzeX+V1XjX4zOWvxIiKM0ODjdwAG5wkrLEvkw481InonvRHFwmovh7QI+usUBmVtHqm/LwZLkl53Szy+SIr440rde62r41el/gxbB1EYs4Qd7NGw1Cqg+dy4aY05u8AR6v/lxJNxYVnXvtnoJd5OFREvWnrC9ndSra0LXe7FLsgeDliaYJk401Sa3a2uXUikjyb90nRUCKtg9G8T/kz7P27Z+Q8kIgHOXDPkGzg2wAL6NQn5G85636522Y3reU1dwzleCpw1jGzjBHBk4gZpbD09uAft2it/GpFfM9Vi3XAXis9+qhwnOPOQVk5ckwkC1Q9CPj3PgEKksLj9c9NWnDttrqsyFaDXOjLwgb3e2g== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(396003)(136003)(39860400002)(346002)(376002)(451199021)(40470700004)(46966006)(36840700001)(82310400005)(36860700001)(36756003)(70206006)(40460700003)(356005)(5660300002)(44832011)(7416002)(8676002)(41300700001)(86362001)(8936002)(4326008)(316002)(40480700001)(70586007)(82740400003)(81166007)(47076005)(1076003)(478600001)(26005)(16526019)(426003)(2906002)(2616005)(186003)(83380400001)(6666004)(336012)(7696005)(110136005)(54906003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 23:55:58.6717 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: def41212-f7b6-4b3a-ecbe-08db72b30f7f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D1.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5127 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" These ioctl interfaces are used for updating device host-to-guest device ID mappings. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/viommu.c | 130 +++++++++++++++++++++++++++++++++++++ 1 file changed, 130 insertions(+) diff --git a/drivers/iommu/amd/viommu.c b/drivers/iommu/amd/viommu.c index 2bafa5102ffa..f6f0056c7fe6 100644 --- a/drivers/iommu/amd/viommu.c +++ b/drivers/iommu/amd/viommu.c @@ -519,3 +519,133 @@ int amd_viommu_iommu_destroy(struct amd_viommu_iommu_= info *data) =20 } EXPORT_SYMBOL(amd_viommu_iommu_destroy); + +static void set_dte_viommu(struct amd_iommu *iommu, u16 hDevId, u16 gid, u= 16 gDevId) +{ + u64 tmp, dte; + struct dev_table_entry *dev_table =3D get_dev_table(iommu); + + // vImuEn + dte =3D dev_table[hDevId].data[3]; + dte |=3D (1ULL << DTE_VIOMMU_EN_SHIFT); + + // GDeviceID + tmp =3D gDevId & DTE_VIOMMU_GUESTID_MASK; + dte |=3D (tmp << DTE_VIOMMU_GUESTID_SHIFT); + + // GuestID + tmp =3D gid & DTE_VIOMMU_GUESTID_MASK; + dte |=3D (tmp << DTE_VIOMMU_GDEVICEID_SHIFT); + + dev_table[hDevId].data[3] =3D dte; + + dte =3D dev_table[hDevId].data[0]; + dte |=3D DTE_FLAG_GV; + dev_table[hDevId].data[0] =3D dte; + + iommu_flush_dte(iommu, hDevId); +} + +void dump_device_mapping(struct amd_iommu *iommu, u16 guestId, u16 gdev_id) +{ + void *addr; + u64 offset, val; + struct amd_iommu_vminfo *vminfo; + + vminfo =3D get_vminfo(iommu, guestId); + if (!vminfo) + return; + + addr =3D vminfo->devid_table; + offset =3D gdev_id << 4; + val =3D *((u64 *)(addr + offset)); + + pr_debug("%s: guestId=3D%#x, gdev_id=3D%#x, base=3D%#llx, offset=3D%#llx(= val=3D%#llx)\n", __func__, + guestId, gdev_id, (unsigned long long)iommu_virt_to_phys(vminfo->devid_= table), + (unsigned long long)offset, (unsigned long long)val); +} + +/* + * Program the DevID via VFCTRL registers + * This function will be called during VM init via VFIO. + */ +static void set_device_mapping(struct amd_iommu *iommu, u16 hDevId, + u16 guestId, u16 queueId, u16 gDevId) +{ + u64 val, tmp1, tmp2; + u8 __iomem *vfctrl; + + pr_debug("%s: iommu_id=3D%#x, gid=3D%#x, hDevId=3D%#x, gDevId=3D%#x\n", + __func__, pci_dev_id(iommu->dev), guestId, hDevId, gDevId); + + set_dte_viommu(iommu, hDevId, guestId, gDevId); + + tmp1 =3D gDevId; + tmp1 =3D ((tmp1 & 0xFFFFULL) << 46); + tmp2 =3D hDevId; + tmp2 =3D ((tmp2 & 0xFFFFULL) << 14); + val =3D tmp1 | tmp2 | 0x8000000000000001ULL; + vfctrl =3D VIOMMU_VFCTRL_MMIO_BASE(iommu, guestId); + writeq(val, vfctrl + VIOMMU_VFCTRL_GUEST_DID_MAP_CONTROL0_OFFSET); + wbinvd_on_all_cpus(); + + tmp1 =3D hDevId; + val =3D ((tmp1 & 0xFFFFULL) << 16); + writeq(val, vfctrl + VIOMMU_VFCTRL_GUEST_MISC_CONTROL_OFFSET); +} + +static void clear_dte_viommu(struct amd_iommu *iommu, u16 hDevId) +{ + struct dev_table_entry *dev_table =3D get_dev_table(iommu); + u64 dte =3D dev_table[hDevId].data[3]; + + dte &=3D ~(1ULL << DTE_VIOMMU_EN_SHIFT); + dte &=3D ~(0xFFFFULL << DTE_VIOMMU_GUESTID_SHIFT); + dte &=3D ~(0xFFFFULL << DTE_VIOMMU_GDEVICEID_SHIFT); + + dev_table[hDevId].data[3] =3D dte; + + dte =3D dev_table[hDevId].data[0]; + dte &=3D ~DTE_FLAG_GV; + dev_table[hDevId].data[0] =3D dte; + + iommu_flush_dte(iommu, hDevId); +} + +int amd_viommu_device_update(struct amd_viommu_dev_info *data, bool is_set) +{ + struct pci_dev *pdev; + struct iommu_domain *dom; + int gid =3D data->gid; + struct amd_iommu *iommu =3D get_amd_iommu_from_devid(data->iommu_id); + + if (!iommu) + return -ENODEV; + + clear_dte_viommu(iommu, data->hdev_id); + + if (is_set) { + set_device_mapping(iommu, data->hdev_id, gid, + data->queue_id, data->gdev_id); + + pdev =3D pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(data->hdev_id), + data->hdev_id & 0xff); + dom =3D iommu_get_domain_for_dev(&pdev->dev); + if (!dom) { + pr_err("%s: Domain not found (devid=3D%#x)\n", + __func__, pci_dev_id(pdev)); + return -EINVAL; + } + + /* TODO: Only support pasid 0 for now */ + amd_iommu_flush_tlb(dom, 0); + dump_device_mapping(iommu, gid, data->gdev_id); + + } else { + clear_device_mapping(iommu, data->hdev_id, gid, + data->queue_id, data->gdev_id); + } + + return 0; +} +EXPORT_SYMBOL(amd_viommu_device_update); --=20 2.34.1 From nobody Sun Feb 8 05:19:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DE78EB64D8 for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9CD.mail.protection.outlook.com (10.167.241.140) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6521.24 via Frontend Transport; Wed, 21 Jun 2023 23:56:02 +0000 Received: from ruby-95f9host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Wed, 21 Jun 2023 18:55:58 -0500 From: Suravee Suthikulpanit To: , , CC: , , , , , , , , , , , , , , , "Suravee Suthikulpanit" Subject: [RFC PATCH 17/21] iommu/amd: Introduce vIOMMU ioctl for updating domain mapping Date: Wed, 21 Jun 2023 18:55:04 -0500 Message-ID: <20230621235508.113949-18-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> References: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CD:EE_|SJ2PR12MB7920:EE_ X-MS-Office365-Filtering-Correlation-Id: 587bf228-48bd-4c05-18f3-08db72b311f6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 23:56:02.8173 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 587bf228-48bd-4c05-18f3-08db72b311f6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7920 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" These ioctl interfaces are used for updating device host-to-guest domain ID mappings. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/viommu.c | 95 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/drivers/iommu/amd/viommu.c b/drivers/iommu/amd/viommu.c index f6f0056c7fe6..1bcb895cffbf 100644 --- a/drivers/iommu/amd/viommu.c +++ b/drivers/iommu/amd/viommu.c @@ -520,6 +520,101 @@ int amd_viommu_iommu_destroy(struct amd_viommu_iommu_= info *data) } EXPORT_SYMBOL(amd_viommu_iommu_destroy); =20 +/* + * Program the DomID via VFCTRL registers + * This function will be called during VM init via VFIO. + */ +static void set_domain_mapping(struct amd_iommu *iommu, u16 guestId, u16 h= DomId, u16 gDomId) +{ + u64 val, tmp1, tmp2; + u8 __iomem *vfctrl =3D VIOMMU_VFCTRL_MMIO_BASE(iommu, guestId); + + pr_debug("%s: iommu_id=3D%#x, gid=3D%#x, dom_id=3D%#x, gdom_id=3D%#x, val= =3D%#llx\n", + __func__, pci_dev_id(iommu->dev), guestId, hDomId, gDomId, val); + + tmp1 =3D gDomId; + tmp1 =3D ((tmp1 & 0xFFFFULL) << 46); + tmp2 =3D hDomId; + tmp2 =3D ((tmp2 & 0xFFFFULL) << 14); + val =3D tmp1 | tmp2 | 0x8000000000000001UL; + writeq(val, vfctrl + VIOMMU_VFCTRL_GUEST_DID_MAP_CONTROL1_OFFSET); + wbinvd_on_all_cpus(); +} + +u64 get_domain_mapping(struct amd_iommu *iommu, u16 gid, u16 gdom_id) +{ + void *addr; + u64 offset, val; + struct amd_iommu_vminfo *vminfo; + + vminfo =3D get_vminfo(iommu, gid); + if (!vminfo) + return -EINVAL; + + addr =3D vminfo->domid_table; + offset =3D gdom_id << 3; + val =3D *((u64 *)(addr + offset)); + + return val; +} + +void dump_domain_mapping(struct amd_iommu *iommu, u16 gid, u16 gdom_id) +{ + void *addr; + u64 offset, val; + struct amd_iommu_vminfo *vminfo; + + vminfo =3D get_vminfo(iommu, gid); + if (!vminfo) + return; + + addr =3D vminfo->domid_table; + offset =3D gdom_id << 3; + val =3D *((u64 *)(addr + offset)); + + pr_debug("%s: offset=3D%#llx(val=3D%#llx)\n", __func__, + (unsigned long long)offset, + (unsigned long long)val); +} + +static u16 viommu_get_hdev_id(struct amd_iommu *iommu, u16 guestId, u16 gd= ev_id) +{ + struct amd_iommu_vminfo *vminfo; + void *addr; + u64 offset; + + vminfo =3D get_vminfo(iommu, guestId); + if (!vminfo) + return -1; + + addr =3D vminfo->devid_table; + offset =3D gdev_id << 4; + return (*((u64 *)(addr + offset)) >> 24) & 0xFFFF; +} + +int amd_viommu_domain_update(struct amd_viommu_dom_info *data, bool is_set) +{ + u16 hdom_id, hdev_id; + int gid =3D data->gid; + struct amd_iommu *iommu =3D get_amd_iommu_from_devid(data->iommu_id); + struct dev_table_entry *dev_table =3D get_dev_table(iommu); + + if (!iommu) + return -ENODEV; + + hdev_id =3D viommu_get_hdev_id(iommu, gid, data->gdev_id); + hdom_id =3D dev_table[hdev_id].data[1] & 0xFFFFULL; + + if (is_set) { + set_domain_mapping(iommu, gid, hdom_id, data->gdom_id); + dump_domain_mapping(iommu, 0, data->gdom_id); + } else + clear_domain_mapping(iommu, gid, hdom_id, data->gdom_id); + + return 0; +} +EXPORT_SYMBOL(amd_viommu_domain_update); + static void set_dte_viommu(struct amd_iommu *iommu, u16 hDevId, u16 gid, u= 16 gDevId) { u64 tmp, dte; --=20 2.34.1 From nobody Sun Feb 8 05:19:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F909EB64DC for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9D1.mail.protection.outlook.com (10.167.241.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6521.23 via Frontend Transport; Wed, 21 Jun 2023 23:56:05 +0000 Received: from ruby-95f9host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Wed, 21 Jun 2023 18:55:59 -0500 From: Suravee Suthikulpanit To: , , CC: , , , , , , , , , , , , , , , "Suravee Suthikulpanit" Subject: [RFC PATCH 18/21] iommu/amd: Introduce vIOMMU ioctl for handling guest MMIO accesses Date: Wed, 21 Jun 2023 18:55:05 -0500 Message-ID: <20230621235508.113949-19-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> References: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D1:EE_|SJ0PR12MB5502:EE_ X-MS-Office365-Filtering-Correlation-Id: f86a63b5-5a58-47bc-4a1d-08db72b3134a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 23:56:05.0311 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f86a63b5-5a58-47bc-4a1d-08db72b3134a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D1.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5502 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This ioctl interface is used for handling guest MMIO read / write to IOMMU MMIO registers. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/viommu.c | 250 +++++++++++++++++++++++++++++++++++++ 1 file changed, 250 insertions(+) diff --git a/drivers/iommu/amd/viommu.c b/drivers/iommu/amd/viommu.c index 1bcb895cffbf..9ddbdbec4a75 100644 --- a/drivers/iommu/amd/viommu.c +++ b/drivers/iommu/amd/viommu.c @@ -744,3 +744,253 @@ int amd_viommu_device_update(struct amd_viommu_dev_in= fo *data, bool is_set) return 0; } EXPORT_SYMBOL(amd_viommu_device_update); + +int amd_viommu_guest_mmio_read(struct amd_viommu_mmio_data *data) +{ + u8 __iomem *vfctrl, *vf; + u64 val, tmp =3D 0; + int gid =3D data->gid; + struct amd_iommu *iommu =3D get_amd_iommu_from_devid(data->iommu_id); + + if (!iommu) + return -ENODEV; + + vf =3D VIOMMU_VF_MMIO_BASE(iommu, gid); + vfctrl =3D VIOMMU_VFCTRL_MMIO_BASE(iommu, gid); + + switch (data->offset) { + case MMIO_CONTROL_OFFSET: + { + /* VFCTRL offset 20h */ + val =3D readq(vfctrl + 0x20); + tmp |=3D SET_CTRL_BITS(val, 8, CONTROL_CMDBUF_EN, 1); // [12] + tmp |=3D SET_CTRL_BITS(val, 9, CONTROL_COMWAIT_EN, 1); // [4] + + /* VFCTRL offset 28h */ + val =3D readq(vfctrl + 0x28); + tmp |=3D SET_CTRL_BITS(val, 8, CONTROL_EVT_LOG_EN, 1); // [2] + tmp |=3D SET_CTRL_BITS(val, 9, CONTROL_EVT_INT_EN, 1); // [3] + tmp |=3D SET_CTRL_BITS(val, 10, CONTROL_DUALEVTLOG_EN, 3); // [33:32] + + /* VFCTRL offset 30h */ + val =3D readq(vfctrl + 0x30); + tmp |=3D SET_CTRL_BITS(val, 8, CONTROL_PPRLOG_EN, 1); // [13] + tmp |=3D SET_CTRL_BITS(val, 9, CONTROL_PPRINT_EN, 1); // [14] + tmp |=3D SET_CTRL_BITS(val, 10, CONTROL_PPR_EN, 1); // [15] + tmp |=3D SET_CTRL_BITS(val, 11, CONTROL_DUALPPRLOG_EN, 3); // [31:30] + tmp |=3D SET_CTRL_BITS(val, 13, CONTROL_PPR_AUTO_RSP_EN, 1); // [39] + tmp |=3D SET_CTRL_BITS(val, 14, CONTROL_BLKSTOPMRK_EN, 1); // [41] + tmp |=3D SET_CTRL_BITS(val, 15, CONTROL_PPR_AUTO_RSP_AON, 1); // [42] + + data->value =3D tmp; + break; + } + case MMIO_CMD_BUF_OFFSET: + { + val =3D readq(vfctrl + 0x20); + /* CmdLen [59:56] */ + tmp |=3D SET_CTRL_BITS(val, 0, 56, 0xF); + data->value =3D tmp; + break; + } + case MMIO_EVT_BUF_OFFSET: + { + val =3D readq(vfctrl + 0x28); + /* EventLen [59:56] */ + tmp |=3D SET_CTRL_BITS(val, 0, 56, 0xF); + data->value =3D tmp; + break; + } + case MMIO_EVTB_LOG_OFFSET: + { + val =3D readq(vfctrl + 0x28); + /* EventLenB [59:56] */ + tmp |=3D SET_CTRL_BITS(val, 4, 56, 0xF); + data->value =3D tmp; + break; + } + case MMIO_PPR_LOG_OFFSET: + { + val =3D readq(vfctrl + 0x30); + /* PPRLogLen [59:56] */ + tmp |=3D SET_CTRL_BITS(val, 0, 56, 0xF); + data->value =3D tmp; + break; + } + case MMIO_PPRB_LOG_OFFSET: + { + val =3D readq(vfctrl + 0x30); + /* PPRLogLenB [59:56] */ + tmp |=3D SET_CTRL_BITS(val, 4, 56, 0xF); + data->value |=3D tmp; + break; + } + case MMIO_CMD_HEAD_OFFSET: + { + val =3D readq(vf + 0x0); + data->value =3D (val & 0x7FFF0); + break; + } + case MMIO_CMD_TAIL_OFFSET: + { + val =3D readq(vf + 0x8); + data->value =3D (val & 0x7FFF0); + break; + } + case MMIO_EXT_FEATURES: + { + amd_iommu_build_efr(&data->value, NULL); + break; + } + default: + break; + } + + pr_debug("%s: iommu_id=3D%#x, gid=3D%u, offset=3D%#x, value=3D%#llx, mmio= _size=3D%u, is_write=3D%u\n", + __func__, data->iommu_id, gid, data->offset, + data->value, data->mmio_size, data->is_write); + return 0; +} +EXPORT_SYMBOL(amd_viommu_guest_mmio_read); + +/* Note: + * This function maps the guest MMIO write to AMD IOMMU MMIO registers + * into vIOMMU VFCTRL register bits. + */ +int amd_viommu_guest_mmio_write(struct amd_viommu_mmio_data *data) +{ + u8 __iomem *vfctrl, *vf; + int gid =3D data->gid; + u64 val, tmp, ctrl =3D data->value; + struct amd_iommu *iommu =3D get_amd_iommu_from_devid(data->iommu_id); + + if (!iommu) + return -ENODEV; + + pr_debug("%s: iommu_id=3D%#x, gid=3D%u, offset=3D%#x, value=3D%#llx, mmio= _size=3D%u, is_write=3D%u\n", + __func__, data->iommu_id, gid, data->offset, + ctrl, data->mmio_size, data->is_write); + + vf =3D VIOMMU_VF_MMIO_BASE(iommu, gid); + vfctrl =3D VIOMMU_VFCTRL_MMIO_BASE(iommu, gid); + + switch (data->offset) { + case MMIO_CONTROL_OFFSET: + { + /* VFCTRL offset 20h */ + val =3D readq(vfctrl + 0x20); + val &=3D ~(0x3ULL << 8); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_CMDBUF_EN, 1); // [12] + val |=3D (tmp << 8); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_COMWAIT_EN, 1); // [4] + val |=3D (tmp << 9); + writeq(val, vfctrl + 0x20); + + /* VFCTRL offset 28h */ + val =3D readq(vfctrl + 0x28); + val &=3D ~(0xFULL << 8); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_EVT_LOG_EN, 1); // [2] + val |=3D (tmp << 8); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_EVT_INT_EN, 1); // [3] + val |=3D (tmp << 9); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_DUALEVTLOG_EN, 3); // [33:32] + val |=3D (tmp << 10); + writeq(val, vfctrl + 0x28); + + /* VFCTRL offset 30h */ + val =3D readq(vfctrl + 0x30); + val &=3D ~(0xFFULL << 8); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_PPRLOG_EN, 1); // [13] + val |=3D (tmp << 8); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_PPRINT_EN, 1); // [14] + val |=3D (tmp << 9); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_PPR_EN, 1); // [15] + val |=3D (tmp << 10); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_DUALPPRLOG_EN, 3); // [31:30] + val |=3D (tmp << 11); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_PPR_AUTO_RSP_EN, 1); // [39] + val |=3D (tmp << 13); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_BLKSTOPMRK_EN, 1); // [41] + val |=3D (tmp << 14); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_PPR_AUTO_RSP_AON, 1); // [42] + val |=3D (tmp << 15); + writeq(val, vfctrl + 0x30); + break; + } + case MMIO_CMD_BUF_OFFSET: + { + val =3D readq(vfctrl + 0x20); + val &=3D ~(0xFULL); + /* CmdLen [59:56] */ + tmp =3D GET_CTRL_BITS(ctrl, 56, 0xF); + val |=3D tmp; + writeq(val, vfctrl + 0x20); + break; + } + case MMIO_EVT_BUF_OFFSET: + { + val =3D readq(vfctrl + 0x28); + val &=3D ~(0xFULL); + /* EventLen [59:56] */ + tmp =3D GET_CTRL_BITS(ctrl, 56, 0xF); + val |=3D tmp; + writeq(val, vfctrl + 0x28); + break; + } + case MMIO_EVTB_LOG_OFFSET: + { + val =3D readq(vfctrl + 0x28); + val &=3D ~(0xF0ULL); + /* EventLenB [59:56] */ + tmp =3D GET_CTRL_BITS(ctrl, 56, 0xF); + val |=3D (tmp << 4); + writeq(val, vfctrl + 0x28); + break; + } + case MMIO_PPR_LOG_OFFSET: + { + val =3D readq(vfctrl + 0x30); + val &=3D ~(0xFULL); + /* PPRLogLen [59:56] */ + tmp =3D GET_CTRL_BITS(ctrl, 56, 0xF); + val |=3D tmp; + writeq(val, vfctrl + 0x30); + break; + } + case MMIO_PPRB_LOG_OFFSET: + { + val =3D readq(vfctrl + 0x30); + val &=3D ~(0xF0ULL); + /* PPRLogLenB [59:56] */ + tmp =3D GET_CTRL_BITS(ctrl, 56, 0xF); + val |=3D (tmp << 4); + writeq(val, vfctrl + 0x30); + break; + } + case MMIO_CMD_HEAD_OFFSET: + { + val =3D readq(vf + 0x0); + val &=3D ~(0x7FFFULL << 4); + tmp =3D GET_CTRL_BITS(ctrl, 4, 0x7FFF); + val |=3D (tmp << 4); + writeq(val, vf + 0x0); + break; + } + case MMIO_CMD_TAIL_OFFSET: + { + val =3D readq(vf + 0x8); + val &=3D ~(0x7FFFULL << 4); + tmp =3D GET_CTRL_BITS(ctrl, 4, 0x7FFF); + val |=3D (tmp << 4); + writeq(val, vf + 0x8); + break; + } + default: + break; + } + + pr_debug("%s: offset=3D%#x, val=3D%#llx, ctrl=3D%#llx\n", + __func__, data->offset, val, ctrl); + return 0; +} +EXPORT_SYMBOL(amd_viommu_guest_mmio_write); --=20 2.34.1 From nobody Sun Feb 8 05:19:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17A2DEB64D8 for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 23:56:05.6405 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4a5cdd97-f8c3-4eb0-45c3-08db72b313a7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D1.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7148 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This ioctl interface is used for handling vIOMMU command buffer mapping. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu_types.h | 1 + drivers/iommu/amd/viommu.c | 78 +++++++++++++++++++++++++++++ 2 files changed, 79 insertions(+) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 5cb5a709b31b..dd3c79e454d8 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -261,6 +261,7 @@ #define CMD_BUFFER_SIZE 8192 #define CMD_BUFFER_UNINITIALIZED 1 #define CMD_BUFFER_ENTRIES 512 +#define CMD_BUFFER_MAXSIZE 0x80000 #define MMIO_CMD_SIZE_SHIFT 56 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT) =20 diff --git a/drivers/iommu/amd/viommu.c b/drivers/iommu/amd/viommu.c index 9ddbdbec4a75..1bd4282384c4 100644 --- a/drivers/iommu/amd/viommu.c +++ b/drivers/iommu/amd/viommu.c @@ -994,3 +994,81 @@ int amd_viommu_guest_mmio_write(struct amd_viommu_mmio= _data *data) return 0; } EXPORT_SYMBOL(amd_viommu_guest_mmio_write); + +static void viommu_cmdbuf_free(struct protection_domain *dom, struct io_pg= table_ops *ops, + unsigned long iova, struct page **pages, unsigned long npages) +{ + int i; + unsigned long flags; + unsigned long tmp =3D iova; + + spin_lock_irqsave(&dom->lock, flags); + for (i =3D 0; i < npages; i++, tmp +=3D PAGE_SIZE) { + amd_iommu_v1_unmap_pages(ops, tmp, PAGE_SIZE, 1, NULL); + /* + * Flush domain TLB(s) and wait for completion. Any Device-Table + * Updates and flushing already happened in + * increase_address_space(). + */ + amd_iommu_domain_flush_tlb_pde(dom); + amd_iommu_domain_flush_complete(dom); + + unpin_user_pages(&pages[i], 1); + } + spin_unlock_irqrestore(&dom->lock, flags); +} + +int amd_viommu_cmdbuf_update(struct amd_viommu_cmdbuf_data *data) +{ + int i, numpg =3D data->cmdbuf_size >> PAGE_SHIFT; + struct amd_iommu *iommu =3D get_amd_iommu_from_devid(data->iommu_id); + struct amd_iommu_vminfo *vminfo; + unsigned int gid =3D data->gid; + struct page **pages; + unsigned long npages =3D 0; + unsigned long iova; + unsigned long hva =3D data->hva; + + pages =3D kcalloc(numpg, sizeof(struct page *), GFP_KERNEL); + if (!pages) + return -ENOMEM; + + vminfo =3D get_vminfo(iommu, gid); + if (!vminfo) + return -EINVAL; + + /* + * Setup vIOMMU guest command buffer in IOMMU Private Address (IPA) space + * for the specified GID. + */ + for (i =3D 0 ; i < numpg; i++, hva +=3D (0x1000 * i)) { + int ret; + u64 phys; + + if (get_user_pages_fast(hva, 1, FOLL_WRITE, &pages[i]) !=3D 1) { + pr_err("%s: Failure locking page:%#lx.\n", __func__, hva); + goto err_out; + } + + phys =3D __sme_set(page_to_pfn(pages[i]) << PAGE_SHIFT); + iova =3D VIOMMU_GUEST_CMDBUF_BASE + (i * PAGE_SIZE) + (gid * CMD_BUFFER_= MAXSIZE); + + pr_debug("%s: iova=3D%#lx, phys=3D%#llx\n", __func__, iova, phys); + ret =3D amd_iommu_v1_map_pages(&iommu->viommu_pdom->iop.iop.ops, + iova, phys, PAGE_SIZE, 1, + IOMMU_PROT_IR | IOMMU_PROT_IW, + GFP_KERNEL, NULL); + if (ret) { + pr_err("%s: Failure to map page iova:%#lx, phys=3D%#llx\n", + __func__, iova, phys); + goto err_out; + } + npages++; + } + return 0; +err_out: + viommu_cmdbuf_free(iommu->viommu_pdom, &iommu->viommu_pdom->iop.iop.ops, + iova, pages, npages); + return -EINVAL; +} +EXPORT_SYMBOL(amd_viommu_cmdbuf_update); --=20 2.34.1 From nobody Sun Feb 8 05:19:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8DBC2EB64D7 for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9CD.mail.protection.outlook.com (10.167.241.140) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6521.24 via Frontend Transport; Wed, 21 Jun 2023 23:56:06 +0000 Received: from ruby-95f9host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Wed, 21 Jun 2023 18:56:01 -0500 From: Suravee Suthikulpanit To: , , CC: , , , , , , , , , , , , , , , "Suravee Suthikulpanit" Subject: [RFC PATCH 20/21] iommu/amd: Introduce vIOMMU ioctl for setting up guest CR3 Date: Wed, 21 Jun 2023 18:55:07 -0500 Message-ID: <20230621235508.113949-21-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> References: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CD:EE_|DM4PR12MB5842:EE_ X-MS-Office365-Filtering-Correlation-Id: d10155f6-2187-4aa4-72af-08db72b31458 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 23:56:06.8016 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d10155f6-2187-4aa4-72af-08db72b31458 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5842 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This ioctl interface sets up guest CR3 (gCR3) table, which is defined by guest IOMMU driver. It also enables nested I/O page translation in the host. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 12 ++++ drivers/iommu/amd/iommu.c | 107 ++++++++++++++++++++++++++++++++++ drivers/iommu/amd/viommu.c | 36 ++++++++++++ include/linux/iommu.h | 1 + include/uapi/linux/iommufd.h | 20 +++++++ 5 files changed, 176 insertions(+) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index fccae07e8c9f..463cd59127b7 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -84,6 +84,18 @@ extern void amd_iommu_domain_flush_tlb_pde(struct protec= tion_domain *domain); extern int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid); extern int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid, unsigned long cr3); +extern int amd_viommu_user_gcr3_update(const void *user_data, + struct iommu_domain *udom); +extern int amd_iommu_setup_gcr3_table(struct amd_iommu *iommu, + struct pci_dev *pdev, + struct iommu_domain *dom, + struct iommu_domain *udom, + int pasids, bool giov); +extern int amd_iommu_user_set_gcr3(struct amd_iommu *iommu, + struct iommu_domain *dom, + struct iommu_domain *udom, + struct pci_dev *pdev, u32 pasid, + unsigned long cr3); extern int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid= ); extern void amd_iommu_iotlb_sync(struct iommu_domain *domain, struct iommu_iotlb_gather *gather); diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index f22b2a5a8bfc..bff53977f8f7 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -80,6 +80,8 @@ struct kmem_cache *amd_iommu_irq_cache; =20 static void detach_device(struct device *dev); static int domain_enable_v2(struct protection_domain *domain, int pasids, = bool giov); +static int __set_gcr3(struct protection_domain *domain, u32 pasid, + unsigned long cr3); =20 /*************************************************************************= *** * @@ -2525,10 +2527,43 @@ static void *amd_iommu_hw_info(struct device *dev, = u32 *length) return hwinfo; } =20 +static struct iommu_domain * +amd_iommu_domain_alloc_user(struct device *dev, + enum iommu_hwpt_type hwpt_type, + struct iommu_domain *parent, + const union iommu_domain_user_data *user_data) +{ + int ret; + struct iommu_domain *dom =3D iommu_domain_alloc(dev->bus); + + if (!dom || !parent) + return dom; + + /* + * The parent is not null only when external driver calls IOMMUFD kAPI + * to create IOMMUFD_OBJ_HW_PAGETABLE to attach a bound device to IOAS. + * This is for nested (v2) page table. + * + * TODO: Currently, only support nested table w/ 1 pasid for GIOV use cas= e. + * Add support for multiple pasids. + */ + dom->type =3D IOMMU_DOMAIN_NESTED; + + ret =3D amd_viommu_user_gcr3_update(user_data, dom); + if (ret) + goto err_out; + + return dom; +err_out: + iommu_domain_free(dom); + return NULL; +} + const struct iommu_ops amd_iommu_ops =3D { .capable =3D amd_iommu_capable, .hw_info =3D amd_iommu_hw_info, .domain_alloc =3D amd_iommu_domain_alloc, + .domain_alloc_user =3D amd_iommu_domain_alloc_user, .probe_device =3D amd_iommu_probe_device, .release_device =3D amd_iommu_release_device, .probe_finalize =3D amd_iommu_probe_finalize, @@ -2537,6 +2572,7 @@ const struct iommu_ops amd_iommu_ops =3D { .is_attach_deferred =3D amd_iommu_is_attach_deferred, .pgsize_bitmap =3D AMD_IOMMU_PGSIZES, .def_domain_type =3D amd_iommu_def_domain_type, + .hw_info_type =3D IOMMU_HW_INFO_TYPE_AMD, .default_domain_ops =3D &(const struct iommu_domain_ops) { .attach_dev =3D amd_iommu_attach_device, .map_pages =3D amd_iommu_map_pages, @@ -2639,6 +2675,77 @@ int amd_iommu_domain_enable_v2(struct iommu_domain *= dom, int pasids, bool giov) } EXPORT_SYMBOL(amd_iommu_domain_enable_v2); =20 +int amd_iommu_setup_gcr3_table(struct amd_iommu *iommu, struct pci_dev *pd= ev, + struct iommu_domain *dom, + struct iommu_domain *udom, + int pasids, bool giov) +{ + int levels; + struct protection_domain *pdom =3D to_pdomain(dom); + struct protection_domain *updom =3D to_pdomain(udom); + struct iommu_dev_data *dev_data =3D dev_iommu_priv_get(&pdev->dev); + + if (updom->gcr3_tbl) + return -EINVAL; + + /* Number of GCR3 table levels required */ + for (levels =3D 0; (pasids - 1) & ~0x1ff; pasids >>=3D 9) + levels +=3D 1; + + if (levels > amd_iommu_max_glx_val) + return -EINVAL; + + updom->gcr3_tbl =3D (void *)get_zeroed_page(GFP_ATOMIC); + if (updom->gcr3_tbl =3D=3D NULL) + return -ENOMEM; + + updom->glx =3D levels; + updom->flags |=3D PD_IOMMUV2_MASK; + if (giov) + updom->flags |=3D PD_GIOV_MASK; + + set_dte_entry(iommu, dev_data->devid, pdom, updom, + updom->gcr3_tbl, + dev_data->ats.enabled, false); + clone_aliases(iommu, dev_data->dev); + + iommu_flush_dte(iommu, dev_data->devid); + iommu_completion_wait(iommu); + return 0; +} + +/* + * Note: For vIOMMU, the guest could be using different + * GCR3 table for each VFIO pass-through device. + * Therefore, we need to per-device GCR3 table. + */ +int amd_iommu_user_set_gcr3(struct amd_iommu *iommu, + struct iommu_domain *dom, + struct iommu_domain *udom, + struct pci_dev *pdev, u32 pasid, + unsigned long cr3) +{ + struct iommu_dev_data *dev_data =3D dev_iommu_priv_get(&pdev->dev); + struct protection_domain *domain =3D to_pdomain(dom); + struct protection_domain *udomain =3D to_pdomain(udom); + unsigned long flags; + int ret; + + spin_lock_irqsave(&domain->lock, flags); + spin_lock_irqsave(&udomain->lock, flags); + + ret =3D __set_gcr3(udomain, pasid, cr3); + if (!ret) { + device_flush_dte(dev_data); + iommu_completion_wait(iommu); + } + + spin_unlock_irqrestore(&udomain->lock, flags); + spin_unlock_irqrestore(&domain->lock, flags); + + return ret; +} + static int __flush_pasid(struct protection_domain *domain, u32 pasid, u64 address, bool size) { diff --git a/drivers/iommu/amd/viommu.c b/drivers/iommu/amd/viommu.c index 1bd4282384c4..8ce3ee3d6bf5 100644 --- a/drivers/iommu/amd/viommu.c +++ b/drivers/iommu/amd/viommu.c @@ -1072,3 +1072,39 @@ int amd_viommu_cmdbuf_update(struct amd_viommu_cmdbu= f_data *data) return -EINVAL; } EXPORT_SYMBOL(amd_viommu_cmdbuf_update); + +int amd_viommu_user_gcr3_update(const void *user_data, struct iommu_domain= *udom) +{ + int ret; + struct pci_dev *pdev; + unsigned long npinned; + struct page *pages[2]; + struct iommu_domain *dom; + struct iommu_hwpt_amd_v2 *hwpt =3D (struct iommu_hwpt_amd_v2 *)user_data; + struct amd_iommu *iommu =3D get_amd_iommu_from_devid(hwpt->iommu_id); + u16 hdev_id =3D viommu_get_hdev_id(iommu, hwpt->gid, hwpt->gdev_id); + + pr_debug("%s: gid=3D%u, hdev_id=3D%#x, gcr3_va=3D%#llx\n", + __func__, hwpt->gid, hdev_id, (unsigned long long) hwpt->gcr3_va); + + npinned =3D get_user_pages_fast(hwpt->gcr3_va, 1, FOLL_WRITE, pages); + if (!npinned) { + pr_err("Failure locking grc3 page (%#llx).\n", hwpt->gcr3_va); + return -EINVAL; + } + + /* Allocate gcr3 table */ + pdev =3D pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(hdev_id), + hdev_id & 0xff); + dom =3D iommu_get_domain_for_dev(&pdev->dev); + if (!dom) + return -EINVAL; + + /* TODO: Only support 1 pasid (zero) for now */ + ret =3D amd_iommu_setup_gcr3_table(iommu, pdev, dom, udom, 1, + iommu_feature(iommu, FEATURE_GIOSUP)); + if (ret) + pr_err("%s: Fail to enable gcr3 (devid=3D%#x)\n", __func__, pci_dev_id(p= dev)); + + return amd_iommu_user_set_gcr3(iommu, dom, udom, pdev, 0, hwpt->gcr3); +} diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 4116f12d5f97..9239cd01d77c 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -236,6 +236,7 @@ union iommu_domain_user_data { #endif struct iommu_hwpt_vtd_s1 vtd; struct iommu_hwpt_arm_smmuv3 smmuv3; + struct iommu_hwpt_amd_v2 amdv2; }; =20 /** diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index f8ea9faf6770..4147171429e1 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -408,6 +408,23 @@ struct iommu_hwpt_arm_smmuv3 { __aligned_u64 out_event_uptr; }; =20 +/** + * struct iommu_hwpt_amd_v2 - AMD IOMMU specific user-managed + * v2 I/O page table data + * @gcr3: GCR3 guest physical ddress + * @gcr3_va: GCR3 host virtual address + * @gid: Guest ID + * @iommu_id: IOMMU host device ID + * @gdev_id: Guest device ID + */ +struct iommu_hwpt_amd_v2 { + __u64 gcr3; + __u64 gcr3_va; + __u32 gid; + __u32 iommu_id; + __u16 gdev_id; +}; + /** * enum iommu_hwpt_type - IOMMU HWPT Type * @IOMMU_HWPT_TYPE_DEFAULT: default @@ -418,6 +435,7 @@ enum iommu_hwpt_type { IOMMU_HWPT_TYPE_DEFAULT, IOMMU_HWPT_TYPE_VTD_S1, IOMMU_HWPT_TYPE_ARM_SMMUV3, + IOMMU_HWPT_TYPE_AMD_V2, }; =20 /** @@ -523,11 +541,13 @@ struct iommu_hw_info_amd { * enum iommu_hw_info_type - IOMMU Hardware Info Types * @IOMMU_HW_INFO_TYPE_INTEL_VTD: Intel VT-d iommu info type * @IOMMU_HW_INFO_TYPE_ARM_SMMUV3: ARM SMMUv3 iommu info type + * @IOMMU_HW_INFO_TYPE_AMD: AMD IOMMU info type */ enum iommu_hw_info_type { IOMMU_HW_INFO_TYPE_NONE, IOMMU_HW_INFO_TYPE_INTEL_VTD, IOMMU_HW_INFO_TYPE_ARM_SMMUV3, + IOMMU_HW_INFO_TYPE_AMD, }; =20 /** --=20 2.34.1 From nobody Sun Feb 8 05:19:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D6FAEB64D7 for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 23:56:07.2547 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7213e5fa-480b-4a71-3491-08db72b3149b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6812 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for AMD HW-vIOMMU in the iommufd /dev/iommu devfs. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/iommufd/Makefile | 3 +- drivers/iommu/iommufd/amd_viommu.c | 158 +++++++++++++++++++++++++++++ drivers/iommu/iommufd/main.c | 17 ++-- include/linux/amd-viommu.h | 26 +++++ include/linux/iommufd.h | 8 ++ 5 files changed, 203 insertions(+), 9 deletions(-) create mode 100644 drivers/iommu/iommufd/amd_viommu.c create mode 100644 include/linux/amd-viommu.h diff --git a/drivers/iommu/iommufd/Makefile b/drivers/iommu/iommufd/Makefile index 8aeba81800c5..84d771c9cfba 100644 --- a/drivers/iommu/iommufd/Makefile +++ b/drivers/iommu/iommufd/Makefile @@ -6,7 +6,8 @@ iommufd-y :=3D \ ioas.o \ main.o \ pages.o \ - vfio_compat.o + vfio_compat.o \ + amd_viommu.o =20 iommufd-$(CONFIG_IOMMUFD_TEST) +=3D selftest.o =20 diff --git a/drivers/iommu/iommufd/amd_viommu.c b/drivers/iommu/iommufd/amd= _viommu.c new file mode 100644 index 000000000000..1836e19cb37d --- /dev/null +++ b/drivers/iommu/iommufd/amd_viommu.c @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Advanced Micro Devices, Inc. + * Author: Suravee Suthikulpanit + */ + +#include +#include +#include +#include +#include + +#include "iommufd_private.h" + +union amd_viommu_ucmd_buffer { + struct amd_viommu_iommu_info iommu; + struct amd_viommu_dev_info dev; + struct amd_viommu_dom_info dom; + struct amd_viommu_mmio_data mmio; + struct amd_viommu_cmdbuf_data cmdbuf; +}; + +#define IOCTL_OP(_ioctl, _fn, _struct, _last) = \ + [_IOC_NR(_ioctl) - IOMMUFD_VIOMMU_CMD_BASE] =3D { \ + .size =3D sizeof(_struct) + \ + BUILD_BUG_ON_ZERO(sizeof(union amd_viommu_ucmd_buffer) < \ + sizeof(_struct)), \ + .min_size =3D offsetofend(_struct, _last), \ + .ioctl_num =3D _ioctl, \ + .execute =3D _fn, \ + } + +int viommu_iommu_init(struct iommufd_ucmd *ucmd) +{ + int ret; + struct amd_viommu_iommu_info *data =3D ucmd->cmd; + + ret =3D amd_viommu_iommu_init(data); + if (ret) + return ret; + + if (copy_to_user(ucmd->ubuffer, data, sizeof(*data))) + ret =3D -EFAULT; + return ret; +} + +int viommu_iommu_destroy(struct iommufd_ucmd *ucmd) +{ + struct amd_viommu_iommu_info *data =3D ucmd->cmd; + + return amd_viommu_iommu_destroy(data); +} + +int viommu_domain_attach(struct iommufd_ucmd *ucmd) +{ + struct amd_viommu_dom_info *data =3D ucmd->cmd; + + return amd_viommu_domain_update(data, true); +} + +int viommu_domain_detach(struct iommufd_ucmd *ucmd) +{ + struct amd_viommu_dom_info *data =3D ucmd->cmd; + + return amd_viommu_domain_update(data, false); +} + +int viommu_device_attach(struct iommufd_ucmd *ucmd) +{ + struct amd_viommu_dev_info *data =3D ucmd->cmd; + + return amd_viommu_device_update(data, true); +} + +int viommu_device_detach(struct iommufd_ucmd *ucmd) +{ + struct amd_viommu_dev_info *data =3D ucmd->cmd; + + return amd_viommu_device_update(data, false); +} + +int viommu_mmio_access(struct iommufd_ucmd *ucmd) +{ + int ret; + struct amd_viommu_mmio_data *data =3D ucmd->cmd; + + if (data->is_write) { + ret =3D amd_viommu_guest_mmio_write(data); + } else { + ret =3D amd_viommu_guest_mmio_read(data); + if (ret) + return ret; + + if (copy_to_user(ucmd->ubuffer, data, sizeof(*data))) + ret =3D -EFAULT; + } + return ret; +} + +int viommu_cmdbuf_update(struct iommufd_ucmd *ucmd) +{ + struct amd_viommu_cmdbuf_data *data =3D ucmd->cmd; + + return amd_viommu_cmdbuf_update(data); +} + +struct iommufd_ioctl_op viommu_ioctl_ops[] =3D { + IOCTL_OP(VIOMMU_IOMMU_INIT, viommu_iommu_init, + struct amd_viommu_iommu_info, gid), + IOCTL_OP(VIOMMU_IOMMU_DESTROY, viommu_iommu_destroy, + struct amd_viommu_iommu_info, gid), + IOCTL_OP(VIOMMU_DEVICE_ATTACH, viommu_device_attach, + struct amd_viommu_dev_info, queue_id), + IOCTL_OP(VIOMMU_DEVICE_DETACH, viommu_device_detach, + struct amd_viommu_dev_info, queue_id), + IOCTL_OP(VIOMMU_DOMAIN_ATTACH, viommu_domain_attach, + struct amd_viommu_dom_info, gdom_id), + IOCTL_OP(VIOMMU_DOMAIN_DETACH, viommu_domain_detach, + struct amd_viommu_dom_info, gdom_id), + IOCTL_OP(VIOMMU_MMIO_ACCESS, viommu_mmio_access, + struct amd_viommu_mmio_data, is_write), + IOCTL_OP(VIOMMU_CMDBUF_UPDATE, viommu_cmdbuf_update, + struct amd_viommu_cmdbuf_data, hva), +}; + +long iommufd_amd_viommu_ioctl(struct file *filp, unsigned int cmd, unsigne= d long arg) +{ + struct iommufd_ctx *ictx =3D filp->private_data; + struct iommufd_ucmd ucmd =3D {}; + struct iommufd_ioctl_op *op; + union amd_viommu_ucmd_buffer buf; + unsigned int nr; + int ret; + + nr =3D _IOC_NR(cmd); + if (nr < IOMMUFD_VIOMMU_CMD_BASE || + (nr - IOMMUFD_VIOMMU_CMD_BASE) >=3D ARRAY_SIZE(viommu_ioctl_ops)) + return -ENOIOCTLCMD; + + ucmd.ictx =3D ictx; + ucmd.ubuffer =3D (void __user *)arg; + ret =3D get_user(ucmd.user_size, (u32 __user *)ucmd.ubuffer); + if (ret) + return ret; + + op =3D &viommu_ioctl_ops[nr - IOMMUFD_VIOMMU_CMD_BASE]; + if (op->ioctl_num !=3D cmd) + return -ENOIOCTLCMD; + if (ucmd.user_size < op->min_size) + return -EOPNOTSUPP; + + ucmd.cmd =3D &buf; + ret =3D copy_struct_from_user(ucmd.cmd, op->size, ucmd.ubuffer, + ucmd.user_size); + if (ret) + return ret; + return op->execute(&ucmd); +} diff --git a/drivers/iommu/iommufd/main.c b/drivers/iommu/iommufd/main.c index 83f8b8f19bcb..d5c2738a8355 100644 --- a/drivers/iommu/iommufd/main.c +++ b/drivers/iommu/iommufd/main.c @@ -17,6 +17,8 @@ #include #include #include +#include +#include #include "../iommu-priv.h" =20 #include "io_pagetable.h" @@ -442,13 +444,6 @@ union ucmd_buffer { struct iommu_hwpt_arm_smmuv3_invalidate smmuv3; }; =20 -struct iommufd_ioctl_op { - unsigned int size; - unsigned int min_size; - unsigned int ioctl_num; - int (*execute)(struct iommufd_ucmd *ucmd); -}; - #define IOCTL_OP(_ioctl, _fn, _struct, _last) = \ [_IOC_NR(_ioctl) - IOMMUFD_CMD_BASE] =3D { \ .size =3D sizeof(_struct) + \ @@ -503,8 +498,14 @@ static long iommufd_fops_ioctl(struct file *filp, unsi= gned int cmd, =20 nr =3D _IOC_NR(cmd); if (nr < IOMMUFD_CMD_BASE || - (nr - IOMMUFD_CMD_BASE) >=3D ARRAY_SIZE(iommufd_ioctl_ops)) + (nr - IOMMUFD_CMD_BASE) >=3D ARRAY_SIZE(iommufd_ioctl_ops)) { + /* AMD VIOMMU ioctl */ + if (!iommufd_amd_viommu_ioctl(filp, cmd, arg)) + return 0; + + /* VFIO ioctl */ return iommufd_vfio_ioctl(ictx, cmd, arg); + } =20 ucmd.ictx =3D ictx; ucmd.ubuffer =3D (void __user *)arg; diff --git a/include/linux/amd-viommu.h b/include/linux/amd-viommu.h new file mode 100644 index 000000000000..645e25c493c2 --- /dev/null +++ b/include/linux/amd-viommu.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2022 Advanced Micro Devices, Inc. + */ + +#ifndef _LINUX_AMD_VIOMMU_H +#define _LINUX_AMD_VIOMMU_H + +#include + +extern long iommufd_amd_viommu_ioctl(struct file *filp, + unsigned int cmd, + unsigned long arg); + +extern long iommufd_viommu_ioctl(struct file *filp, unsigned int cmd, + unsigned long arg); + +extern int amd_viommu_iommu_init(struct amd_viommu_iommu_info *data); +extern int amd_viommu_iommu_destroy(struct amd_viommu_iommu_info *data); +extern int amd_viommu_domain_update(struct amd_viommu_dom_info *data, bool= is_set); +extern int amd_viommu_device_update(struct amd_viommu_dev_info *data, bool= is_set); +extern int amd_viommu_guest_mmio_write(struct amd_viommu_mmio_data *data); +extern int amd_viommu_guest_mmio_read(struct amd_viommu_mmio_data *data); +extern int amd_viommu_cmdbuf_update(struct amd_viommu_cmdbuf_data *data); + +#endif /* _LINUX_AMD_VIOMMU_H */ diff --git a/include/linux/iommufd.h b/include/linux/iommufd.h index 9269ce668d9b..91912e044038 100644 --- a/include/linux/iommufd.h +++ b/include/linux/iommufd.h @@ -17,6 +17,14 @@ struct iommufd_ctx; struct iommufd_access; struct file; struct iommu_group; +struct iommufd_ucmd; + +struct iommufd_ioctl_op { + unsigned int size; + unsigned int min_size; + unsigned int ioctl_num; + int (*execute)(struct iommufd_ucmd *ucmd); +}; =20 struct iommufd_device *iommufd_device_bind(struct iommufd_ctx *ictx, struct device *dev, u32 *id); --=20 2.34.1