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Wed, 21 Jun 2023 06:44:07 -0700 From: Sumit Gupta To: , , , , CC: , , Subject: [Patch RESEND 1/4] memory: tegra: sort tegra234_mc_clients table as per register offsets Date: Wed, 21 Jun 2023 19:13:57 +0530 Message-ID: <20230621134400.23070-2-sumitg@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230621134400.23070-1-sumitg@nvidia.com> References: <20230621134400.23070-1-sumitg@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636B:EE_|DM6PR12MB4465:EE_ X-MS-Office365-Filtering-Correlation-Id: 90f26f89-4be9-4041-6ab7-08db725d9b00 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nXTrn/PmFHRSIW5uZjZ9CKZC8uM2QOEY7lrx+8cofp1h/aJu+5tmyUK6aNUKw2cQzEGIhNY1UkpVNTq6ULCQ5tAPHAgVriDX0V+2VgNVFtSrGhgWcEaKw5eDK3tPU8WwzAJ1TEgKeXmh5qyu9sxfDVGfSZ42T0K/0wzLZzUQ9eAM2SB1EgkZI1JgMXsbUQ1WAwe4ZbgthUfSHYW9FQo+OnIeG9f+Lal2sGqcVhEL9d7zSb4EfJ+xtaAWniAAx1SO2lq13ESxUHM4KjYg/56rPG3WkN8Ih421Rj+PS8ntbEX4g1665fbuxDgbCjgqhqpq9+jp0LjJObeeDJ0X9VXKraH6usOKo8FeUreuIEvN7s9nHKpoDvp1V5wlATiiIQXsx3gA+ueQJklCE5jQ9zZd5vbir5DDIXnH5rgwIMb0JUidqPhlIIRBWA9oNK+u2mEhFBKZIl3XxwV/gYFZ38byzcCbSl3Yym7FZFacnIJPHe9NhLb20jubN1T/dBWnIj/9BrYcPMtB/njvlaMJ7FTzrmLm/uNN5aVTrenyPzm1IojRYYUz8mTJUecWb18gaePJO/QvwwLKaxbm8AzbtWfe67/Ttp2+13LeA/YOE8WIDw6CkyUSSSWMsJ+7qvSC6dMuHTIAizi39F0gJd75AJ9IWXyGD7UDJfGaPZHc3US5meFL5HjZcRDPVP+DOdf2dUK7ms+HRpumZmqMFFW/bnaodQlV6QiYfCVN9Fvkc6AlLE99lSEBioFn40j8crxMXiFA X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230028)(4636009)(396003)(136003)(346002)(39860400002)(376002)(451199021)(36840700001)(46966006)(40470700004)(336012)(83380400001)(82310400005)(426003)(2616005)(8936002)(8676002)(41300700001)(4326008)(70206006)(5660300002)(70586007)(316002)(40460700003)(86362001)(36756003)(26005)(186003)(1076003)(107886003)(82740400003)(47076005)(36860700001)(6666004)(2906002)(478600001)(30864003)(7696005)(40480700001)(7636003)(110136005)(54906003)(356005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 13:44:15.9827 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 90f26f89-4be9-4041-6ab7-08db725d9b00 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4465 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Sort the MC client entries in "tegra234_mc_clients" table as per the override and security register offsets. This will help to avoid creating duplicate entries. Signed-off-by: Sumit Gupta Acked-by: Thierry Reding --- drivers/memory/tegra/tegra234.c | 514 ++++++++++++++++---------------- 1 file changed, 259 insertions(+), 255 deletions(-) diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra23= 4.c index 8e873a7bc34f..3e44efe4541e 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -12,6 +12,10 @@ #include #include "mc.h" =20 +/* + * MC Client entries are sorted in the increasing order of the + * override and security register offsets. + */ static const struct tegra_mc_client tegra234_mc_clients[] =3D { { .id =3D TEGRA234_MEMORY_CLIENT_HDAR, @@ -25,6 +29,106 @@ static const struct tegra_mc_client tegra234_mc_clients= [] =3D { .security =3D 0xac, }, }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE6AR, + .name =3D "pcie6ar", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_6, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_PCIE6, + .regs =3D { + .sid =3D { + .override =3D 0x140, + .security =3D 0x144, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE6AW, + .name =3D "pcie6aw", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_6, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_PCIE6, + .regs =3D { + .sid =3D { + .override =3D 0x148, + .security =3D 0x14c, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE7AR, + .name =3D "pcie7ar", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_7, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_PCIE7, + .regs =3D { + .sid =3D { + .override =3D 0x150, + .security =3D 0x154, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_DLA0RDB, + .name =3D "dla0rdb", + .sid =3D TEGRA234_SID_NVDLA0, + .regs =3D { + .sid =3D { + .override =3D 0x160, + .security =3D 0x164, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_DLA0RDB1, + .name =3D "dla0rdb1", + .sid =3D TEGRA234_SID_NVDLA0, + .regs =3D { + .sid =3D { + .override =3D 0x168, + .security =3D 0x16c, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_DLA0WRB, + .name =3D "dla0wrb", + .sid =3D TEGRA234_SID_NVDLA0, + .regs =3D { + .sid =3D { + .override =3D 0x170, + .security =3D 0x174, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_DLA1RDB, + .name =3D "dla0rdb", + .sid =3D TEGRA234_SID_NVDLA1, + .regs =3D { + .sid =3D { + .override =3D 0x178, + .security =3D 0x17c, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE7AW, + .name =3D "pcie7aw", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_7, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_PCIE7, + .regs =3D { + .sid =3D { + .override =3D 0x180, + .security =3D 0x184, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE8AR, + .name =3D "pcie8ar", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_8, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_PCIE8, + .regs =3D { + .sid =3D { + .override =3D 0x190, + .security =3D 0x194, + }, + }, }, { .id =3D TEGRA234_MEMORY_CLIENT_HDAW, .name =3D "hdaw", @@ -37,6 +141,102 @@ static const struct tegra_mc_client tegra234_mc_client= s[] =3D { .security =3D 0x1ac, }, }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE8AW, + .name =3D "pcie8aw", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_8, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_PCIE8, + .regs =3D { + .sid =3D { + .override =3D 0x1d8, + .security =3D 0x1dc, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE9AR, + .name =3D "pcie9ar", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_9, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_PCIE9, + .regs =3D { + .sid =3D { + .override =3D 0x1e0, + .security =3D 0x1e4, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE6AR1, + .name =3D "pcie6ar1", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_6, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_PCIE6, + .regs =3D { + .sid =3D { + .override =3D 0x1e8, + .security =3D 0x1ec, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE9AW, + .name =3D "pcie9aw", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_9, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_PCIE9, + .regs =3D { + .sid =3D { + .override =3D 0x1f0, + .security =3D 0x1f4, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE10AR, + .name =3D "pcie10ar", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_10, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_PCIE10, + .regs =3D { + .sid =3D { + .override =3D 0x1f8, + .security =3D 0x1fc, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE10AW, + .name =3D "pcie10aw", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_10, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_PCIE10, + .regs =3D { + .sid =3D { + .override =3D 0x200, + .security =3D 0x204, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE10AR1, + .name =3D "pcie10ar1", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_10, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_PCIE10, + .regs =3D { + .sid =3D { + .override =3D 0x240, + .security =3D 0x244, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE7AR1, + .name =3D "pcie7ar1", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_7, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_PCIE7, + .regs =3D { + .sid =3D { + .override =3D 0x248, + .security =3D 0x24c, + }, + }, }, { .id =3D TEGRA234_MEMORY_CLIENT_MGBEARD, .name =3D "mgbeard", @@ -157,6 +357,26 @@ static const struct tegra_mc_client tegra234_mc_client= s[] =3D { .security =3D 0x33c, }, }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_DLA1RDB1, + .name =3D "dla0rdb1", + .sid =3D TEGRA234_SID_NVDLA1, + .regs =3D { + .sid =3D { + .override =3D 0x370, + .security =3D 0x374, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_DLA1WRB, + .name =3D "dla0wrb", + .sid =3D TEGRA234_SID_NVDLA1, + .regs =3D { + .sid =3D { + .override =3D 0x378, + .security =3D 0x37c, + }, + }, }, { .id =3D TEGRA234_MEMORY_CLIENT_VI2W, .name =3D "vi2w", @@ -181,18 +401,6 @@ static const struct tegra_mc_client tegra234_mc_client= s[] =3D { .security =3D 0x38c, }, }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_VI2FALW, - .name =3D "vi2falw", - .bpmp_id =3D TEGRA_ICC_BPMP_VI2FAL, - .type =3D TEGRA_ICC_ISO_VIFAL, - .sid =3D TEGRA234_SID_ISO_VI2FALC, - .regs =3D { - .sid =3D { - .override =3D 0x3e0, - .security =3D 0x3e4, - }, - }, }, { .id =3D TEGRA234_MEMORY_CLIENT_APER, .name =3D "aper", @@ -218,27 +426,27 @@ static const struct tegra_mc_client tegra234_mc_clien= ts[] =3D { }, }, }, { - .id =3D TEGRA234_MEMORY_CLIENT_NVDISPLAYR, - .name =3D "nvdisplayr", - .bpmp_id =3D TEGRA_ICC_BPMP_DISPLAY, - .type =3D TEGRA_ICC_ISO_DISPLAY, - .sid =3D TEGRA234_SID_ISO_NVDISPLAY, + .id =3D TEGRA234_MEMORY_CLIENT_VI2FALW, + .name =3D "vi2falw", + .bpmp_id =3D TEGRA_ICC_BPMP_VI2FAL, + .type =3D TEGRA_ICC_ISO_VIFAL, + .sid =3D TEGRA234_SID_ISO_VI2FALC, .regs =3D { .sid =3D { - .override =3D 0x490, - .security =3D 0x494, + .override =3D 0x3e0, + .security =3D 0x3e4, }, }, }, { - .id =3D TEGRA234_MEMORY_CLIENT_NVDISPLAYR1, - .name =3D "nvdisplayr1", + .id =3D TEGRA234_MEMORY_CLIENT_NVDISPLAYR, + .name =3D "nvdisplayr", .bpmp_id =3D TEGRA_ICC_BPMP_DISPLAY, .type =3D TEGRA_ICC_ISO_DISPLAY, .sid =3D TEGRA234_SID_ISO_NVDISPLAY, .regs =3D { .sid =3D { - .override =3D 0x508, - .security =3D 0x50c, + .override =3D 0x490, + .security =3D 0x494, }, }, }, { @@ -305,6 +513,18 @@ static const struct tegra_mc_client tegra234_mc_client= s[] =3D { .security =3D 0x504, }, }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_NVDISPLAYR1, + .name =3D "nvdisplayr1", + .bpmp_id =3D TEGRA_ICC_BPMP_DISPLAY, + .type =3D TEGRA_ICC_ISO_DISPLAY, + .sid =3D TEGRA234_SID_ISO_NVDISPLAY, + .regs =3D { + .sid =3D { + .override =3D 0x508, + .security =3D 0x50c, + }, + }, }, { .id =3D TEGRA234_MEMORY_CLIENT_DLA0RDA, .name =3D "dla0rda", @@ -335,26 +555,6 @@ static const struct tegra_mc_client tegra234_mc_client= s[] =3D { .security =3D 0x604, }, }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_DLA0RDB, - .name =3D "dla0rdb", - .sid =3D TEGRA234_SID_NVDLA0, - .regs =3D { - .sid =3D { - .override =3D 0x160, - .security =3D 0x164, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_DLA0RDA1, - .name =3D "dla0rda1", - .sid =3D TEGRA234_SID_NVDLA0, - .regs =3D { - .sid =3D { - .override =3D 0x748, - .security =3D 0x74c, - }, - }, }, { .id =3D TEGRA234_MEMORY_CLIENT_DLA0FALWRB, .name =3D "dla0falwrb", @@ -365,26 +565,6 @@ static const struct tegra_mc_client tegra234_mc_client= s[] =3D { .security =3D 0x60c, }, }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_DLA0RDB1, - .name =3D "dla0rdb1", - .sid =3D TEGRA234_SID_NVDLA0, - .regs =3D { - .sid =3D { - .override =3D 0x168, - .security =3D 0x16c, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_DLA0WRB, - .name =3D "dla0wrb", - .sid =3D TEGRA234_SID_NVDLA0, - .regs =3D { - .sid =3D { - .override =3D 0x170, - .security =3D 0x174, - }, - }, }, { .id =3D TEGRA234_MEMORY_CLIENT_DLA1RDA, .name =3D "dla0rda", @@ -415,26 +595,6 @@ static const struct tegra_mc_client tegra234_mc_client= s[] =3D { .security =3D 0x624, }, }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_DLA1RDB, - .name =3D "dla0rdb", - .sid =3D TEGRA234_SID_NVDLA1, - .regs =3D { - .sid =3D { - .override =3D 0x178, - .security =3D 0x17c, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_DLA1RDA1, - .name =3D "dla0rda1", - .sid =3D TEGRA234_SID_NVDLA1, - .regs =3D { - .sid =3D { - .override =3D 0x750, - .security =3D 0x754, - }, - }, }, { .id =3D TEGRA234_MEMORY_CLIENT_DLA1FALWRB, .name =3D "dla0falwrb", @@ -445,26 +605,6 @@ static const struct tegra_mc_client tegra234_mc_client= s[] =3D { .security =3D 0x62c, }, }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_DLA1RDB1, - .name =3D "dla0rdb1", - .sid =3D TEGRA234_SID_NVDLA1, - .regs =3D { - .sid =3D { - .override =3D 0x370, - .security =3D 0x374, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_DLA1WRB, - .name =3D "dla0wrb", - .sid =3D TEGRA234_SID_NVDLA1, - .regs =3D { - .sid =3D { - .override =3D 0x378, - .security =3D 0x37c, - }, - }, }, { .id =3D TEGRA234_MEMORY_CLIENT_PCIE0R, .name =3D "pcie0r", @@ -610,171 +750,35 @@ static const struct tegra_mc_client tegra234_mc_clie= nts[] =3D { }, }, }, { - .id =3D TEGRA234_MEMORY_CLIENT_PCIE5R1, - .name =3D "pcie5r1", - .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_5, - .type =3D TEGRA_ICC_NISO, - .sid =3D TEGRA234_SID_PCIE5, - .regs =3D { - .sid =3D { - .override =3D 0x778, - .security =3D 0x77c, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_PCIE6AR, - .name =3D "pcie6ar", - .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_6, - .type =3D TEGRA_ICC_NISO, - .sid =3D TEGRA234_SID_PCIE6, - .regs =3D { - .sid =3D { - .override =3D 0x140, - .security =3D 0x144, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_PCIE6AW, - .name =3D "pcie6aw", - .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_6, - .type =3D TEGRA_ICC_NISO, - .sid =3D TEGRA234_SID_PCIE6, - .regs =3D { - .sid =3D { - .override =3D 0x148, - .security =3D 0x14c, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_PCIE6AR1, - .name =3D "pcie6ar1", - .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_6, - .type =3D TEGRA_ICC_NISO, - .sid =3D TEGRA234_SID_PCIE6, - .regs =3D { - .sid =3D { - .override =3D 0x1e8, - .security =3D 0x1ec, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_PCIE7AR, - .name =3D "pcie7ar", - .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_7, - .type =3D TEGRA_ICC_NISO, - .sid =3D TEGRA234_SID_PCIE7, - .regs =3D { - .sid =3D { - .override =3D 0x150, - .security =3D 0x154, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_PCIE7AW, - .name =3D "pcie7aw", - .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_7, - .type =3D TEGRA_ICC_NISO, - .sid =3D TEGRA234_SID_PCIE7, - .regs =3D { - .sid =3D { - .override =3D 0x180, - .security =3D 0x184, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_PCIE7AR1, - .name =3D "pcie7ar1", - .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_7, - .type =3D TEGRA_ICC_NISO, - .sid =3D TEGRA234_SID_PCIE7, - .regs =3D { - .sid =3D { - .override =3D 0x248, - .security =3D 0x24c, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_PCIE8AR, - .name =3D "pcie8ar", - .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_8, - .type =3D TEGRA_ICC_NISO, - .sid =3D TEGRA234_SID_PCIE8, - .regs =3D { - .sid =3D { - .override =3D 0x190, - .security =3D 0x194, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_PCIE8AW, - .name =3D "pcie8aw", - .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_8, - .type =3D TEGRA_ICC_NISO, - .sid =3D TEGRA234_SID_PCIE8, - .regs =3D { - .sid =3D { - .override =3D 0x1d8, - .security =3D 0x1dc, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_PCIE9AR, - .name =3D "pcie9ar", - .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_9, - .type =3D TEGRA_ICC_NISO, - .sid =3D TEGRA234_SID_PCIE9, - .regs =3D { - .sid =3D { - .override =3D 0x1e0, - .security =3D 0x1e4, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_PCIE9AW, - .name =3D "pcie9aw", - .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_9, - .type =3D TEGRA_ICC_NISO, - .sid =3D TEGRA234_SID_PCIE9, - .regs =3D { - .sid =3D { - .override =3D 0x1f0, - .security =3D 0x1f4, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_PCIE10AR, - .name =3D "pcie10ar", - .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_10, - .type =3D TEGRA_ICC_NISO, - .sid =3D TEGRA234_SID_PCIE10, + .id =3D TEGRA234_MEMORY_CLIENT_DLA0RDA1, + .name =3D "dla0rda1", + .sid =3D TEGRA234_SID_NVDLA0, .regs =3D { .sid =3D { - .override =3D 0x1f8, - .security =3D 0x1fc, + .override =3D 0x748, + .security =3D 0x74c, }, }, }, { - .id =3D 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X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8152 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add entries for VIC, NVDEC, NVENC, NVJPG memory controller clients into the 'tegra_234_mc_clients' table. Signed-off-by: Johnny Liu Signed-off-by: Sumit Gupta Acked-by: Thierry Reding --- drivers/memory/tegra/tegra234.c | 120 ++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra23= 4.c index 3e44efe4541e..bc73be7fe143 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -29,6 +29,18 @@ static const struct tegra_mc_client tegra234_mc_clients[= ] =3D { .security =3D 0xac, }, }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_NVENCSRD, + .name =3D "nvencsrd", + .bpmp_id =3D TEGRA_ICC_BPMP_NVENC, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_NVENC, + .regs =3D { + .sid =3D { + .override =3D 0xe0, + .security =3D 0xe4, + }, + }, }, { .id =3D TEGRA234_MEMORY_CLIENT_PCIE6AR, .name =3D "pcie6ar", @@ -65,6 +77,18 @@ static const struct tegra_mc_client tegra234_mc_clients[= ] =3D { .security =3D 0x154, }, }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_NVENCSWR, + .name =3D "nvencswr", + .bpmp_id =3D TEGRA_ICC_BPMP_NVENC, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_NVENC, + .regs =3D { + .sid =3D { + .override =3D 0x158, + .security =3D 0x15c, + }, + }, }, { .id =3D TEGRA234_MEMORY_CLIENT_DLA0RDB, .name =3D "dla0rdb", @@ -357,6 +381,30 @@ static const struct tegra_mc_client tegra234_mc_client= s[] =3D { .security =3D 0x33c, }, }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_VICSRD, + .name =3D "vicsrd", + .bpmp_id =3D TEGRA_ICC_BPMP_VIC, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_VIC, + .regs =3D { + .sid =3D { + .override =3D 0x360, + .security =3D 0x364, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_VICSWR, + .name =3D "vicswr", + .bpmp_id =3D TEGRA_ICC_BPMP_VIC, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_VIC, + .regs =3D { + .sid =3D { + .override =3D 0x368, + .security =3D 0x36c, + }, + }, }, { .id =3D TEGRA234_MEMORY_CLIENT_DLA1RDB1, .name =3D "dla0rdb1", @@ -401,6 +449,30 @@ static const struct tegra_mc_client tegra234_mc_client= s[] =3D { .security =3D 0x38c, }, }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_NVDECSRD, + .name =3D "nvdecsrd", + .bpmp_id =3D TEGRA_ICC_BPMP_NVDEC, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_NVDEC, + .regs =3D { + .sid =3D { + .override =3D 0x3c0, + .security =3D 0x3c4, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_NVDECSWR, + .name =3D "nvdecswr", + .bpmp_id =3D TEGRA_ICC_BPMP_NVDEC, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_NVDEC, + .regs =3D { + .sid =3D { + .override =3D 0x3c8, + .security =3D 0x3cc, + }, + }, }, { .id =3D TEGRA234_MEMORY_CLIENT_APER, .name =3D "aper", @@ -437,6 +509,30 @@ static const struct tegra_mc_client tegra234_mc_client= s[] =3D { .security =3D 0x3e4, }, }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_NVJPGSRD, + .name =3D "nvjpgsrd", + .bpmp_id =3D TEGRA_ICC_BPMP_NVJPG_0, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_NVJPG, + .regs =3D { + .sid =3D { + .override =3D 0x3f0, + .security =3D 0x3f4, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_NVJPGSWR, + .name =3D "nvjpgswr", + .bpmp_id =3D TEGRA_ICC_BPMP_NVJPG_0, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_NVJPG, + .regs =3D { + .sid =3D { + .override =3D 0x3f8, + .security =3D 0x3fc, + }, + }, }, { .id =3D TEGRA234_MEMORY_CLIENT_NVDISPLAYR, .name =3D "nvdisplayr", @@ -781,6 +877,30 @@ static const struct tegra_mc_client tegra234_mc_client= s[] =3D { .security =3D 0x77c, }, }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_NVJPG1SRD, + .name =3D "nvjpg1srd", + .bpmp_id =3D TEGRA_ICC_BPMP_NVJPG_1, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_NVJPG1, + .regs =3D { + .sid =3D { + .override =3D 0x918, + .security =3D 0x91c, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_NVJPG1SWR, + .name =3D "nvjpg1swr", + .bpmp_id =3D TEGRA_ICC_BPMP_NVJPG_1, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_NVJPG1, + .regs =3D { + .sid =3D { + .override =3D 0x920, + .security =3D 0x924, + }, + }, }, { .id =3D TEGRA_ICC_MC_CPU_CLUSTER0, .name =3D "sw_cluster0", --=20 2.17.1 From nobody Sun Feb 8 02:22:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51CECEB64D7 for ; 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Wed, 21 Jun 2023 06:44:16 -0700 From: Sumit Gupta To: , , , , CC: , , Subject: [Patch RESEND 3/4] memory: tegra: add check if MRQ_EMC_DVFS_LATENCY is supported Date: Wed, 21 Jun 2023 19:13:59 +0530 Message-ID: <20230621134400.23070-4-sumitg@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230621134400.23070-1-sumitg@nvidia.com> References: <20230621134400.23070-1-sumitg@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00026367:EE_|IA1PR12MB6412:EE_ X-MS-Office365-Filtering-Correlation-Id: 8b6917cb-5ad0-4c32-631d-08db725d9f97 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: fjemLxqa97PWSC+GYOp5isR+Ix2/HixmOKykKGUhljS49vm7CxSy7em6GiuvKl88kz0d4NWoHZ4fTRjHeFWKB5hVHerCT3wJZ5Skw+UdHbZ1mt9zB0ApfiG2c3uQu/IbSqroRPjsjmITg2xDmYvETkn3lA1XBDffYBtsCZjV9SdPtM4nDsDj7NSfs2Vu3cEgG6YZPRga9CqPK2wXgHjg+xJfV2mZP+w8k+Wg0EfvHsBbwWpJrc7AP7j+mxbuGvnm+mmtjnMSDZ/OWJE2vGl8XFGIUX+62h1kxJGBzuXmZvPKO0KXamlZGQ/denbw/p/Ekn+9MUT/KodBQ8f+mZjq268dnep/PWaEmePdLd6UYlP8clgVMyZgVXlR1z7rfL3CIOLswyrhlLmFaHc/2KkF26xaGhJMbtrqum5cc+aOY/oZtODGjEfcGECap59Es/AyBUovHnVaYWxtvKLtXWi768pLqIJdG/Tsgys+Io4vtKIXLnYaPjvtfWMeakcbe2Bztr98GIN3GWhOiE6OOIpT64z1wfDKHRVEKso4Jmxy3WaCvWOEWfX4m1cwI/REExT16BBvTE7578Ab7fr/7pBzS4h6lbSc5CdFgsriov6iDd07RVBEYXnQoROsfURh4ZEU9u18+Ez9PZAHvP19JHz4Ubmgx4cKGQyFKznELF113xTfkSwEKwKk0CfvSUSVxDBCaNcHBUxQC4+1OMS3DRX5PiD493+ZPzfg7osib0Je/vMS4LCA7+QMDI/R/7wpgC5s X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230028)(4636009)(376002)(346002)(396003)(39860400002)(136003)(451199021)(40470700004)(46966006)(36840700001)(6666004)(478600001)(54906003)(110136005)(4326008)(47076005)(40480700001)(336012)(426003)(83380400001)(2616005)(86362001)(36756003)(36860700001)(40460700003)(2906002)(70586007)(82310400005)(186003)(7696005)(1076003)(107886003)(26005)(356005)(82740400003)(7636003)(316002)(70206006)(8676002)(8936002)(41300700001)(5660300002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 13:44:23.6830 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8b6917cb-5ad0-4c32-631d-08db725d9f97 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00026367.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6412 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add check to ensure that "MRQ_EMC_DVFS_LATENCY" is supported by the BPMP-FW before making the MRQ request. Currently, if the BPMP-FW doesn't support this MRQ, then the "tegra186_emc_probe" fails. Due to this the Memory Interconnect initialization also doesn't happen. Memory Interconnect is not dependent on this MRQ and can initialize even when this MRQ is not supported in any platform. The check ensures that the MRQ is called only when it is supported by the BPMP-FW and Interconnect initializes independent of this MRQ. Also, moved the code to new function for better readability. Signed-off-by: Sumit Gupta Acked-by: Thierry Reding --- drivers/memory/tegra/tegra186-emc.c | 136 +++++++++++++++------------- 1 file changed, 71 insertions(+), 65 deletions(-) diff --git a/drivers/memory/tegra/tegra186-emc.c b/drivers/memory/tegra/teg= ra186-emc.c index 6ad8a4023dd7..83981ae3ea86 100644 --- a/drivers/memory/tegra/tegra186-emc.c +++ b/drivers/memory/tegra/tegra186-emc.c @@ -155,6 +155,73 @@ DEFINE_DEBUGFS_ATTRIBUTE(tegra186_emc_debug_max_rate_f= ops, tegra186_emc_debug_max_rate_get, tegra186_emc_debug_max_rate_set, "%llu\n"); =20 +static int tegra186_emc_get_emc_dvfs_latency(struct tegra186_emc *emc) +{ + struct mrq_emc_dvfs_latency_response response; + struct tegra_bpmp_message msg; + unsigned int i; + int err; + + memset(&msg, 0, sizeof(msg)); + msg.mrq =3D MRQ_EMC_DVFS_LATENCY; + msg.tx.data =3D NULL; + msg.tx.size =3D 0; + msg.rx.data =3D &response; + msg.rx.size =3D sizeof(response); + + err =3D tegra_bpmp_transfer(emc->bpmp, &msg); + if (err < 0) { + dev_err(emc->dev, "failed to EMC DVFS pairs: %d\n", err); + return err; + } + if (msg.rx.ret < 0) { + dev_err(emc->dev, "EMC DVFS MRQ failed: %d (BPMP error code)\n", msg.rx.= ret); + return -EINVAL; + } + + emc->debugfs.min_rate =3D ULONG_MAX; + emc->debugfs.max_rate =3D 0; + + emc->num_dvfs =3D response.num_pairs; + + emc->dvfs =3D devm_kmalloc_array(emc->dev, emc->num_dvfs, sizeof(*emc->dv= fs), GFP_KERNEL); + if (!emc->dvfs) + return -ENOMEM; + + dev_dbg(emc->dev, "%u DVFS pairs:\n", emc->num_dvfs); + + for (i =3D 0; i < emc->num_dvfs; i++) { + emc->dvfs[i].rate =3D response.pairs[i].freq * 1000; + emc->dvfs[i].latency =3D response.pairs[i].latency; + + if (emc->dvfs[i].rate < emc->debugfs.min_rate) + emc->debugfs.min_rate =3D emc->dvfs[i].rate; + + if (emc->dvfs[i].rate > emc->debugfs.max_rate) + emc->debugfs.max_rate =3D emc->dvfs[i].rate; + + dev_dbg(emc->dev, " %2u: %lu Hz -> %lu us\n", i, + emc->dvfs[i].rate, emc->dvfs[i].latency); + } + + err =3D clk_set_rate_range(emc->clk, emc->debugfs.min_rate, emc->debugfs.= max_rate); + if (err < 0) { + dev_err(emc->dev, "failed to set rate range [%lu-%lu] for %pC\n", + emc->debugfs.min_rate, emc->debugfs.max_rate, emc->clk); + return err; + } + + emc->debugfs.root =3D debugfs_create_dir("emc", NULL); + debugfs_create_file("available_rates", S_IRUGO, emc->debugfs.root, + emc, &tegra186_emc_debug_available_rates_fops); + debugfs_create_file("min_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, + emc, &tegra186_emc_debug_min_rate_fops); + debugfs_create_file("max_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, + emc, &tegra186_emc_debug_max_rate_fops); + + return 0; +} + /* * tegra_emc_icc_set_bw() - Set BW api for EMC provider * @src: ICC node for External Memory Controller (EMC) @@ -251,10 +318,7 @@ static int tegra_emc_interconnect_init(struct tegra186= _emc *emc) static int tegra186_emc_probe(struct platform_device *pdev) { struct tegra_mc *mc =3D dev_get_drvdata(pdev->dev.parent); - struct mrq_emc_dvfs_latency_response response; - struct tegra_bpmp_message msg; struct tegra186_emc *emc; - unsigned int i; int err; =20 emc =3D devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); @@ -275,70 +339,12 @@ static int tegra186_emc_probe(struct platform_device = *pdev) platform_set_drvdata(pdev, emc); emc->dev =3D &pdev->dev; =20 - memset(&msg, 0, sizeof(msg)); - msg.mrq =3D MRQ_EMC_DVFS_LATENCY; - msg.tx.data =3D NULL; - msg.tx.size =3D 0; - msg.rx.data =3D &response; - msg.rx.size =3D sizeof(response); - - err =3D tegra_bpmp_transfer(emc->bpmp, &msg); - if (err < 0) { - dev_err(&pdev->dev, "failed to EMC DVFS pairs: %d\n", err); - goto put_bpmp; - } - if (msg.rx.ret < 0) { - err =3D -EINVAL; - dev_err(&pdev->dev, "EMC DVFS MRQ failed: %d (BPMP error code)\n", msg.r= x.ret); - goto put_bpmp; - } - - emc->debugfs.min_rate =3D ULONG_MAX; - emc->debugfs.max_rate =3D 0; - - emc->num_dvfs =3D response.num_pairs; - - emc->dvfs =3D devm_kmalloc_array(&pdev->dev, emc->num_dvfs, - sizeof(*emc->dvfs), GFP_KERNEL); - if (!emc->dvfs) { - err =3D -ENOMEM; - goto put_bpmp; - } - - dev_dbg(&pdev->dev, "%u DVFS pairs:\n", emc->num_dvfs); - - for (i =3D 0; i < emc->num_dvfs; i++) { - emc->dvfs[i].rate =3D response.pairs[i].freq * 1000; - emc->dvfs[i].latency =3D response.pairs[i].latency; - - if (emc->dvfs[i].rate < emc->debugfs.min_rate) - emc->debugfs.min_rate =3D emc->dvfs[i].rate; - - if (emc->dvfs[i].rate > emc->debugfs.max_rate) - emc->debugfs.max_rate =3D emc->dvfs[i].rate; - - dev_dbg(&pdev->dev, " %2u: %lu Hz -> %lu us\n", i, - emc->dvfs[i].rate, emc->dvfs[i].latency); - } - - err =3D clk_set_rate_range(emc->clk, emc->debugfs.min_rate, - emc->debugfs.max_rate); - if (err < 0) { - dev_err(&pdev->dev, - "failed to set rate range [%lu-%lu] for %pC\n", - emc->debugfs.min_rate, emc->debugfs.max_rate, - emc->clk); - goto put_bpmp; + if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_EMC_DVFS_LATENCY)) { + err =3D tegra186_emc_get_emc_dvfs_latency(emc); + if (err) + goto put_bpmp; } =20 - emc->debugfs.root =3D debugfs_create_dir("emc", NULL); - debugfs_create_file("available_rates", S_IRUGO, emc->debugfs.root, - emc, &tegra186_emc_debug_available_rates_fops); - debugfs_create_file("min_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, - emc, &tegra186_emc_debug_min_rate_fops); - debugfs_create_file("max_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, - emc, &tegra186_emc_debug_max_rate_fops); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 13:44:25.8393 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 96bcc264-de77-4a49-6955-08db725da0e0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00026367.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6174 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Return zero from icc_set_bw() to MC client driver if MRQ_BWMGR_INT is not supported by the BPMP-FW. Currently, 'EINVAL' is returned which causes error message in client drivers even when the platform doesn't support scaling. Signed-off-by: Sumit Gupta Acked-by: Thierry Reding --- drivers/memory/tegra/tegra234.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra23= 4.c index bc73be7fe143..07aba301a173 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -951,7 +951,7 @@ static int tegra234_mc_icc_set(struct icc_node *src, st= ruct icc_node *dst) return 0; =20 if (!mc->bwmgr_mrq_supported) - return -EINVAL; + return 0; =20 if (!mc->bpmp) { dev_err(mc->dev, "BPMP reference NULL\n"); @@ -998,7 +998,7 @@ static int tegra234_mc_icc_aggregate(struct icc_node *n= ode, u32 tag, u32 avg_bw, struct tegra_mc *mc =3D icc_provider_to_tegra_mc(p); =20 if (!mc->bwmgr_mrq_supported) - return -EINVAL; + return 0; =20 if (node->id =3D=3D TEGRA_ICC_MC_CPU_CLUSTER0 || node->id =3D=3D TEGRA_ICC_MC_CPU_CLUSTER1 || --=20 2.17.1