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Wed, 21 Jun 2023 06:35:33 -0700 From: Sumit Gupta To: , , , , CC: , , Subject: [Patch 1/4] memory: tegra: sort tegra234_mc_clients table as per register offsets Date: Wed, 21 Jun 2023 19:05:24 +0530 Message-ID: <20230621133526.22492-2-sumitg@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230621133526.22492-1-sumitg@nvidia.com> References: <20230621133526.22492-1-sumitg@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AA:EE_|MW4PR12MB7333:EE_ X-MS-Office365-Filtering-Correlation-Id: 2c37faa4-952b-4d7b-89b1-08db725c6d7e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hSygYxAyd8Z2O2aZs8Ma0LBS0ffauV/tVl8ywvvY8CN+y8INRB2RuybI3h683g3zdIX8j+GxZkD+8DqN0W23rXm+Dmry/mDXqPThs63dHUK+2D8cqOJCDCB8OrF8tqThJzIXRm67XwtHLiR/tQJN+vAvRnqVaA9f+0FjuG3xDa6bd1kCtweyMdqshL5cEZNUyNlv31+u9LyjPFTGg93OxXADWLDMkkuMDMDkod2BL6VVRrRhltUEPzF3EZGYdZm/9bVEVD0cfaJV4dhYjrOLohVXii7AvnW7R4q9gTgxiLo/L1C1PGdibsz/z/N5nas0SvR8bpq1HBTwDuEikCAiRka8Ibole5GlhgpkjyLvIOsN9il40sKMXn5mV9veJxdrlCeV5vzHk+Ln9AMhLxxXfih71SqSnksMGHmLEimfSMB1FYSJzDrgF1yln7ra6OWmbAVK35kwVrkx2g17BRC90xtVRbpKR/TLjcFImxly3a+znUQ2bsQ7gv+xtxf7vKwLQ77HnrX61YtkIIIIQpk975LoEr1ipuAORzXv6UXO9Z1YcW8cAFozX9QN9X6xQuBhVGHYO1dS7YGPEbLQdJj2IBlUq0YChEau0zBwdDQQt8jlysodjCZIgmxdklsZBCg4j/V7q/sBB/ra4lyLkPNMAwDTXufChnmfta+AmFnVVT8tA6xC6smBn3X5TGX+QW22uvcPnR0EqnOaduoJJA2TIVNT7abWpxQhkK0KGwdC75dgMUMWnZdqPsCfq9z84Eux X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230028)(4636009)(136003)(376002)(39860400002)(346002)(396003)(451199021)(36840700001)(46966006)(40470700004)(54906003)(110136005)(26005)(41300700001)(1076003)(186003)(7696005)(6666004)(478600001)(70586007)(70206006)(40460700003)(4326008)(316002)(40480700001)(36756003)(336012)(5660300002)(8936002)(36860700001)(107886003)(8676002)(47076005)(2616005)(2906002)(86362001)(82310400005)(83380400001)(30864003)(356005)(7636003)(82740400003)(426003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 13:35:50.1061 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2c37faa4-952b-4d7b-89b1-08db725c6d7e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7333 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Sort the MC client entries in "tegra234_mc_clients" table as per the override and security register offsets. This will help to avoid creating duplicate entries. Signed-off-by: Sumit Gupta --- drivers/memory/tegra/tegra234.c | 514 ++++++++++++++++---------------- 1 file changed, 259 insertions(+), 255 deletions(-) diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra23= 4.c index 8e873a7bc34f..3e44efe4541e 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -12,6 +12,10 @@ #include #include "mc.h" =20 +/* + * MC Client entries are sorted in the increasing order of the + * override and security register offsets. + */ static const struct tegra_mc_client tegra234_mc_clients[] =3D { { .id =3D TEGRA234_MEMORY_CLIENT_HDAR, @@ -25,6 +29,106 @@ static const struct tegra_mc_client tegra234_mc_clients= [] =3D { .security =3D 0xac, }, }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE6AR, + .name =3D "pcie6ar", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_6, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_PCIE6, + .regs =3D { + .sid =3D { + .override =3D 0x140, + .security =3D 0x144, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE6AW, + .name =3D "pcie6aw", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_6, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_PCIE6, + .regs =3D { + .sid =3D { + .override =3D 0x148, + .security =3D 0x14c, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE7AR, + .name =3D "pcie7ar", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_7, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_PCIE7, + .regs =3D { + .sid =3D { + .override =3D 0x150, + .security =3D 0x154, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_DLA0RDB, + .name =3D "dla0rdb", + .sid =3D TEGRA234_SID_NVDLA0, + .regs =3D { + .sid =3D { + .override =3D 0x160, + .security =3D 0x164, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_DLA0RDB1, + .name =3D "dla0rdb1", + .sid =3D TEGRA234_SID_NVDLA0, + .regs =3D { + .sid =3D { + .override =3D 0x168, + .security =3D 0x16c, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_DLA0WRB, + .name =3D "dla0wrb", + .sid =3D TEGRA234_SID_NVDLA0, + .regs =3D { + .sid =3D { + .override =3D 0x170, + .security =3D 0x174, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_DLA1RDB, + .name =3D "dla0rdb", + .sid =3D TEGRA234_SID_NVDLA1, + .regs =3D { + .sid =3D { + .override =3D 0x178, + .security =3D 0x17c, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE7AW, + .name =3D "pcie7aw", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_7, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_PCIE7, + .regs =3D { + .sid =3D { + .override =3D 0x180, + .security =3D 0x184, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE8AR, + .name =3D "pcie8ar", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_8, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_PCIE8, + .regs =3D { + .sid =3D { + .override =3D 0x190, + .security =3D 0x194, + }, + }, }, { .id =3D TEGRA234_MEMORY_CLIENT_HDAW, .name =3D "hdaw", @@ -37,6 +141,102 @@ static const struct tegra_mc_client tegra234_mc_client= s[] =3D { .security =3D 0x1ac, }, }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE8AW, + .name =3D "pcie8aw", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_8, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_PCIE8, + .regs =3D { + .sid =3D { + .override =3D 0x1d8, + .security =3D 0x1dc, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE9AR, + .name =3D "pcie9ar", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_9, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_PCIE9, + .regs =3D { + .sid =3D { + .override =3D 0x1e0, + .security =3D 0x1e4, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE6AR1, + .name =3D "pcie6ar1", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_6, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_PCIE6, + .regs =3D { + .sid =3D { + .override =3D 0x1e8, + .security =3D 0x1ec, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE9AW, + .name =3D "pcie9aw", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_9, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_PCIE9, + .regs =3D { + .sid =3D { + .override =3D 0x1f0, + .security =3D 0x1f4, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE10AR, + .name =3D "pcie10ar", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_10, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_PCIE10, + .regs =3D { + .sid =3D { + .override =3D 0x1f8, + .security =3D 0x1fc, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE10AW, + .name =3D "pcie10aw", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_10, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_PCIE10, + .regs =3D { + .sid =3D { + .override =3D 0x200, + .security =3D 0x204, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE10AR1, + .name =3D "pcie10ar1", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_10, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_PCIE10, + .regs =3D { + .sid =3D { + .override =3D 0x240, + .security =3D 0x244, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE7AR1, + .name =3D "pcie7ar1", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_7, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA234_SID_PCIE7, + .regs =3D { + .sid =3D { + .override =3D 0x248, + .security =3D 0x24c, + }, + }, }, { .id =3D TEGRA234_MEMORY_CLIENT_MGBEARD, .name =3D "mgbeard", @@ -157,6 +357,26 @@ static const struct tegra_mc_client tegra234_mc_client= s[] =3D { .security =3D 0x33c, }, }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_DLA1RDB1, + .name =3D "dla0rdb1", + .sid =3D TEGRA234_SID_NVDLA1, + .regs =3D { + .sid =3D { + .override =3D 0x370, + .security =3D 0x374, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_DLA1WRB, + .name =3D "dla0wrb", + .sid =3D TEGRA234_SID_NVDLA1, + .regs =3D { + .sid =3D { + .override =3D 0x378, + .security =3D 0x37c, + }, + }, }, { .id =3D TEGRA234_MEMORY_CLIENT_VI2W, .name =3D "vi2w", @@ -181,18 +401,6 @@ static const struct tegra_mc_client tegra234_mc_client= s[] =3D { .security =3D 0x38c, }, }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_VI2FALW, - .name =3D "vi2falw", - .bpmp_id =3D TEGRA_ICC_BPMP_VI2FAL, - .type =3D TEGRA_ICC_ISO_VIFAL, - .sid =3D TEGRA234_SID_ISO_VI2FALC, - .regs =3D { - .sid =3D { - .override =3D 0x3e0, - .security =3D 0x3e4, - }, - }, }, { .id =3D TEGRA234_MEMORY_CLIENT_APER, .name =3D "aper", @@ -218,27 +426,27 @@ static const struct tegra_mc_client tegra234_mc_clien= ts[] =3D { }, }, }, { - .id =3D TEGRA234_MEMORY_CLIENT_NVDISPLAYR, - .name =3D "nvdisplayr", - .bpmp_id =3D TEGRA_ICC_BPMP_DISPLAY, - .type =3D TEGRA_ICC_ISO_DISPLAY, - .sid =3D TEGRA234_SID_ISO_NVDISPLAY, + .id =3D TEGRA234_MEMORY_CLIENT_VI2FALW, + .name =3D "vi2falw", + .bpmp_id =3D TEGRA_ICC_BPMP_VI2FAL, + .type =3D TEGRA_ICC_ISO_VIFAL, + .sid =3D TEGRA234_SID_ISO_VI2FALC, .regs =3D { .sid =3D { - .override =3D 0x490, - .security =3D 0x494, + .override =3D 0x3e0, + .security =3D 0x3e4, }, }, }, { - .id =3D TEGRA234_MEMORY_CLIENT_NVDISPLAYR1, - .name =3D "nvdisplayr1", + .id =3D TEGRA234_MEMORY_CLIENT_NVDISPLAYR, + .name =3D "nvdisplayr", .bpmp_id =3D TEGRA_ICC_BPMP_DISPLAY, .type =3D TEGRA_ICC_ISO_DISPLAY, .sid =3D TEGRA234_SID_ISO_NVDISPLAY, .regs =3D { .sid =3D { - .override =3D 0x508, - .security =3D 0x50c, + .override =3D 0x490, + .security =3D 0x494, }, }, }, { @@ -305,6 +513,18 @@ static const struct tegra_mc_client tegra234_mc_client= s[] =3D { .security =3D 0x504, }, }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_NVDISPLAYR1, + .name =3D "nvdisplayr1", + .bpmp_id =3D TEGRA_ICC_BPMP_DISPLAY, + .type =3D TEGRA_ICC_ISO_DISPLAY, + .sid =3D TEGRA234_SID_ISO_NVDISPLAY, + .regs =3D { + .sid =3D { + .override =3D 0x508, + .security =3D 0x50c, + }, + }, }, { .id =3D TEGRA234_MEMORY_CLIENT_DLA0RDA, .name =3D "dla0rda", @@ -335,26 +555,6 @@ static const struct tegra_mc_client tegra234_mc_client= s[] =3D { .security =3D 0x604, }, }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_DLA0RDB, - .name =3D "dla0rdb", - .sid =3D TEGRA234_SID_NVDLA0, - .regs =3D { - .sid =3D { - .override =3D 0x160, - .security =3D 0x164, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_DLA0RDA1, - .name =3D "dla0rda1", - .sid =3D TEGRA234_SID_NVDLA0, - .regs =3D { - .sid =3D { - .override =3D 0x748, - .security =3D 0x74c, - }, - }, }, { .id =3D TEGRA234_MEMORY_CLIENT_DLA0FALWRB, .name =3D "dla0falwrb", @@ -365,26 +565,6 @@ static const struct tegra_mc_client tegra234_mc_client= s[] =3D { .security =3D 0x60c, }, }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_DLA0RDB1, - .name =3D "dla0rdb1", - .sid =3D TEGRA234_SID_NVDLA0, - .regs =3D { - .sid =3D { - .override =3D 0x168, - .security =3D 0x16c, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_DLA0WRB, - .name =3D "dla0wrb", - .sid =3D TEGRA234_SID_NVDLA0, - .regs =3D { - .sid =3D { - .override =3D 0x170, - .security =3D 0x174, - }, - }, }, { .id =3D TEGRA234_MEMORY_CLIENT_DLA1RDA, .name =3D "dla0rda", @@ -415,26 +595,6 @@ static const struct tegra_mc_client tegra234_mc_client= s[] =3D { .security =3D 0x624, }, }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_DLA1RDB, - .name =3D "dla0rdb", - .sid =3D TEGRA234_SID_NVDLA1, - .regs =3D { - .sid =3D { - .override =3D 0x178, - .security =3D 0x17c, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_DLA1RDA1, - .name =3D "dla0rda1", - .sid =3D TEGRA234_SID_NVDLA1, - .regs =3D { - .sid =3D { - .override =3D 0x750, - .security =3D 0x754, - }, - }, }, { .id =3D TEGRA234_MEMORY_CLIENT_DLA1FALWRB, .name =3D "dla0falwrb", @@ -445,26 +605,6 @@ static const struct tegra_mc_client tegra234_mc_client= s[] =3D { .security =3D 0x62c, }, }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_DLA1RDB1, - .name =3D "dla0rdb1", - .sid =3D TEGRA234_SID_NVDLA1, - .regs =3D { - .sid =3D { - .override =3D 0x370, - .security =3D 0x374, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_DLA1WRB, - .name =3D "dla0wrb", - .sid =3D TEGRA234_SID_NVDLA1, - .regs =3D { - .sid =3D { - .override =3D 0x378, - .security =3D 0x37c, - }, - }, }, { .id =3D TEGRA234_MEMORY_CLIENT_PCIE0R, .name =3D "pcie0r", @@ -610,171 +750,35 @@ static const struct tegra_mc_client tegra234_mc_clie= nts[] =3D { }, }, }, { - .id =3D TEGRA234_MEMORY_CLIENT_PCIE5R1, - .name =3D "pcie5r1", - .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_5, - .type =3D TEGRA_ICC_NISO, - .sid =3D TEGRA234_SID_PCIE5, - .regs =3D { - .sid =3D { - .override =3D 0x778, - .security =3D 0x77c, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_PCIE6AR, - .name =3D "pcie6ar", - .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_6, - .type =3D TEGRA_ICC_NISO, - .sid =3D TEGRA234_SID_PCIE6, - .regs =3D { - .sid =3D { - .override =3D 0x140, - .security =3D 0x144, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_PCIE6AW, - .name =3D "pcie6aw", - .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_6, - .type =3D TEGRA_ICC_NISO, - .sid =3D TEGRA234_SID_PCIE6, - .regs =3D { - .sid =3D { - .override =3D 0x148, - .security =3D 0x14c, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_PCIE6AR1, - .name =3D "pcie6ar1", - .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_6, - .type =3D TEGRA_ICC_NISO, - .sid =3D TEGRA234_SID_PCIE6, - .regs =3D { - .sid =3D { - .override =3D 0x1e8, - .security =3D 0x1ec, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_PCIE7AR, - .name =3D "pcie7ar", - .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_7, - .type =3D TEGRA_ICC_NISO, - .sid =3D TEGRA234_SID_PCIE7, - .regs =3D { - .sid =3D { - .override =3D 0x150, - .security =3D 0x154, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_PCIE7AW, - .name =3D "pcie7aw", - .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_7, - .type =3D TEGRA_ICC_NISO, - .sid =3D TEGRA234_SID_PCIE7, - .regs =3D { - .sid =3D { - .override =3D 0x180, - .security =3D 0x184, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_PCIE7AR1, - .name =3D "pcie7ar1", - .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_7, - .type =3D TEGRA_ICC_NISO, - .sid =3D TEGRA234_SID_PCIE7, - .regs =3D { - .sid =3D { - .override =3D 0x248, - .security =3D 0x24c, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_PCIE8AR, - .name =3D "pcie8ar", - .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_8, - .type =3D TEGRA_ICC_NISO, - .sid =3D TEGRA234_SID_PCIE8, - .regs =3D { - .sid =3D { - .override =3D 0x190, - .security =3D 0x194, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_PCIE8AW, - .name =3D "pcie8aw", - .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_8, - .type =3D TEGRA_ICC_NISO, - .sid =3D TEGRA234_SID_PCIE8, - .regs =3D { - .sid =3D { - .override =3D 0x1d8, - .security =3D 0x1dc, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_PCIE9AR, - .name =3D "pcie9ar", - .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_9, - .type =3D TEGRA_ICC_NISO, - .sid =3D TEGRA234_SID_PCIE9, - .regs =3D { - .sid =3D { - .override =3D 0x1e0, - .security =3D 0x1e4, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_PCIE9AW, - .name =3D "pcie9aw", - .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_9, - .type =3D TEGRA_ICC_NISO, - .sid =3D TEGRA234_SID_PCIE9, - .regs =3D { - .sid =3D { - .override =3D 0x1f0, - .security =3D 0x1f4, - }, - }, - }, { - .id =3D TEGRA234_MEMORY_CLIENT_PCIE10AR, - .name =3D "pcie10ar", - .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_10, - .type =3D TEGRA_ICC_NISO, - .sid =3D TEGRA234_SID_PCIE10, + .id =3D TEGRA234_MEMORY_CLIENT_DLA0RDA1, + .name =3D "dla0rda1", + .sid =3D TEGRA234_SID_NVDLA0, .regs =3D { .sid =3D { - .override =3D 0x1f8, - .security =3D 0x1fc, + .override =3D 0x748, + .security =3D 0x74c, }, }, }, { - .id =3D TEGRA234_MEMORY_CLIENT_PCIE10AW, - .name =3D "pcie10aw", - .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_10, - .type =3D TEGRA_ICC_NISO, - .sid =3D TEGRA234_SID_PCIE10, + .id =3D TEGRA234_MEMORY_CLIENT_DLA1RDA1, + .name =3D "dla0rda1", + .sid =3D TEGRA234_SID_NVDLA1, .regs =3D { .sid =3D { - .override =3D 0x200, - .security =3D 0x204, + .override =3D 0x750, + .security =3D 0x754, }, }, }, { - .id =3D TEGRA234_MEMORY_CLIENT_PCIE10AR1, - .name =3D "pcie10ar1", - .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_10, + .id =3D TEGRA234_MEMORY_CLIENT_PCIE5R1, + .name =3D "pcie5r1", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_5, .type =3D TEGRA_ICC_NISO, - .sid =3D TEGRA234_SID_PCIE10, + .sid =3D TEGRA234_SID_PCIE5, .regs =3D { .sid =3D { - .override =3D 0x240, - .security =3D 0x244, + .override =3D 0x778, + .security =3D 0x77c, }, }, }, { --=20 2.17.1