From nobody Mon Feb 9 14:03:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9194EEB64D7 for ; Wed, 21 Jun 2023 06:44:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231161AbjFUGoL (ORCPT ); Wed, 21 Jun 2023 02:44:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230489AbjFUGnn (ORCPT ); Wed, 21 Jun 2023 02:43:43 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA328198E for ; Tue, 20 Jun 2023 23:43:40 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-bd69bb4507eso6010283276.2 for ; Tue, 20 Jun 2023 23:43:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1687329820; x=1689921820; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=jzXQy+3gWCRrOq/bPJGSod35GlRHXYXuXCqPkpYte2c=; b=rvLyDf3473Ea5KgbE9MzK4m81ED5MczQdqagmULEilVLDvyqXUuA956dDqxQL8afkd I/KMEhrIM3w+cmdo4c6BxJzNUY5csQMLavWP2+i17nXGNqCj+ZP70yPu0bi+pTgs225a rAZ2HNjpybLfLtg0BQ98c3tHjAB9BijbI8q7UEO3+8148457WZur9CdIO5YNp4lm+Vdl Rq0CSZOcZtZN/6WN2azDEvWHFdlHaHUH9P77mTDTDjJVMQbgx5Uae087uO5s5uldv2nM l7OWmzWlWv7Q89Y0t3V/kW5ayh5OzqWwRmyT8IrUe+tNL09iKKoA09VyeydJpGmNpmxs Pbww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687329820; x=1689921820; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=jzXQy+3gWCRrOq/bPJGSod35GlRHXYXuXCqPkpYte2c=; b=llm04Lonz2x7I5/uzi1EAewIWMJNz0FGpSBjP6HrcDTy0n/mP2Fa1kMdIaZe5726Xi jvMslTBBesh3SzGImpvmnd3jf19ya6wQJypPL9x0XGlf9VpxIFDhvbBroxQnxw25KrTU kgoM8ko1mxtAjioj2DttGhgo2oPKVkmQc2KAeMIrqxKRzvnTK5l6f8jS1bLBLTUB2moG J006xuaGmK31VuQ1tbNm5YPKbMHVcJDDuNpwsaJGl9C1QJweEex0N6FWxomPhmLmZMAi KMGX02Jp98nYg6ZXmmqK3rszrKJYQAMKGQZHU8LIX8dmrubbSoDCP0M36tK8dPzDFDnP jlsQ== X-Gm-Message-State: AC+VfDxjKbRGTpESdtJitsCsvxYwBmeGjYNMuI8/k1+K6LXGlt/BLLX8 Idgg463w5xnZEoyQSbFN28ED+9pKkE37 X-Google-Smtp-Source: ACHHUZ6o7pYjIQ5aJehf2aHfK+lSFLWTkcaxHxTVWaWUeBs4KhACfgfWfn/usRnAdFLLIcrDe6s0cY2LaPQS X-Received: from mshavit.ntc.corp.google.com ([2401:fa00:95:20c:384f:f7da:c61d:5a3e]) (user=mshavit job=sendgmr) by 2002:a05:6902:15c4:b0:be4:d646:48d8 with SMTP id l4-20020a05690215c400b00be4d64648d8mr1659256ybu.8.1687329820101; Tue, 20 Jun 2023 23:43:40 -0700 (PDT) Date: Wed, 21 Jun 2023 14:37:15 +0800 In-Reply-To: <20230621063825.268890-1-mshavit@google.com> Mime-Version: 1.0 References: <20230621063825.268890-1-mshavit@google.com> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog Message-ID: <20230621063825.268890-4-mshavit@google.com> Subject: [PATCH v4 03/13] iommu/arm-smmu-v3: Refactor write_strtab_ent From: Michael Shavit To: Will Deacon , Robin Murphy , Joerg Roedel Cc: Michael Shavit , jean-philippe@linaro.org, nicolinc@nvidia.com, jgg@nvidia.com, baolu.lu@linux.intel.com, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Explicity keep track of the s1_cfg and s2_cfg that are attached to a master in arm_smmu_master, regardless of whether they are owned by arm_smmu_master, arm_smmu_domain or userspace. Signed-off-by: Michael Shavit --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 37 +++++++++------------ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 ++ 2 files changed, 17 insertions(+), 22 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 023769f5ca79a..d79c6ef5d6ed4 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1269,10 +1269,9 @@ static void arm_smmu_write_strtab_ent(struct arm_smm= u_master *master, u32 sid, */ u64 val =3D le64_to_cpu(dst[0]); bool ste_live =3D false; - struct arm_smmu_device *smmu =3D NULL; + struct arm_smmu_device *smmu =3D master->smmu; struct arm_smmu_s1_cfg *s1_cfg =3D NULL; struct arm_smmu_s2_cfg *s2_cfg =3D NULL; - struct arm_smmu_domain *smmu_domain =3D NULL; struct arm_smmu_cmdq_ent prefetch_cmd =3D { .opcode =3D CMDQ_OP_PREFETCH_CFG, .prefetch =3D { @@ -1280,24 +1279,10 @@ static void arm_smmu_write_strtab_ent(struct arm_sm= mu_master *master, u32 sid, }, }; =20 - if (master) { - smmu_domain =3D master->domain; - smmu =3D master->smmu; - } - - if (smmu_domain) { - switch (smmu_domain->stage) { - case ARM_SMMU_DOMAIN_S1: - s1_cfg =3D &smmu_domain->s1_cfg; - break; - case ARM_SMMU_DOMAIN_S2: - case ARM_SMMU_DOMAIN_NESTED: - s2_cfg =3D &smmu_domain->s2_cfg; - break; - default: - break; - } - } + if (master->s1_cfg) + s1_cfg =3D master->s1_cfg; + else if (master->s2_cfg) + s2_cfg =3D master->s2_cfg; =20 if (val & STRTAB_STE_0_V) { switch (FIELD_GET(STRTAB_STE_0_CFG, val)) { @@ -1319,8 +1304,8 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu= _master *master, u32 sid, val =3D STRTAB_STE_0_V; =20 /* Bypass/fault */ - if (!smmu_domain || !(s1_cfg || s2_cfg)) { - if (!smmu_domain && disable_bypass) + if (!(s1_cfg || s2_cfg)) { + if (disable_bypass) val |=3D FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT); else val |=3D FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS); @@ -2401,6 +2386,8 @@ static void arm_smmu_detach_dev(struct arm_smmu_maste= r *master) =20 master->domain =3D NULL; master->ats_enabled =3D false; + master->s1_cfg =3D NULL; + master->s2_cfg =3D NULL; arm_smmu_install_ste_for_dev(master); } =20 @@ -2454,6 +2441,12 @@ static int arm_smmu_attach_dev(struct iommu_domain *= domain, struct device *dev) } =20 master->domain =3D smmu_domain; + if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { + master->s1_cfg =3D &smmu_domain->s1_cfg; + } else if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S2 || + smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_NESTED) { + master->s2_cfg =3D &smmu_domain->s2_cfg; + } =20 /* * The SMMU does not support enabling ATS with bypass. When the STE is diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 053cc14c23969..3c614fbe2b8b9 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -689,6 +689,8 @@ struct arm_smmu_master { struct list_head domain_head; struct arm_smmu_stream *streams; struct arm_smmu_s1_cfg owned_s1_cfg; + struct arm_smmu_s1_cfg *s1_cfg; + struct arm_smmu_s2_cfg *s2_cfg; unsigned int num_streams; bool ats_enabled; bool stall_enabled; --=20 2.41.0.162.gfafddb0af9-goog