From nobody Mon Feb 9 15:09:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6AC93EB64D8 for ; Wed, 21 Jun 2023 06:44:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231137AbjFUGoG (ORCPT ); Wed, 21 Jun 2023 02:44:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230013AbjFUGni (ORCPT ); Wed, 21 Jun 2023 02:43:38 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA09B1709 for ; Tue, 20 Jun 2023 23:43:32 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-56cf9a86277so64701257b3.3 for ; Tue, 20 Jun 2023 23:43:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1687329812; x=1689921812; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=9vic1ayWBGr79y9f6y1FKqdm9/OskuVUCQ3Tr10KopQ=; b=RHaZJpocBAQex9N5sK+TVgzUKOuPn86MHuZT6EA4DsHyu3bgrSiJ/6leoQ9tr/MTNx fVcPxmgqsOc7bhA2bsToHFQk+6KAT5J8fjFvvBWV+GJ4hDTWKk5sDKZrS6MdI7si7KLi U0w462zitIRC0tsUnPZ2VYTHS65xaYWpUBs3saGloaPiHLGGDwtc031gios/uY13QTlj SLI28LI7OgWZJ/KaLkGSiBakAq8YtZIW1WVFV/BHehBRDjzQk0BaP4UntwQQWNb9F+I3 WNjFWpxs2VsOOSkh253vfrsykGVgRTXkImRD20J3FM6r7C4ZtfnPpiaPfw4QU//NgebR VONQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687329812; x=1689921812; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=9vic1ayWBGr79y9f6y1FKqdm9/OskuVUCQ3Tr10KopQ=; b=iry8OVdYcROmVOCX1TzbhtUzbOFGG2sqXhMcvwSC00foUcgZsEqy8Vk8tsofkgIrY+ zP8WBX+yMLywhMASZKFI6eQYzqzTVVyLMISMYmqC38NWFdYj4akEsVJdBON4Pet811Xi wovbksTsJ36z7Df+GWbdWApsh4cCveL0lJrIEyXE7YsqHoPBks9rw+vk7FnKTibmjzBT VTD2XhthnH263VivTiEqS59D27QXdJZHR16EaUoahnBDV//f81/Qq+ePMqYZrGZhW7wD Bc0dBRPcFRSD4USZpv0/9gtxUjGdDcuipjftDwonU3r0JHIHPoVNVngpPv0kauh7HLnJ joqQ== X-Gm-Message-State: AC+VfDwYf0+wfwVPAoJjpoyU74cPkOm7D/L2hmJ6FC7tWLQ1rZnaXUVj okpzMcVbcMaVexx+UA48m6OIl1xIVaoE X-Google-Smtp-Source: ACHHUZ4TXGK0i+D7h+9Nd4z8i5gJT8bGw52lE7GnL9ZKETGpo9OOKiKvObn0KiD3N3+R9rM2oZ7yQsyYMx8u X-Received: from mshavit.ntc.corp.google.com ([2401:fa00:95:20c:384f:f7da:c61d:5a3e]) (user=mshavit job=sendgmr) by 2002:a25:c514:0:b0:ba8:b828:c8ff with SMTP id v20-20020a25c514000000b00ba8b828c8ffmr1585519ybe.10.1687329812105; Tue, 20 Jun 2023 23:43:32 -0700 (PDT) Date: Wed, 21 Jun 2023 14:37:14 +0800 In-Reply-To: <20230621063825.268890-1-mshavit@google.com> Mime-Version: 1.0 References: <20230621063825.268890-1-mshavit@google.com> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog Message-ID: <20230621063825.268890-3-mshavit@google.com> Subject: [PATCH v4 02/13] iommu/arm-smmu-v3: Add smmu_s1_cfg to smmu_master From: Michael Shavit To: Will Deacon , Robin Murphy , Joerg Roedel Cc: Michael Shavit , jean-philippe@linaro.org, nicolinc@nvidia.com, jgg@nvidia.com, baolu.lu@linux.intel.com, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Except for Nested domains, arm_smmu_master will own the STEs that are inserted into the arm_smmu_device's STE table. Signed-off-by: Michael Shavit --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 28 +++++++++++++-------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + 2 files changed, 18 insertions(+), 11 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index beff04b897718..023769f5ca79a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1126,15 +1126,16 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_domain = *smmu_domain, int ssid, return 0; } =20 -static int arm_smmu_alloc_cd_tables(struct arm_smmu_domain *smmu_domain) +static int arm_smmu_init_s1_cfg(struct arm_smmu_master *master, + struct arm_smmu_s1_cfg *cfg) { int ret; size_t l1size; size_t max_contexts; - struct arm_smmu_device *smmu =3D smmu_domain->smmu; - struct arm_smmu_s1_cfg *cfg =3D &smmu_domain->s1_cfg; + struct arm_smmu_device *smmu =3D master->smmu; struct arm_smmu_ctx_desc_cfg *cdcfg =3D &cfg->cdcfg; =20 + cfg->s1cdmax =3D master->ssid_bits; max_contexts =3D 1 << cfg->s1cdmax; =20 if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB) || @@ -1175,12 +1176,11 @@ static int arm_smmu_alloc_cd_tables(struct arm_smmu= _domain *smmu_domain) return ret; } =20 -static void arm_smmu_free_cd_tables(struct arm_smmu_domain *smmu_domain) +static void arm_smmu_free_cd_tables(struct arm_smmu_device *smmu, + struct arm_smmu_ctx_desc_cfg *cdcfg) { int i; size_t size, l1size; - struct arm_smmu_device *smmu =3D smmu_domain->smmu; - struct arm_smmu_ctx_desc_cfg *cdcfg =3D &smmu_domain->s1_cfg.cdcfg; =20 if (cdcfg->l1_desc) { size =3D CTXDESC_L2_ENTRIES * (CTXDESC_CD_DWORDS << 3); @@ -2076,7 +2076,7 @@ static void arm_smmu_domain_free(struct iommu_domain = *domain) /* Prevent SVA from touching the CD while we're freeing it */ mutex_lock(&arm_smmu_asid_lock); if (cfg->cdcfg.cdtab) - arm_smmu_free_cd_tables(smmu_domain); + arm_smmu_free_cd_tables(smmu, &cfg->cdcfg); arm_smmu_free_asid(&smmu_domain->cd); mutex_unlock(&arm_smmu_asid_lock); } else { @@ -2108,11 +2108,9 @@ static int arm_smmu_domain_finalise_s1(struct arm_sm= mu_domain *smmu_domain, if (ret) goto out_unlock; =20 - cfg->s1cdmax =3D master->ssid_bits; - smmu_domain->stall_enabled =3D master->stall_enabled; =20 - ret =3D arm_smmu_alloc_cd_tables(smmu_domain); + ret =3D arm_smmu_init_s1_cfg(master, cfg); if (ret) goto out_free_asid; =20 @@ -2140,7 +2138,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_smm= u_domain *smmu_domain, return 0; =20 out_free_cd_tables: - arm_smmu_free_cd_tables(smmu_domain); + arm_smmu_free_cd_tables(smmu, &cfg->cdcfg); out_free_asid: arm_smmu_free_asid(cd); out_unlock: @@ -2704,6 +2702,13 @@ static struct iommu_device *arm_smmu_probe_device(st= ruct device *dev) smmu->features & ARM_SMMU_FEAT_STALL_FORCE) master->stall_enabled =3D true; =20 + ret =3D arm_smmu_init_s1_cfg(master, &master->owned_s1_cfg); + if (ret) { + arm_smmu_disable_pasid(master); + arm_smmu_remove_master(master); + goto err_free_master; + } + return &smmu->iommu; =20 err_free_master: @@ -2719,6 +2724,7 @@ static void arm_smmu_release_device(struct device *de= v) if (WARN_ON(arm_smmu_master_sva_enabled(master))) iopf_queue_remove_device(master->smmu->evtq.iopf, dev); arm_smmu_detach_dev(master); + arm_smmu_free_cd_tables(master->smmu, &master->owned_s1_cfg.cdcfg); arm_smmu_disable_pasid(master); arm_smmu_remove_master(master); kfree(master); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 68d519f21dbd8..053cc14c23969 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -688,6 +688,7 @@ struct arm_smmu_master { struct arm_smmu_domain *domain; struct list_head domain_head; struct arm_smmu_stream *streams; + struct arm_smmu_s1_cfg owned_s1_cfg; unsigned int num_streams; bool ats_enabled; bool stall_enabled; --=20 2.41.0.162.gfafddb0af9-goog