From nobody Thu Nov 14 17:33:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 138F4EB64D7 for ; Wed, 21 Jun 2023 03:20:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230218AbjFUDUi (ORCPT ); Tue, 20 Jun 2023 23:20:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230082AbjFUDTy (ORCPT ); Tue, 20 Jun 2023 23:19:54 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E54341739; Tue, 20 Jun 2023 20:19:50 -0700 (PDT) X-UUID: 76c28c1c0fe211ee9cb5633481061a41-20230621 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=3K4tEFJ0y9VbPt887jkZSqq8jz3bTbKpIp+i71YQQuQ=; b=dmaik9vCd7mqQgh3muqwkn1D5tLzUMxw48nMT/JPTo0g8OHEcoz3aQAkNGrFzy5pHu9ayrkEaVG7IQuKLVhnwhrii6EMSd+L8gbv/Vp141kL4fkCcd/zlT6FTQDv1A0vqgACLQT5iQVG0yIj0972bGJCuhG0nKIZHAmfRgjP4hI=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.27,REQID:28c5774b-1061-4dd6-a8c7-1f9f92181ff9,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:01c9525,CLOUDID:9b9cbb6f-2f20-4998-991c-3b78627e4938,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 76c28c1c0fe211ee9cb5633481061a41-20230621 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1167508213; Wed, 21 Jun 2023 11:19:42 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 21 Jun 2023 11:19:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 21 Jun 2023 11:19:40 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel , Rob Herring CC: , , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Shawn Sung Subject: [PATCH v4 12/14] drm/mediatek: Improve compatibility of display driver Date: Wed, 21 Jun 2023 11:19:36 +0800 Message-ID: <20230621031938.5884-13-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230621031938.5884-1-shawn.sung@mediatek.com> References: <20230621031938.5884-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" - Add new functions to enable/disable components, and reuse them when clock enable/disable - Check if the component is defined before using it since some modules are MT8188 only (ex. PADDING) - Control components according to its type rather than ID - Use a for-loop to add/remove components in an arrays, so we can only maintain this array to make sure every component will be initialized properly Signed-off-by: Hsiao Chien Sung --- .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 186 +++++++++--------- 1 file changed, 96 insertions(+), 90 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index c0a38f5217ee..69ae531294ff 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -51,6 +51,7 @@ enum mtk_ovl_adaptor_comp_id { =20 struct ovl_adaptor_comp_match { enum mtk_ovl_adaptor_comp_type type; + enum mtk_ddp_comp_id comp_id; int alias_id; }; =20 @@ -67,21 +68,78 @@ static const char * const private_comp_stem[OVL_ADAPTOR= _TYPE_NUM] =3D { }; =20 static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX= ] =3D { - [OVL_ADAPTOR_MDP_RDMA0] =3D { OVL_ADAPTOR_TYPE_RDMA, 0 }, - [OVL_ADAPTOR_MDP_RDMA1] =3D { OVL_ADAPTOR_TYPE_RDMA, 1 }, - [OVL_ADAPTOR_MDP_RDMA2] =3D { OVL_ADAPTOR_TYPE_RDMA, 2 }, - [OVL_ADAPTOR_MDP_RDMA3] =3D { OVL_ADAPTOR_TYPE_RDMA, 3 }, - [OVL_ADAPTOR_MDP_RDMA4] =3D { OVL_ADAPTOR_TYPE_RDMA, 4 }, - [OVL_ADAPTOR_MDP_RDMA5] =3D { OVL_ADAPTOR_TYPE_RDMA, 5 }, - [OVL_ADAPTOR_MDP_RDMA6] =3D { OVL_ADAPTOR_TYPE_RDMA, 6 }, - [OVL_ADAPTOR_MDP_RDMA7] =3D { OVL_ADAPTOR_TYPE_RDMA, 7 }, - [OVL_ADAPTOR_MERGE0] =3D { OVL_ADAPTOR_TYPE_MERGE, 1 }, - [OVL_ADAPTOR_MERGE1] =3D { OVL_ADAPTOR_TYPE_MERGE, 2 }, - [OVL_ADAPTOR_MERGE2] =3D { OVL_ADAPTOR_TYPE_MERGE, 3 }, - [OVL_ADAPTOR_MERGE3] =3D { OVL_ADAPTOR_TYPE_MERGE, 4 }, - [OVL_ADAPTOR_ETHDR0] =3D { OVL_ADAPTOR_TYPE_ETHDR, 0 }, + [OVL_ADAPTOR_ETHDR0] =3D { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MI= XER, 0 }, + [OVL_ADAPTOR_MDP_RDMA0] =3D { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RD= MA0, 0 }, + [OVL_ADAPTOR_MDP_RDMA1] =3D { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RD= MA1, 1 }, + [OVL_ADAPTOR_MDP_RDMA2] =3D { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RD= MA2, 2 }, + [OVL_ADAPTOR_MDP_RDMA3] =3D { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RD= MA3, 3 }, + [OVL_ADAPTOR_MDP_RDMA4] =3D { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RD= MA4, 4 }, + [OVL_ADAPTOR_MDP_RDMA5] =3D { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RD= MA5, 5 }, + [OVL_ADAPTOR_MDP_RDMA6] =3D { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RD= MA6, 6 }, + [OVL_ADAPTOR_MDP_RDMA7] =3D { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RD= MA7, 7 }, + [OVL_ADAPTOR_MERGE0] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, = 1 }, + [OVL_ADAPTOR_MERGE1] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, = 2 }, + [OVL_ADAPTOR_MERGE2] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, = 3 }, + [OVL_ADAPTOR_MERGE3] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, = 4 }, }; =20 +static int mtk_ovl_adaptor_enable(struct device *dev, enum mtk_ovl_adaptor= _comp_type type) +{ + int ret =3D 0; + + if (!dev) + goto end; + + switch (type) { + case OVL_ADAPTOR_TYPE_ETHDR: + ret =3D mtk_ethdr_clk_enable(dev); + break; + case OVL_ADAPTOR_TYPE_MERGE: + ret =3D mtk_merge_clk_enable(dev); + break; + case OVL_ADAPTOR_TYPE_RDMA: + // only LARB users need to do this + ret =3D pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "Failed to enable power domain, error(%d)\n", ret); + goto end; + } + ret =3D mtk_mdp_rdma_clk_enable(dev); + if (ret) + pm_runtime_put(dev); + break; + default: + dev_err(dev, "Unknown type: %d\n", type); + } + + if (ret) + dev_err(dev, "Failed to enable clock: error(%d)\n", ret); + +end: + return ret; +} + +static void mtk_ovl_adaptor_disable(struct device *dev, enum mtk_ovl_adapt= or_comp_type type) +{ + if (!dev) + return; + + switch (type) { + case OVL_ADAPTOR_TYPE_ETHDR: + mtk_ethdr_clk_disable(dev); + break; + case OVL_ADAPTOR_TYPE_MERGE: + mtk_merge_clk_disable(dev); + break; + case OVL_ADAPTOR_TYPE_RDMA: + mtk_mdp_rdma_clk_disable(dev); + pm_runtime_put(dev); + break; + default: + dev_err(dev, "Unknown type: %d\n", type); + } +} + void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx, struct mtk_plane_state *state, struct cmdq_pkt *cmdq_pkt) @@ -186,72 +244,30 @@ void mtk_ovl_adaptor_stop(struct device *dev) int mtk_ovl_adaptor_clk_enable(struct device *dev) { struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); - struct device *comp; - int ret; + int ret =3D 0; int i; =20 - for (i =3D 0; i < OVL_ADAPTOR_MERGE0; i++) { - comp =3D ovl_adaptor->ovl_adaptor_comp[i]; - ret =3D pm_runtime_get_sync(comp); - if (ret < 0) { - dev_err(dev, "Failed to enable power domain %d, err %d\n", i, ret); - goto pwr_err; - } - } - for (i =3D 0; i < OVL_ADAPTOR_ID_MAX; i++) { - comp =3D ovl_adaptor->ovl_adaptor_comp[i]; - - if (i < OVL_ADAPTOR_MERGE0) - ret =3D mtk_mdp_rdma_clk_enable(comp); - else if (i < OVL_ADAPTOR_ETHDR0) - ret =3D mtk_merge_clk_enable(comp); - else - ret =3D mtk_ethdr_clk_enable(comp); + ret =3D mtk_ovl_adaptor_enable(ovl_adaptor->ovl_adaptor_comp[i], + comp_matches[i].type); if (ret) { - dev_err(dev, "Failed to enable clock %d, err %d\n", i, ret); - goto clk_err; + while (--i >=3D 0) + mtk_ovl_adaptor_disable(ovl_adaptor->ovl_adaptor_comp[i], + comp_matches[i].type); + break; } } - - return ret; - -clk_err: - while (--i >=3D 0) { - comp =3D ovl_adaptor->ovl_adaptor_comp[i]; - if (i < OVL_ADAPTOR_MERGE0) - mtk_mdp_rdma_clk_disable(comp); - else if (i < OVL_ADAPTOR_ETHDR0) - mtk_merge_clk_disable(comp); - else - mtk_ethdr_clk_disable(comp); - } - i =3D OVL_ADAPTOR_MERGE0; - -pwr_err: - while (--i >=3D 0) - pm_runtime_put(ovl_adaptor->ovl_adaptor_comp[i]); - return ret; } =20 void mtk_ovl_adaptor_clk_disable(struct device *dev) { struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); - struct device *comp; int i; =20 for (i =3D 0; i < OVL_ADAPTOR_ID_MAX; i++) { - comp =3D ovl_adaptor->ovl_adaptor_comp[i]; - - if (i < OVL_ADAPTOR_MERGE0) { - mtk_mdp_rdma_clk_disable(comp); - pm_runtime_put(comp); - } else if (i < OVL_ADAPTOR_ETHDR0) { - mtk_merge_clk_disable(comp); - } else { - mtk_ethdr_clk_disable(comp); - } + mtk_ovl_adaptor_disable(ovl_adaptor->ovl_adaptor_comp[i], + comp_matches[i].type); } } =20 @@ -313,36 +329,26 @@ size_t mtk_ovl_adaptor_get_num_formats(struct device = *dev) =20 void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex) { - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA0); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA1); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA2); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA3); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA4); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA5); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA6); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA7); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE1); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE2); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE3); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE4); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER); + struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); + int i; + + for (i =3D 0; i < OVL_ADAPTOR_ID_MAX; i++) { + if (!ovl_adaptor->ovl_adaptor_comp[i]) + continue; + mtk_mutex_add_comp(mutex, comp_matches[i].comp_id); + } } =20 void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mut= ex) { - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA0); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA1); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA2); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA3); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA4); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA5); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA6); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA7); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE1); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE2); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE3); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE4); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER); + struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); + int i; + + for (i =3D 0; i < OVL_ADAPTOR_ID_MAX; i++) { + if (!ovl_adaptor->ovl_adaptor_comp[i]) + continue; + mtk_mutex_remove_comp(mutex, comp_matches[i].comp_id); + } } =20 void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev,= unsigned int next) --=20 2.39.2