From nobody Thu Nov 14 17:17:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35296EB64DC for ; Wed, 21 Jun 2023 03:20:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230230AbjFUDUs (ORCPT ); Tue, 20 Jun 2023 23:20:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230087AbjFUDTy (ORCPT ); Tue, 20 Jun 2023 23:19:54 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E8B041982; Tue, 20 Jun 2023 20:19:51 -0700 (PDT) X-UUID: 765cd0de0fe211ee9cb5633481061a41-20230621 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Sh12eafoPPWkZNYzsIQFMoHqC8cfw09yFzJnHYKMalw=; b=SlhyaVVurMsN0NckQ3wz8z1QA0VQ+06idu5t2AJqsie8g0Pz3otiLM/3VKLKXJoaKyXeZR1ImnqBkv3/uqivaWxAHsmMyDRpzFpXyEUpO+occ6FF3ozCnf8QxhMwz+zQQ4AeFrIZkyolUME/gO+d1iASrUAgSbYm8bQUHu6J+Oc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.27,REQID:11ec56da-5f9e-4214-ad4d-f651ab215982,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:01c9525,CLOUDID:d415173f-de1e-4348-bc35-c96f92f1dcbb,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 765cd0de0fe211ee9cb5633481061a41-20230621 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 425437497; Wed, 21 Jun 2023 11:19:41 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 21 Jun 2023 11:19:40 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 21 Jun 2023 11:19:40 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel , Rob Herring CC: , , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Shawn Sung Subject: [PATCH v4 10/14] soc: mediatek: Add MT8188 VDOSYS reset bit map Date: Wed, 21 Jun 2023 11:19:34 +0800 Message-ID: <20230621031938.5884-11-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230621031938.5884-1-shawn.sung@mediatek.com> References: <20230621031938.5884-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add MT8188 reset bit map for VDOSYS0 and VDOSYS1. Signed-off-by: Hsiao Chien Sung Reviewed-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mt8188-mmsys.h | 84 +++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 7 ++- 2 files changed, 90 insertions(+), 1 deletion(-) diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8= 188-mmsys.h index a9490c3c4256..6bebf1a69fc0 100644 --- a/drivers/soc/mediatek/mt8188-mmsys.h +++ b/drivers/soc/mediatek/mt8188-mmsys.h @@ -3,6 +3,10 @@ #ifndef __SOC_MEDIATEK_MT8188_MMSYS_H #define __SOC_MEDIATEK_MT8188_MMSYS_H =20 +#include +#include + +#define MT8188_VDO0_SW0_RST_B 0x190 #define MT8188_VDO0_OVL_MOUT_EN 0xf14 #define MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0) #define MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1) @@ -67,6 +71,7 @@ #define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE BIT(18) #define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0 BIT(19) =20 +#define MT8188_VDO1_SW0_RST_B 0x1d0 #define MT8188_VDO1_HDR_TOP_CFG 0xd00 #define MT8188_VDO1_MIXER_IN1_ALPHA 0xd30 #define MT8188_VDO1_MIXER_IN1_PAD 0xd40 @@ -117,6 +122,85 @@ #define MT8188_VDO1_MIXER_SOUT_SEL_IN 0xf68 #define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0 =20 +static const u8 mmsys_mt8188_vdo0_rst_tb[] =3D { + [MT8188_VDO0_RST_DISP_OVL0] =3D MMSYS_RST_NR(0, 0), + [MT8188_VDO0_RST_FAKE_ENG0] =3D MMSYS_RST_NR(0, 2), + [MT8188_VDO0_RST_DISP_CCORR0] =3D MMSYS_RST_NR(0, 4), + [MT8188_VDO0_RST_DISP_MUTEX0] =3D MMSYS_RST_NR(0, 6), + [MT8188_VDO0_RST_DISP_GAMMA0] =3D MMSYS_RST_NR(0, 8), + [MT8188_VDO0_RST_DISP_DITHER0] =3D MMSYS_RST_NR(0, 10), + [MT8188_VDO0_RST_DISP_WDMA0] =3D MMSYS_RST_NR(0, 17), + [MT8188_VDO0_RST_DISP_RDMA0] =3D MMSYS_RST_NR(0, 19), + [MT8188_VDO0_RST_DSI0] =3D MMSYS_RST_NR(0, 21), + [MT8188_VDO0_RST_DSI1] =3D MMSYS_RST_NR(0, 22), + [MT8188_VDO0_RST_DSC_WRAP0] =3D MMSYS_RST_NR(0, 23), + [MT8188_VDO0_RST_VPP_MERGE0] =3D MMSYS_RST_NR(0, 24), + [MT8188_VDO0_RST_DP_INTF0] =3D MMSYS_RST_NR(0, 25), + [MT8188_VDO0_RST_DISP_AAL0] =3D MMSYS_RST_NR(0, 26), + [MT8188_VDO0_RST_INLINEROT0] =3D MMSYS_RST_NR(0, 27), + [MT8188_VDO0_RST_APB_BUS] =3D MMSYS_RST_NR(0, 28), + [MT8188_VDO0_RST_DISP_COLOR0] =3D MMSYS_RST_NR(0, 29), + [MT8188_VDO0_RST_MDP_WROT0] =3D MMSYS_RST_NR(0, 30), + [MT8188_VDO0_RST_DISP_RSZ0] =3D MMSYS_RST_NR(0, 31), +}; + +static const u8 mmsys_mt8188_vdo1_rst_tb[] =3D { + [MT8188_VDO1_RST_SMI_LARB2] =3D MMSYS_RST_NR(0, 0), + [MT8188_VDO1_RST_SMI_LARB3] =3D MMSYS_RST_NR(0, 1), + [MT8188_VDO1_RST_GALS] =3D MMSYS_RST_NR(0, 2), + [MT8188_VDO1_RST_FAKE_ENG0] =3D MMSYS_RST_NR(0, 3), + [MT8188_VDO1_RST_FAKE_ENG1] =3D MMSYS_RST_NR(0, 4), + [MT8188_VDO1_RST_MDP_RDMA0] =3D MMSYS_RST_NR(0, 5), + [MT8188_VDO1_RST_MDP_RDMA1] =3D MMSYS_RST_NR(0, 6), + [MT8188_VDO1_RST_MDP_RDMA2] =3D MMSYS_RST_NR(0, 7), + [MT8188_VDO1_RST_MDP_RDMA3] =3D MMSYS_RST_NR(0, 8), + [MT8188_VDO1_RST_VPP_MERGE0] =3D MMSYS_RST_NR(0, 9), + [MT8188_VDO1_RST_VPP_MERGE1] =3D MMSYS_RST_NR(0, 10), + [MT8188_VDO1_RST_VPP_MERGE2] =3D MMSYS_RST_NR(0, 11), + [MT8188_VDO1_RST_VPP_MERGE3] =3D MMSYS_RST_NR(1, 0), + [MT8188_VDO1_RST_VPP_MERGE4] =3D MMSYS_RST_NR(1, 1), + [MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC] =3D MMSYS_RST_NR(1, 2), + [MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC] =3D MMSYS_RST_NR(1, 3), + [MT8188_VDO1_RST_DISP_MUTEX] =3D MMSYS_RST_NR(1, 4), + [MT8188_VDO1_RST_MDP_RDMA4] =3D MMSYS_RST_NR(1, 5), + [MT8188_VDO1_RST_MDP_RDMA5] =3D MMSYS_RST_NR(1, 6), + [MT8188_VDO1_RST_MDP_RDMA6] =3D MMSYS_RST_NR(1, 7), + [MT8188_VDO1_RST_MDP_RDMA7] =3D MMSYS_RST_NR(1, 8), + [MT8188_VDO1_RST_DP_INTF1_MMCK] =3D MMSYS_RST_NR(1, 9), + [MT8188_VDO1_RST_DPI0_MM_CK] =3D MMSYS_RST_NR(1, 10), + [MT8188_VDO1_RST_DPI1_MM_CK] =3D MMSYS_RST_NR(1, 11), + [MT8188_VDO1_RST_MERGE0_DL_ASYNC] =3D MMSYS_RST_NR(1, 13), + [MT8188_VDO1_RST_MERGE1_DL_ASYNC] =3D MMSYS_RST_NR(1, 14), + [MT8188_VDO1_RST_MERGE2_DL_ASYNC] =3D MMSYS_RST_NR(1, 15), + [MT8188_VDO1_RST_MERGE3_DL_ASYNC] =3D MMSYS_RST_NR(1, 16), + [MT8188_VDO1_RST_MERGE4_DL_ASYNC] =3D MMSYS_RST_NR(1, 17), + [MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC] =3D MMSYS_RST_NR(1, 18), + [MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC] =3D MMSYS_RST_NR(1, 19), + [MT8188_VDO1_RST_PADDING0] =3D MMSYS_RST_NR(1, 20), + [MT8188_VDO1_RST_PADDING1] =3D MMSYS_RST_NR(1, 21), + [MT8188_VDO1_RST_PADDING2] =3D MMSYS_RST_NR(1, 22), + [MT8188_VDO1_RST_PADDING3] =3D MMSYS_RST_NR(1, 23), + [MT8188_VDO1_RST_PADDING4] =3D MMSYS_RST_NR(1, 24), + [MT8188_VDO1_RST_PADDING5] =3D MMSYS_RST_NR(1, 25), + [MT8188_VDO1_RST_PADDING6] =3D MMSYS_RST_NR(1, 26), + [MT8188_VDO1_RST_PADDING7] =3D MMSYS_RST_NR(1, 27), + [MT8188_VDO1_RST_DISP_RSZ0] =3D MMSYS_RST_NR(1, 28), + [MT8188_VDO1_RST_DISP_RSZ1] =3D MMSYS_RST_NR(1, 29), + [MT8188_VDO1_RST_DISP_RSZ2] =3D MMSYS_RST_NR(1, 30), + [MT8188_VDO1_RST_DISP_RSZ3] =3D MMSYS_RST_NR(1, 31), + [MT8188_VDO1_RST_HDR_VDO_FE0] =3D MMSYS_RST_NR(2, 0), + [MT8188_VDO1_RST_HDR_GFX_FE0] =3D MMSYS_RST_NR(2, 1), + [MT8188_VDO1_RST_HDR_VDO_BE] =3D MMSYS_RST_NR(2, 2), + [MT8188_VDO1_RST_HDR_VDO_FE1] =3D MMSYS_RST_NR(2, 16), + [MT8188_VDO1_RST_HDR_GFX_FE1] =3D MMSYS_RST_NR(2, 17), + [MT8188_VDO1_RST_DISP_MIXER] =3D MMSYS_RST_NR(2, 18), + [MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC] =3D MMSYS_RST_NR(2, 19), + [MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC] =3D MMSYS_RST_NR(2, 20), + [MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC] =3D MMSYS_RST_NR(2, 21), + [MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC] =3D MMSYS_RST_NR(2, 22), + [MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC] =3D MMSYS_RST_NR(2, 23), +}; + static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] =3D { { DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mm= sys.c index ace71cc714c4..04eccd8653db 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -87,6 +87,9 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_= driver_data =3D { .clk_driver =3D "clk-mt8188-vdo0", .routes =3D mmsys_mt8188_routing_table, .num_routes =3D ARRAY_SIZE(mmsys_mt8188_routing_table), + .sw0_rst_offset =3D MT8188_VDO0_SW0_RST_B, + .rst_tb =3D mmsys_mt8188_vdo0_rst_tb, + .num_resets =3D ARRAY_SIZE(mmsys_mt8188_vdo0_rst_tb), }; =20 =20 @@ -94,7 +97,9 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys1_= driver_data =3D { .clk_driver =3D "clk-mt8188-vdo1", .routes =3D mmsys_mt8188_vdo1_routing_table, .num_routes =3D ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table), - .num_resets =3D 96, + .sw0_rst_offset =3D MT8188_VDO1_SW0_RST_B, + .rst_tb =3D mmsys_mt8188_vdo1_rst_tb, + .num_resets =3D ARRAY_SIZE(mmsys_mt8188_vdo1_rst_tb), .vsync_len =3D 1, }; =20 --=20 2.39.2