From nobody Thu Nov 14 17:18:57 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72B1CEB64DC for ; Tue, 20 Jun 2023 12:20:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232611AbjFTMUS (ORCPT ); Tue, 20 Jun 2023 08:20:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232473AbjFTMUJ (ORCPT ); Tue, 20 Jun 2023 08:20:09 -0400 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BBD9810CF for ; Tue, 20 Jun 2023 05:20:07 -0700 (PDT) Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-3f9b23dc270so20836665e9.0 for ; Tue, 20 Jun 2023 05:20:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20221208.gappssmtp.com; s=20221208; t=1687263606; x=1689855606; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8BYbQnXe4htpj9TigSsM3351htH/uh9Sm3aVNnCROXw=; b=B32y/xwAVrgbYjg6vunSD62J6YM4agPJp5ei85PyumXObEqWm0lXmV5y6sdJUwoa01 CcHsB0Zi5Q++ENs+CK3hpQxIf0l1+OmsEuyt+9W3KUaH5Cr1b2Ha5RiTNCukya+U6aZz MDh80LOb0/xu3qK9CDn2JuQdE079U1Wcudo8TwLviuisTDlksHiaiEvPGohsksmlE44+ 7TvrRoTMrcMkHeDmHbf3F5VwcBx3LUwWhCTVF72E3Hk1arP/a/iMrkEz9YE7+HcC8jzB zChQ5FivLFmWlo866Bx14kyarvfOj3B+j6Eq7u/nDYygMXBriS0GBLKFpESst3kwPanY GH/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687263606; x=1689855606; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8BYbQnXe4htpj9TigSsM3351htH/uh9Sm3aVNnCROXw=; b=e3/g57t6df5EePGf0Hef4FKGBLsnUL8E+RR1dTfyb9LoSZouqUcmsEKNuEF+5Gtk0l ZIKmfaOzFjwhG09tTHewQOa4EOI5Ebl+MshTooC1dqpWvrrmxE/idKkZdC8CKhsRScUU ScD7v8b6P/XtzaRpuBudKjYWdxwcrAufBbV8IPgkotDTKWD9LKpC0MdvDS0qzJKzQ5u4 zsaeD1Z2Sq/XtpDM3N0qIw7wj8H1uCxVUtMS/u2POk2pMkqB2nwKlV0VB2pcFO9ZjOMs FhYz7VDiMbbpSctWwFyUwh5ck0K6WawdtOANupKIgNFlgZ7EKq4R7ri4OlvyerNyGzhS L42Q== X-Gm-Message-State: AC+VfDwL14uKScez0C1EJLTOABHtgpPBHzQblvbxWzUZ2yz7cpwuyCNj KWd+PAX9mJUWT6l66fG9AG9hGg== X-Google-Smtp-Source: ACHHUZ4aidN2IH9QVc7djX74bWEbv9o822J3PTVF4DZjfCvgh/OcwOUH7SKRjUpzItIbeSK5/NbWfA== X-Received: by 2002:a05:600c:22d8:b0:3f8:f884:ebec with SMTP id 24-20020a05600c22d800b003f8f884ebecmr9754504wmg.17.1687263606221; Tue, 20 Jun 2023 05:20:06 -0700 (PDT) Received: from localhost.localdomain ([2a01:e0a:55f:21e0:9e19:4376:dea6:dbfa]) by smtp.gmail.com with ESMTPSA id u15-20020a05600c210f00b003f18b942338sm2242513wml.3.2023.06.20.05.20.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jun 2023 05:20:05 -0700 (PDT) From: Julien Stephan Cc: pnguyen@baylibre.com, louis.kuo@mediatek.com, fsylvestre@baylibre.com, Julien Stephan , Andy Hsieh , AngeloGioacchino Del Regno , Chunfeng Yun , Chun-Kuang Hu , Conor Dooley , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, Kishon Vijay Abraham I , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Matthias Brugger , Philipp Zabel , Rob Herring , Vinod Koul Subject: [PATCH v4 2/2] phy: mtk-mipi-csi: add driver for CSI phy Date: Tue, 20 Jun 2023 14:18:47 +0200 Message-ID: <20230620121928.1231745-3-jstephan@baylibre.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230620121928.1231745-1-jstephan@baylibre.com> References: <20230620121928.1231745-1-jstephan@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Phi-bang Nguyen This is a new driver that supports the MIPI CSI CD-PHY version 0.5 The number of PHYs depend on the SoC. Each PHY can support D-PHY only or CD-PHY configuration. The driver supports only D-PHY mode, so CD-PHY compatible PHY are configured in D-PHY mode. Signed-off-by: Louis Kuo Signed-off-by: Phi-bang Nguyen [Julien Stephan: refactor code] [Julien Stephan: simplify driver model: one instance per phy vs one instance for all phys] Co-developed-by: Julien Stephan Signed-off-by: Julien Stephan --- MAINTAINERS | 1 + drivers/phy/mediatek/Kconfig | 12 + drivers/phy/mediatek/Makefile | 2 + .../mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h | 62 ++++ drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c | 343 ++++++++++++++++++ 5 files changed, 420 insertions(+) create mode 100644 drivers/phy/mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h create mode 100644 drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c diff --git a/MAINTAINERS b/MAINTAINERS index 024d67eb7a94..4d9b6c9f6662 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13189,6 +13189,7 @@ M: Julien Stephan M: Andy Hsieh S: Supported F: Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml +F: drivers/phy/mediatek/phy-mtk-mipi-csi-0-5* =20 MEDIATEK MMC/SD/SDIO DRIVER M: Chaotian Jing diff --git a/drivers/phy/mediatek/Kconfig b/drivers/phy/mediatek/Kconfig index 3125ecb5d119..7088382ebc9e 100644 --- a/drivers/phy/mediatek/Kconfig +++ b/drivers/phy/mediatek/Kconfig @@ -74,3 +74,15 @@ config PHY_MTK_DP select GENERIC_PHY help Support DisplayPort PHY for MediaTek SoCs. + +config PHY_MTK_MIPI_CSI_0_5 + tristate "MediaTek MIPI CSI CD-PHY v0.5 Driver" + depends on ARCH_MEDIATEK || COMPILE_TEST + depends on OF + select GENERIC_PHY + help + Enable this to support the MIPI CSI CD-PHY receiver version 0.5. + The driver supports multiple CSI cdphy ports simultaneously. + + To compile this driver as a module, choose M here: the + module will be called phy-mtk-mipi-csi-0-5. diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile index c9a50395533e..63f2fa3ec7e5 100644 --- a/drivers/phy/mediatek/Makefile +++ b/drivers/phy/mediatek/Makefile @@ -19,3 +19,5 @@ phy-mtk-mipi-dsi-drv-y :=3D phy-mtk-mipi-dsi.o phy-mtk-mipi-dsi-drv-y +=3D phy-mtk-mipi-dsi-mt8173.o phy-mtk-mipi-dsi-drv-y +=3D phy-mtk-mipi-dsi-mt8183.o obj-$(CONFIG_PHY_MTK_MIPI_DSI) +=3D phy-mtk-mipi-dsi-drv.o + +obj-$(CONFIG_PHY_MTK_MIPI_CSI_0_5) +=3D phy-mtk-mipi-csi-0-5.o diff --git a/drivers/phy/mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h b/drivers/p= hy/mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h new file mode 100644 index 000000000000..97b4c27a1699 --- /dev/null +++ b/drivers/phy/mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, MediaTek Inc. + * Copyright (c) 2023, BayLibre Inc. + */ + +#ifndef __PHY_MTK_MIPI_CSI_V_0_5_RX_REG_H__ +#define __PHY_MTK_MIPI_CSI_V_0_5_RX_REG_H__ + +/* + * CSI1 and CSI2 are identical, and similar to CSI0. All CSIX macros are + * applicable to the three PHYs. Where differences exist, they are denoted= by + * macro names using CSI0 and CSI1, the latter being applicable to CSI1 and + * CSI2 alike. + */ + +#define MIPI_RX_ANA00_CSIXA 0x0000 +#define RG_CSI0A_CPHY_EN BIT(0) +#define RG_CSIXA_EQ_PROTECT_EN BIT(1) +#define RG_CSIXA_BG_LPF_EN BIT(2) +#define RG_CSIXA_BG_CORE_EN BIT(3) +#define RG_CSIXA_DPHY_L0_CKMODE_EN BIT(5) +#define RG_CSIXA_DPHY_L0_CKSEL BIT(6) +#define RG_CSIXA_DPHY_L1_CKMODE_EN BIT(8) +#define RG_CSIXA_DPHY_L1_CKSEL BIT(9) +#define RG_CSIXA_DPHY_L2_CKMODE_EN BIT(11) +#define RG_CSIXA_DPHY_L2_CKSEL BIT(12) + +#define MIPI_RX_ANA18_CSIXA 0x0018 +#define RG_CSI0A_L0_T0AB_EQ_IS GENMASK(5, 4) +#define RG_CSI0A_L0_T0AB_EQ_BW GENMASK(7, 6) +#define RG_CSI0A_L1_T1AB_EQ_IS GENMASK(21, 20) +#define RG_CSI0A_L1_T1AB_EQ_BW GENMASK(23, 22) +#define RG_CSI0A_L2_T1BC_EQ_IS GENMASK(21, 20) +#define RG_CSI0A_L2_T1BC_EQ_BW GENMASK(23, 22) +#define RG_CSI1A_L0_EQ_IS GENMASK(5, 4) +#define RG_CSI1A_L0_EQ_BW GENMASK(7, 6) +#define RG_CSI1A_L1_EQ_IS GENMASK(21, 20) +#define RG_CSI1A_L1_EQ_BW GENMASK(23, 22) +#define RG_CSI1A_L2_EQ_IS GENMASK(5, 4) +#define RG_CSI1A_L2_EQ_BW GENMASK(7, 6) + +#define MIPI_RX_ANA1C_CSIXA 0x001c +#define MIPI_RX_ANA20_CSI0A 0x0020 + +#define MIPI_RX_ANA24_CSIXA 0x0024 +#define RG_CSIXA_RESERVE GENMASK(31, 24) + +#define MIPI_RX_ANA40_CSIXA 0x0040 +#define RG_CSIXA_CPHY_FMCK_SEL GENMASK(1, 0) +#define RG_CSIXA_ASYNC_OPTION GENMASK(7, 4) +#define RG_CSIXA_CPHY_SPARE GENMASK(31, 16) + +#define MIPI_RX_WRAPPER80_CSIXA 0x0080 +#define CSR_CSI_RST_MODE GENMASK(17, 16) + +#define MIPI_RX_ANAA8_CSIXA 0x00a8 +#define RG_CSIXA_CDPHY_L0_T0_BYTECK_INVERT BIT(0) +#define RG_CSIXA_DPHY_L1_BYTECK_INVERT BIT(1) +#define RG_CSIXA_CDPHY_L2_T1_BYTECK_INVERT BIT(2) + +#endif diff --git a/drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c b/drivers/phy/medi= atek/phy-mtk-mipi-csi-0-5.c new file mode 100644 index 000000000000..dbe1d0713fb4 --- /dev/null +++ b/drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c @@ -0,0 +1,343 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek MIPI CSI v0.5 driver + * + * Copyright (c) 2023, MediaTek Inc. + * Copyright (c) 2023, BayLibre Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "phy-mtk-io.h" +#include "phy-mtk-mipi-csi-0-5-rx-reg.h" + +#define CSIXB_OFFSET 0x1000 + +struct mtk_mipi_cdphy_port { + struct device *dev; + void __iomem *base; + struct phy *phy; + u32 type; + u32 mode; + u32 num_lanes; +}; + +enum PHY_TYPE { + DPHY =3D 0, + CPHY, + CDPHY, +}; + +static void mtk_phy_csi_cdphy_ana_eq_tune(void __iomem *base) +{ + mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, + RG_CSI0A_L0_T0AB_EQ_IS, 1); + mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, + RG_CSI0A_L0_T0AB_EQ_BW, 1); + mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA, + RG_CSI0A_L1_T1AB_EQ_IS, 1); + mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA, + RG_CSI0A_L1_T1AB_EQ_BW, 1); + mtk_phy_update_field(base + MIPI_RX_ANA20_CSI0A, + RG_CSI0A_L2_T1BC_EQ_IS, 1); + mtk_phy_update_field(base + MIPI_RX_ANA20_CSI0A, + RG_CSI0A_L2_T1BC_EQ_BW, 1); + + mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, + RG_CSI0A_L0_T0AB_EQ_IS, 1); + mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, + RG_CSI0A_L0_T0AB_EQ_BW, 1); + mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA1C_CSIXA, + RG_CSI0A_L1_T1AB_EQ_IS, 1); + mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA1C_CSIXA, + RG_CSI0A_L1_T1AB_EQ_BW, 1); + mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA20_CSI0A, + RG_CSI0A_L2_T1BC_EQ_IS, 1); + mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA20_CSI0A, + RG_CSI0A_L2_T1BC_EQ_BW, 1); +} + +static void mtk_phy_csi_dphy_ana_eq_tune(void __iomem *base) +{ + mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, + RG_CSI1A_L0_EQ_IS, 1); + mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, + RG_CSI1A_L0_EQ_BW, 1); + mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, + RG_CSI1A_L1_EQ_IS, 1); + mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, + RG_CSI1A_L1_EQ_BW, 1); + mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA, + RG_CSI1A_L2_EQ_IS, 1); + mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA, + RG_CSI1A_L2_EQ_BW, 1); + + mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, + RG_CSI1A_L0_EQ_IS, 1); + mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, + RG_CSI1A_L0_EQ_BW, 1); + mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, + RG_CSI1A_L1_EQ_IS, 1); + mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, + RG_CSI1A_L1_EQ_BW, 1); + mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA1C_CSIXA, + RG_CSI1A_L2_EQ_IS, 1); + mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA1C_CSIXA, + RG_CSI1A_L2_EQ_BW, 1); +} + +static int mtk_mipi_phy_power_on(struct phy *phy) +{ + struct mtk_mipi_cdphy_port *port =3D phy_get_drvdata(phy); + void __iomem *base =3D port->base; + + /* + * The driver currently supports DPHY and CD-PHY phys, + * but the only mode supported is DPHY, + * so CD-PHY capable phys must be configured in DPHY mode + */ + if (port->type =3D=3D CDPHY) { + mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, + RG_CSI0A_CPHY_EN, 0); + mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, + RG_CSI0A_CPHY_EN, 0); + } + + /* + * Lane configuration: + * + * Only 4 data + 1 clock is supported for now with the following mapping: + * + * CSIXA_LNR0 --> D2 + * CSIXA_LNR1 --> D0 + * CSIXA_LNR2 --> C + * CSIXB_LNR0 --> D1 + * CSIXB_LNR1 --> D3 + */ + mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, + RG_CSIXA_DPHY_L0_CKMODE_EN, 0); + mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, + RG_CSIXA_DPHY_L0_CKSEL, 1); + mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, + RG_CSIXA_DPHY_L1_CKMODE_EN, 0); + mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, + RG_CSIXA_DPHY_L1_CKSEL, 1); + mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, + RG_CSIXA_DPHY_L2_CKMODE_EN, 1); + mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, + RG_CSIXA_DPHY_L2_CKSEL, 1); + + mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, + RG_CSIXA_DPHY_L0_CKMODE_EN, 0); + mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, + RG_CSIXA_DPHY_L0_CKSEL, 1); + mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, + RG_CSIXA_DPHY_L1_CKMODE_EN, 0); + mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, + RG_CSIXA_DPHY_L1_CKSEL, 1); + mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, + RG_CSIXA_DPHY_L2_CKMODE_EN, 0); + mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, + RG_CSIXA_DPHY_L2_CKSEL, 1); + + /* Byte clock invert */ + mtk_phy_update_field(base + MIPI_RX_ANAA8_CSIXA, + RG_CSIXA_CDPHY_L0_T0_BYTECK_INVERT, 1); + mtk_phy_update_field(base + MIPI_RX_ANAA8_CSIXA, + RG_CSIXA_DPHY_L1_BYTECK_INVERT, 1); + mtk_phy_update_field(base + MIPI_RX_ANAA8_CSIXA, + RG_CSIXA_CDPHY_L2_T1_BYTECK_INVERT, 1); + + mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANAA8_CSIXA, + RG_CSIXA_CDPHY_L0_T0_BYTECK_INVERT, 1); + mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANAA8_CSIXA, + RG_CSIXA_DPHY_L1_BYTECK_INVERT, 1); + mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANAA8_CSIXA, + RG_CSIXA_CDPHY_L2_T1_BYTECK_INVERT, 1); + + /* Start ANA EQ tuning */ + if (port->type =3D=3D CDPHY) + mtk_phy_csi_cdphy_ana_eq_tune(base); + else + mtk_phy_csi_dphy_ana_eq_tune(base); + + /* End ANA EQ tuning */ + mtk_phy_set_bits(base + MIPI_RX_ANA40_CSIXA, 0x90); + + mtk_phy_update_field(base + MIPI_RX_ANA24_CSIXA, + RG_CSIXA_RESERVE, 0x40); + mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA24_CSIXA, + RG_CSIXA_RESERVE, 0x40); + mtk_phy_update_field(base + MIPI_RX_WRAPPER80_CSIXA, + CSR_CSI_RST_MODE, 0); + mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_WRAPPER80_CSIXA, + CSR_CSI_RST_MODE, 0); + /* ANA power on */ + mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, + RG_CSIXA_BG_CORE_EN, 1); + mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, + RG_CSIXA_BG_CORE_EN, 1); + usleep_range(20, 40); + mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, + RG_CSIXA_BG_LPF_EN, 1); + mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, + RG_CSIXA_BG_LPF_EN, 1); + + return 0; +} + +static int mtk_mipi_phy_power_off(struct phy *phy) +{ + struct mtk_mipi_cdphy_port *port =3D phy_get_drvdata(phy); + void __iomem *base =3D port->base; + + /* Disable MIPI BG. */ + mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, + RG_CSIXA_BG_CORE_EN, 0); + mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, + RG_CSIXA_BG_LPF_EN, 0); + + mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, + RG_CSIXA_BG_CORE_EN, 0); + mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, + RG_CSIXA_BG_LPF_EN, 0); + + return 0; +} + +static struct phy *mtk_mipi_cdphy_xlate(struct device *dev, + struct of_phandle_args *args) +{ + struct mtk_mipi_cdphy_port *priv =3D dev_get_drvdata(dev); + + /* + * If PHY is CD-PHY then we need to get the operating mode + * For now only D-PHY mode is supported + */ + if (priv->type =3D=3D CDPHY) { + if (args->args_count !=3D 1) { + dev_err(dev, "invalid number of arguments\n"); + return ERR_PTR(-EINVAL); + } + switch (args->args[0]) { + case PHY_TYPE_DPHY: + priv->mode =3D DPHY; + if (priv->num_lanes !=3D 4) { + dev_err(dev, "Only 4D1C mode is supported for now!\n"); + return ERR_PTR(-EINVAL); + } + break; + default: + dev_err(dev, "Unsupported PHY type: %i\n", args->args[0]); + return ERR_PTR(-EINVAL); + } + } else { + if (args->args_count) { + dev_err(dev, "invalid number of arguments\n"); + return ERR_PTR(-EINVAL); + } + priv->mode =3D DPHY; + } + + return priv->phy; +} + +static const struct phy_ops mtk_cdphy_ops =3D { + .power_on =3D mtk_mipi_phy_power_on, + .power_off =3D mtk_mipi_phy_power_off, + .owner =3D THIS_MODULE, +}; + +static int mtk_mipi_cdphy_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct phy_provider *phy_provider; + struct mtk_mipi_cdphy_port *port; + struct phy *phy; + int ret; + u32 phy_type; + + port =3D devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); + if (!port) + return -ENOMEM; + + dev_set_drvdata(dev, port); + + port->dev =3D dev; + + port->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(port->base)) + return PTR_ERR(port->base); + + ret =3D of_property_read_u32(dev->of_node, "num-lanes", &port->num_lanes); + if (ret) { + dev_err(dev, "Failed to read num-lanes property: %i\n", ret); + return ret; + } + + /* + * phy-type is optional, if not present, PHY is considered to be CD-PHY + */ + if (device_property_present(dev, "phy-type")) { + ret =3D of_property_read_u32(dev->of_node, "phy-type", &phy_type); + if (ret) { + dev_err(dev, "Failed to read phy-type property: %i\n", ret); + return ret; + } + switch (phy_type) { + case PHY_TYPE_DPHY: + port->type =3D DPHY; + break; + default: + dev_err(dev, "Unsupported PHY type: %i\n", phy_type); + return -EINVAL; + } + } else { + port->type =3D CDPHY; + } + + phy =3D devm_phy_create(dev, NULL, &mtk_cdphy_ops); + if (IS_ERR(phy)) { + dev_err(dev, "Failed to create PHY: %ld\n", PTR_ERR(phy)); + return PTR_ERR(phy); + } + + port->phy =3D phy; + phy_set_drvdata(phy, port); + + phy_provider =3D devm_of_phy_provider_register(dev, mtk_mipi_cdphy_xlate); + if (IS_ERR(phy_provider)) { + dev_err(dev, "Failed to register PHY provider: %ld\n", + PTR_ERR(phy_provider)); + return PTR_ERR(phy_provider); + } + + return 0; +} + +static const struct of_device_id mtk_mipi_cdphy_of_match[] =3D { + { .compatible =3D "mediatek,mt8365-csi-rx" }, + { /* sentinel */}, +}; +MODULE_DEVICE_TABLE(of, mtk_mipi_cdphy_of_match); + +static struct platform_driver mipi_cdphy_pdrv =3D { + .probe =3D mtk_mipi_cdphy_probe, + .driver =3D { + .name =3D "mtk-mipi-csi-0-5", + .of_match_table =3D mtk_mipi_cdphy_of_match, + }, +}; +module_platform_driver(mipi_cdphy_pdrv); + +MODULE_DESCRIPTION("MediaTek MIPI CSI CD-PHY v0.5 Driver"); +MODULE_AUTHOR("Louis Kuo "); +MODULE_LICENSE("GPL"); --=20 2.41.0