From nobody Mon Feb 9 17:07:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F59EEB64D9 for ; Mon, 19 Jun 2023 15:06:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230418AbjFSPFm (ORCPT ); Mon, 19 Jun 2023 11:05:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50826 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229886AbjFSPFJ (ORCPT ); Mon, 19 Jun 2023 11:05:09 -0400 Received: from mail-oa1-x2d.google.com (mail-oa1-x2d.google.com [IPv6:2001:4860:4864:20::2d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 148DC19A7 for ; Mon, 19 Jun 2023 08:04:23 -0700 (PDT) Received: by mail-oa1-x2d.google.com with SMTP id 586e51a60fabf-1a9d57f8f9fso3311473fac.3 for ; Mon, 19 Jun 2023 08:04:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687187061; x=1689779061; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0m9rhWOn8qYbjuVQmQ20zeGCmNCpO//YkkWL6MmvNwg=; b=X4rnGsDhhgcstlEOl2O8Xh0D75fvA4vp4Lp/Hch/7e27uzGYUexdfNn8ekHr0mFBme xRW2Jgigs40z3tnW83vRGWXtbHyCNxWMrMBZJ6b1+dj/QesU3nVfa2PCr01i4TxFgyl5 JBfJcs93mVxfsGsi6e5la8UBwnx4Ipd7LNTUrMxmhu+eV0oXz/Fh8ARus8WzXPrPV/RS lHTfF2qz+tPJkpSeHgniix7/lRe+ods8MgZJ1EIpBI2htcjR7+uqSkL5vkczsm7R2HpG aU2lpY8HphbspEUze2dxaRhc3sjMSJ+IqLTvOqRFsi5UolLc0LtUzb8u+bMHAMdKZW1N WU3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687187061; x=1689779061; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0m9rhWOn8qYbjuVQmQ20zeGCmNCpO//YkkWL6MmvNwg=; b=Kv8l4h1HWnKWtaE2ehEhjhik805PqHfJ3iOl7ca8nJfHVeFwrBL1KXtcWrGs9b8faK c8BsZkHl0wxoIy+zu+KTxEkAa8JADQiOhy08yFq3KaUteHljv/bs5yMm0pcmwgBwzQr7 zqfHC+zEHyDZxMe+SEessxsCc5eQfXdYovYZ/2QC97fy+/Bnfrt+9IfRVyrvlQX76w03 9zQtKsBg32V+EI+ObXNqFNLhthDqSwYH3jxj07ePylU996ecOuwm6/S6//8VFZS1La+m 6MpJUElZ3ThR5+gWIRatbqx4ULtwRHWVoOWwc2E7krkEMgP6extqC5YTgy8ht2wjyzcI v5Wg== X-Gm-Message-State: AC+VfDxLG2zuXsaZjm/crNNnr+PRiyqGV1Q549DkvIuuWVIipDHl/b5F NUdcg86RIP9h9zOJFDMqu5aI X-Google-Smtp-Source: ACHHUZ5vRE7brlsRPe3Zp8R6nDsOTJqauqzXZH+wyitHVFyn/PXC/KWiff8ZoBlpQBA7Fut4l4DxOw== X-Received: by 2002:a05:6870:4710:b0:18f:558a:1f51 with SMTP id b16-20020a056870471000b0018f558a1f51mr11017078oaq.53.1687187061309; Mon, 19 Jun 2023 08:04:21 -0700 (PDT) Received: from localhost.localdomain ([117.217.183.37]) by smtp.gmail.com with ESMTPSA id 10-20020a17090a19ca00b0025efaf7a0d3sm2765480pjj.14.2023.06.19.08.04.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 08:04:20 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v4 1/9] PCI: qcom: Disable write access to read only registers for IP v2.3.3 Date: Mon, 19 Jun 2023 20:34:00 +0530 Message-Id: <20230619150408.8468-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> References: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In the post init sequence of v2.9.0, write access to read only registers are not disabled after updating the registers. Fix it by disabling the access after register update. Cc: Fixes: 5d76117f070d ("PCI: qcom: Add support for IPQ8074 PCIe controller") Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 4ab30892f6ef..ef385d36d653 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -836,6 +836,8 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *= pcie) writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + PCI_EXP_DEVCTL2); =20 + dw_pcie_dbi_ro_wr_dis(pci); + return 0; } =20 --=20 2.25.1 From nobody Mon Feb 9 17:07:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C9EEEB64D9 for ; Mon, 19 Jun 2023 15:05:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230310AbjFSPFc (ORCPT ); Mon, 19 Jun 2023 11:05:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53836 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230110AbjFSPFL (ORCPT ); Mon, 19 Jun 2023 11:05:11 -0400 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B20CE10F9 for ; Mon, 19 Jun 2023 08:04:25 -0700 (PDT) Received: by mail-pj1-x1034.google.com with SMTP id 98e67ed59e1d1-25edb50c3acso1677307a91.1 for ; Mon, 19 Jun 2023 08:04:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687187065; x=1689779065; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B3Dy+kmf8ZISKkCa0j/2ldqP//6MEtxXXYzBp48Kt14=; b=vtWdf8pUd95J6h7vr8vtdO30v//wqJANxXMEAkrewzCtyzASzN6R1KCTHyzYqpE4XQ hT2kjH2LwEyWdUVa4l+QKByViVVB3fDKG589hDa2B/GS61bFgtH+ehQeoiGkasGegRpT YQx9WvmTyBkaBEXT8Br5Lw/JrB0Ls9D8M5+/Z7CN0NCZmzBFuhT9LpZE4Mfddpg8iiJB qYKTrgxOMkA5GiRUJ49ooaOW55zu4RQ+IbRQgq55Naz61UT/c70rzn9DvhG+UMzQVjsF jUk0ALOCs2vziKBb4OHIaKfoPmUib0Swi38K7NWzs4xSpQQxbr5Io76IuGCZcrAT2BCt ImLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687187065; x=1689779065; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B3Dy+kmf8ZISKkCa0j/2ldqP//6MEtxXXYzBp48Kt14=; b=kus8bGHBWvk7Ec0RH2TJfx1wZrEMRpNwzmJmj5MHvEXcaYKlbl4QfjInBR1sTA6umk f/sVqefQzthRi/0WX8gUpkJzRiQDqAX2Ue4lqmvkUR4iXgZs6dvPQcpByen2wReman6r Jekj4szaMSwbWewi0J5qcBnKsyPxeWnSItjqawfCVjr7DOMhRzNC+DtTzWuSVDtlwKBU VDKdq8BVNJ1P1uxL82Yu0/K87G5qqaOqldHj6yHX9kR0uI/ybFTtqNlgNyMqII0mEJ+6 oFvALe3q1EK/fskliSL88u93xfuFaC4gQJWgud3miRgkYfn3v2SIpE/m+TLJgOJ/K16I SnXw== X-Gm-Message-State: AC+VfDw8xPmdSSNdgxT+iI7Z29OPbTNGuS+Qm2Ueqa78y5jzHAFLHXyW HLEHExRQC+x3cg002QqmoH2O X-Google-Smtp-Source: ACHHUZ4qUQ3hwY9mNHMbObMwBwLYFeY8h8minGqKyB/SxZiGDuFVPaHBPp6CG8/MfyFm+ePr+YTp5A== X-Received: by 2002:a17:90a:e516:b0:25e:8f12:a74d with SMTP id t22-20020a17090ae51600b0025e8f12a74dmr9926485pjy.44.1687187065087; Mon, 19 Jun 2023 08:04:25 -0700 (PDT) Received: from localhost.localdomain ([117.217.183.37]) by smtp.gmail.com with ESMTPSA id 10-20020a17090a19ca00b0025efaf7a0d3sm2765480pjj.14.2023.06.19.08.04.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 08:04:24 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, Manivannan Sadhasivam , Dmitry Baryshkov Subject: [PATCH v4 2/9] PCI: qcom: Use DWC helpers for modifying the read-only DBI registers Date: Mon, 19 Jun 2023 20:34:01 +0530 Message-Id: <20230619150408.8468-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> References: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" DWC core already exposes dw_pcie_dbi_ro_wr_{en/dis} helper APIs for enabling and disabling the write access to read only DBI registers. So let's use them instead of doing it manually. Also, the existing code doesn't disable the write access when it's done. This is also fixed now. Fixes: 5d76117f070d ("PCI: qcom: Add support for IPQ8074 PCIe controller") Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index ef385d36d653..01795ee7ce45 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -61,7 +61,6 @@ /* DBI registers */ #define AXI_MSTR_RESP_COMP_CTRL0 0x818 #define AXI_MSTR_RESP_COMP_CTRL1 0x81c -#define MISC_CONTROL_1_REG 0x8bc =20 /* MHI registers */ #define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04 @@ -132,9 +131,6 @@ /* AXI_MSTR_RESP_COMP_CTRL1 register fields */ #define CFG_BRIDGE_SB_INIT BIT(0) =20 -/* MISC_CONTROL_1_REG register fields */ -#define DBI_RO_WR_EN 1 - /* PCI_EXP_SLTCAP register fields */ #define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, 250) #define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, 1) @@ -826,7 +822,9 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *= pcie) writel(0, pcie->parf + PARF_Q2A_FLUSH); =20 writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND); - writel(DBI_RO_WR_EN, pci->dbi_base + MISC_CONTROL_1_REG); + + dw_pcie_dbi_ro_wr_en(pci); + writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); =20 val =3D readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); --=20 2.25.1 From nobody Mon Feb 9 17:07:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16EE4EB64D9 for ; Mon, 19 Jun 2023 15:05:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230356AbjFSPFh (ORCPT ); Mon, 19 Jun 2023 11:05:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230155AbjFSPFL (ORCPT ); Mon, 19 Jun 2023 11:05:11 -0400 Received: from mail-oi1-x233.google.com (mail-oi1-x233.google.com [IPv6:2607:f8b0:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CCB2F19AD for ; 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charset="utf-8" In the post init sequence of v2.9.0, write access to read only registers are not disabled after updating the registers. Fix it by disabling the access after register update. While at it, let's also add a newline after existing dw_pcie_dbi_ro_wr_en() guard function to align with rest of the driver. Fixes: 0cf7c2efe8ac ("PCI: qcom: Add IPQ60xx support") Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 01795ee7ce45..391a45d1e70a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1136,6 +1136,7 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie= *pcie) writel(0, pcie->parf + PARF_Q2A_FLUSH); =20 dw_pcie_dbi_ro_wr_en(pci); + writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); =20 val =3D readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); @@ -1145,6 +1146,8 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie= *pcie) writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + PCI_EXP_DEVCTL2); =20 + dw_pcie_dbi_ro_wr_dis(pci); + for (i =3D 0; i < 256; i++) writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i)); =20 --=20 2.25.1 From nobody Mon Feb 9 17:07:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D330EEB64DB for ; Mon, 19 Jun 2023 15:06:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231673AbjFSPFp (ORCPT ); Mon, 19 Jun 2023 11:05:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50922 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230266AbjFSPFQ (ORCPT ); Mon, 19 Jun 2023 11:05:16 -0400 Received: from mail-oa1-x2c.google.com (mail-oa1-x2c.google.com [IPv6:2001:4860:4864:20::2c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94BF319B1 for ; Mon, 19 Jun 2023 08:04:33 -0700 (PDT) Received: by mail-oa1-x2c.google.com with SMTP id 586e51a60fabf-1a98cf01151so3640353fac.2 for ; Mon, 19 Jun 2023 08:04:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687187073; x=1689779073; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=A98UhrwZrGyc1cxKVoW5P/FDL2aF5ZgMxYnhHsr36+Y=; b=EbDKlvCL0JefPd3whitlUpQhGUTNoSgjlKumRPfJJUtaRaRyJi+GXgBe31dGYr55C9 ooZUsmxAmjAppZ5UZ+pVq90G5rEuSmRRGezO0LHbpNsr0QBgX/e2E8trhwuUHjO1yboz IRGB2OQ4ucJyQBP+bUdwxIgscucJ1rALjFg6TBzngbUBHOD8yI8VZoJ+URb1UngfQi+R 1QjQXE4M89eAna+gUWYkhhDfYPqpcFOv2RDAWpYni6BG119UbCn8Ufsg5BjcyLIh/cUq niy86RbSU38dkxt+ppkH+YyH6w+dfqv88OPDc1LsJILqrDaL9+6bAAQXbBuxS11oViJJ xtDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687187073; x=1689779073; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=A98UhrwZrGyc1cxKVoW5P/FDL2aF5ZgMxYnhHsr36+Y=; b=SpaBBWQeNLkK5ueu7zSnjM3RkaXMRdI6VDqwhq3Dc72e60iQcFbXBeoOJOQYwZW1Me Opqs8goAUZCl/3JtY6HsEFQzfA434DkdMA2cPhMBOsviY3DwQMTBG1opLXbArlGMwl7v TfExhykHY+Z8IeJU+Qm3RUXbsWTq0KUI3WMBllu1v/6p9a2DjLF4OgcT831JOIf57sE4 Lz+ObjwbJGagt2152NdlAMODzoQi1kpJ4RXzVLAqMWeqFBionqCOIXZ+AgZa89zcrm3d UomIW1NyVOTcUy42PNT0ckJMk+73jAFkcWdrzmeC/2QLNvlqLx/DoXE4l32soGG1V5BJ vL6A== X-Gm-Message-State: AC+VfDxxSOKvhSTuA5EXlmqIrFa2YGt7RHFYNJ9GnqXQMbej5Bq8mSf9 CmMy7o2Kc7QSRNtFA2xmCNfX X-Google-Smtp-Source: ACHHUZ5SNI/kwXJznqe6EkZb9zy0U9dMvylpUymgT1TDx1gqUr+yiw95cWcUBffVD5qvzPCw77UOnw== X-Received: by 2002:a05:6871:894:b0:1a2:cfd7:bfdc with SMTP id r20-20020a056871089400b001a2cfd7bfdcmr12096478oaq.6.1687187072875; Mon, 19 Jun 2023 08:04:32 -0700 (PDT) Received: from localhost.localdomain ([117.217.183.37]) by smtp.gmail.com with ESMTPSA id 10-20020a17090a19ca00b0025efaf7a0d3sm2765480pjj.14.2023.06.19.08.04.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 08:04:32 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, Manivannan Sadhasivam , Dmitry Baryshkov Subject: [PATCH v4 4/9] PCI: qcom: Do not advertise hotplug capability for IPs v2.7.0 and v1.9.0 Date: Mon, 19 Jun 2023 20:34:03 +0530 Message-Id: <20230619150408.8468-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> References: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SoCs making use of Qcom PCIe controller IPs v2.7.0 and v1.9.0 do not support hotplug functionality. But the hotplug capability bit is set by default in the hardware. This causes the kernel PCI core to register hotplug service for the controller and send hotplug commands to it. But those commands will timeout generating messages as below during boot and suspend/resume. [ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x= 03c0 (issued 2020 msec ago) [ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x= 03c0 (issued 2048 msec ago) [ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x= 07c0 (issued 2020 msec ago) [ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x= 07c0 (issued 2052 msec ago) This not only spams the console output but also induces a delay of a couple of seconds. To fix this issue, let's clear the HPC bit in PCI_EXP_SLTCAP register as a part of the post init sequence to not advertise the hotplug capability for the controller. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 391a45d1e70a..8f448156eccc 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -270,6 +270,20 @@ static int qcom_pcie_start_link(struct dw_pcie *pci) return 0; } =20 +static void qcom_pcie_clear_hpc(struct dw_pcie *pci) +{ + u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u32 val; + + dw_pcie_dbi_ro_wr_en(pci); + + val =3D readl(pci->dbi_base + offset + PCI_EXP_SLTCAP); + val &=3D ~PCI_EXP_SLTCAP_HPC; + writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP); + + dw_pcie_dbi_ro_wr_dis(pci); +} + static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie) { u32 val; @@ -966,6 +980,13 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) return ret; } =20 +static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) +{ + qcom_pcie_clear_hpc(pcie->pci); + + return 0; +} + static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_7_0 *res =3D &pcie->res.v2_7_0; @@ -1272,6 +1293,7 @@ static const struct qcom_pcie_ops ops_2_3_3 =3D { static const struct qcom_pcie_ops ops_2_7_0 =3D { .get_resources =3D qcom_pcie_get_resources_2_7_0, .init =3D qcom_pcie_init_2_7_0, + .post_init =3D qcom_pcie_post_init_2_7_0, .deinit =3D qcom_pcie_deinit_2_7_0, .ltssm_enable =3D qcom_pcie_2_3_2_ltssm_enable, }; @@ -1280,6 +1302,7 @@ static const struct qcom_pcie_ops ops_2_7_0 =3D { static const struct qcom_pcie_ops ops_1_9_0 =3D { .get_resources =3D qcom_pcie_get_resources_2_7_0, .init =3D qcom_pcie_init_2_7_0, + .post_init =3D qcom_pcie_post_init_2_7_0, .deinit =3D qcom_pcie_deinit_2_7_0, .ltssm_enable =3D qcom_pcie_2_3_2_ltssm_enable, .config_sid =3D qcom_pcie_config_sid_1_9_0, --=20 2.25.1 From nobody Mon Feb 9 17:07:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1A52EB64DA for ; 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Mon, 19 Jun 2023 08:04:36 -0700 (PDT) Received: from localhost.localdomain ([117.217.183.37]) by smtp.gmail.com with ESMTPSA id 10-20020a17090a19ca00b0025efaf7a0d3sm2765480pjj.14.2023.06.19.08.04.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 08:04:36 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, Manivannan Sadhasivam , Dmitry Baryshkov Subject: [PATCH v4 5/9] PCI: qcom: Do not advertise hotplug capability for IPs v2.3.3 and v2.9.0 Date: Mon, 19 Jun 2023 20:34:04 +0530 Message-Id: <20230619150408.8468-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> References: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SoCs making use of Qcom PCIe controller IPs v2.3.3 and v2.9.0 do not support hotplug functionality. But the hotplug capability bit is set by default in the hardware. This causes the kernel PCI core to register hotplug service for the controller and send hotplug commands to it. But those commands will timeout generating messages as below during boot and suspend/resume. [ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x= 03c0 (issued 2020 msec ago) [ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x= 03c0 (issued 2048 msec ago) [ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x= 07c0 (issued 2020 msec ago) [ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x= 07c0 (issued 2052 msec ago) This not only spams the console output but also induces a delay of a couple of seconds. To fix this issue, let's not set the HPC bit in PCI_EXP_SLTCAP register as a part of the post init sequence to not advertise the hotplug capability for the controller. Tested-by: Sricharan Ramabadhran Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 8f448156eccc..64b6a8c6a99d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -140,7 +140,6 @@ PCI_EXP_SLTCAP_AIP | \ PCI_EXP_SLTCAP_PIP | \ PCI_EXP_SLTCAP_HPS | \ - PCI_EXP_SLTCAP_HPC | \ PCI_EXP_SLTCAP_EIP | \ PCIE_CAP_SLOT_POWER_LIMIT_VAL | \ PCIE_CAP_SLOT_POWER_LIMIT_SCALE) --=20 2.25.1 From nobody Mon Feb 9 17:07:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5033EC001DD for ; Mon, 19 Jun 2023 15:06:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229885AbjFSPGP (ORCPT ); Mon, 19 Jun 2023 11:06:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51000 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231215AbjFSPFT (ORCPT ); Mon, 19 Jun 2023 11:05:19 -0400 Received: from mail-oo1-xc2b.google.com (mail-oo1-xc2b.google.com [IPv6:2607:f8b0:4864:20::c2b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4004310D2 for ; Mon, 19 Jun 2023 08:04:41 -0700 (PDT) Received: by mail-oo1-xc2b.google.com with SMTP id 006d021491bc7-55e0706af99so2614692eaf.1 for ; Mon, 19 Jun 2023 08:04:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687187080; x=1689779080; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ltCiTsDOD5ydUGLVe1beQMJS2WLXn803YOi09x8rHPs=; b=RxWkwsnVaP8PkS+Iu4kSHBZxSZwvPpQ+s508UcLy+kyDeCLsGxKmiLpVWFg2PF8BV8 qHvx7HgeTREoO61gDGcC6iocs6OzDVNKR5mXRpAhSdTH+cjqgCj2/4AZuCTbFUp5BQ86 vRP8zT38xgSQpJurbkYnPowLjIjy1oXWE3Y9+Sy3tdESLZSM/LT9GbHjKDU76pMjLcJR TpV6/1IhdBV6+qT5qPhXMeXm7WTVqixTfEnBF2jD9+prcCNOoPjXFWZ+PmMLL5FTHasj nv0W4B2sAd5KKZeKfkQ2at0ZkrNKaZ0zxoMuY1RJ77gG+5qIcj47SAoxTzEfu37ytEAC wgog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687187080; x=1689779080; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ltCiTsDOD5ydUGLVe1beQMJS2WLXn803YOi09x8rHPs=; b=eo9a9gi5iC59eZq2qUPf2GcXJf5a2jGhLtNAtxr/xMGrRlWwyVqsHSO6ayqDNqSJAa W/tLXtmQ8iFb66f9GirsaLo7/4BoMU8Fr8F7nxCGburMLdjYvrCmFWBCs9C8RzSnBTDN 8qDUtU8+RM6YqCbGmBLIhgj54vt4tm27w6vldXTYR3yfXBZOd7Dmzzh7A4DeZdzvSoke Ms+UKuHSlOtzgYgH9BCvQk6jNs2JNRmNTnjZ7ZqQh7pq9mAQUYeYY03FNHmgXOkha08i Q6TlhHIYPEzOiJLqm53/D/H4dDkcrO3EouW6ajm7sy6pjVGjZLizT3nWxr3I32JfQt3e DIRA== X-Gm-Message-State: AC+VfDyGJqtDTIkRPh++3CPX6thGoU17dWaICrnstk0PeooKxHn59M1q fCyY+SCbQ3/+INX+t1o3z53r X-Google-Smtp-Source: ACHHUZ7jUCBkk2GZ6mqGYAXM5FgcdG5o86hJ+mp4QPxJJVPhMwUe4RqjHcCfX7pPSzpKAYrptEqsBw== X-Received: by 2002:aca:220d:0:b0:39c:4563:d23c with SMTP id b13-20020aca220d000000b0039c4563d23cmr1033259oic.46.1687187080530; Mon, 19 Jun 2023 08:04:40 -0700 (PDT) Received: from localhost.localdomain ([117.217.183.37]) by smtp.gmail.com with ESMTPSA id 10-20020a17090a19ca00b0025efaf7a0d3sm2765480pjj.14.2023.06.19.08.04.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 08:04:40 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v4 6/9] PCI: qcom: Do not advertise hotplug capability for IP v2.3.2 Date: Mon, 19 Jun 2023 20:34:05 +0530 Message-Id: <20230619150408.8468-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> References: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SoCs making use of Qcom PCIe controller IP v2.3.2 do not support hotplug functionality. But the hotplug capability bit is set by default in the hardware. This causes the kernel PCI core to register hotplug service for the controller and send hotplug commands to it. But those commands will timeout generating messages as below during boot and suspend/resume. [ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x= 03c0 (issued 2020 msec ago) [ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x= 03c0 (issued 2048 msec ago) [ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x= 07c0 (issued 2020 msec ago) [ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x= 07c0 (issued 2052 msec ago) This not only spams the console output but also induces a delay of a couple of seconds. To fix this issue, let's clear the HPC bit in PCI_EXP_SLTCAP register as a part of the post init sequence to not advertise the hotplug capability for the controller. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 64b6a8c6a99d..9c8dfd224e6e 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -616,6 +616,8 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *= pcie) val |=3D EN; writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); =20 + qcom_pcie_clear_hpc(pcie->pci); + return 0; } =20 --=20 2.25.1 From nobody Mon Feb 9 17:07:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5EFBAC001E0 for ; Mon, 19 Jun 2023 15:06:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230128AbjFSPGT (ORCPT ); Mon, 19 Jun 2023 11:06:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53734 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231373AbjFSPFU (ORCPT ); Mon, 19 Jun 2023 11:05:20 -0400 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EA2FA10DD for ; Mon, 19 Jun 2023 08:04:44 -0700 (PDT) Received: by mail-pj1-x102f.google.com with SMTP id 98e67ed59e1d1-25ec175b86bso2339437a91.1 for ; Mon, 19 Jun 2023 08:04:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687187084; x=1689779084; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Y/GAaoCJDXRESh8SzkgobGj/lkVGqp4sgMGqg7raF+w=; b=V9wXOuC0u6MhserqB+G6difAW8y4vzCRO18OAHl8pZnY48vHjoerHjTRsy+IVJqNcJ yRJh/pMYCSaxpRbcXAZFUsGHkqN5noXwbP/l5hlnO5r2kADG2CM0AQW5UtMji3Ppz+HK oTskUMwOIwrFfONX8n3SF9RSKCh3AOC19NJ12xPMVmOneKEpTzxmfyUAx+2pfBn5+AlB g1u2B4xEfnBiJo3IUVVaYLZuLmzh/0on5msGUMn1RuePtdM8wq4HTxrWZJupUxO/9MAd VhoNpR/Nu+8I11s4QzL5bA60jEWGz6kuipBuN5+njDVf+6Q8C3i7xutqeRTpI6rTbNPW wmAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687187084; x=1689779084; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Y/GAaoCJDXRESh8SzkgobGj/lkVGqp4sgMGqg7raF+w=; b=Jl4uPkWtUQAiEF7IRGzQakvEGeMyE+Cr/OFmU4Za+cVKLfYYjTpAC70O5W3/R4LuvU gCDqCROo9FZh17Oy+iGjRWAyR9f65SV0KPlJPjgkge5nguAgVWFZBo+/GDoZC+B1cCeT o/uTaT95Z8hRsry2cAwvX8VlRivHcn9OpZOfkFbqh5wpm1roVWQQcWR44W6q8DUSh1Gy C9zwoTP1R0FI5V66KkX8iZbfL8HEsDsnQamETAmZinjbZHvcjxtugkQ2xtyHMg3i0ziy KPee93XRUOEze6GkP0ynWYcHiJiCatCVQVh2SzCKgv69dCKxSm1MJHlQfaJOloJu7uae +sbQ== X-Gm-Message-State: AC+VfDwyl1sMQL0kQs5uZx2b2yFGKII+Aj8D0RRBosuiJus4rWjznY7H WSCRAKKmdUbiTSCyqCYYDrVi X-Google-Smtp-Source: ACHHUZ6Lgv+CRaeHvpmMJL0dObGrC9m7WE8tCgI+82+fGfhWauNyHfgIcYA5lk5e88NN9cFcN1NqLA== X-Received: by 2002:a17:90a:44:b0:260:a45e:751a with SMTP id 4-20020a17090a004400b00260a45e751amr1973170pjb.25.1687187084355; Mon, 19 Jun 2023 08:04:44 -0700 (PDT) Received: from localhost.localdomain ([117.217.183.37]) by smtp.gmail.com with ESMTPSA id 10-20020a17090a19ca00b0025efaf7a0d3sm2765480pjj.14.2023.06.19.08.04.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 08:04:44 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, Manivannan Sadhasivam , Dmitry Baryshkov Subject: [PATCH v4 7/9] PCI: qcom: Use post init sequence of IP v2.3.2 for v2.4.0 Date: Mon, 19 Jun 2023 20:34:06 +0530 Message-Id: <20230619150408.8468-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> References: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The post init sequence of IP v2.4.0 is same as v2.3.2. So let's reuse the v2.3.2 sequence which now also disables hotplug capability of the controller as it is not at all supported on any SoCs making use of this IP. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 30 +------------------------- 1 file changed, 1 insertion(+), 29 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 9c8dfd224e6e..e6db9e551752 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -703,34 +703,6 @@ static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie) return 0; } =20 -static int qcom_pcie_post_init_2_4_0(struct qcom_pcie *pcie) -{ - u32 val; - - /* enable PCIe clocks and resets */ - val =3D readl(pcie->parf + PARF_PHY_CTRL); - val &=3D ~PHY_TEST_PWR_DOWN; - writel(val, pcie->parf + PARF_PHY_CTRL); - - /* change DBI base address */ - writel(0, pcie->parf + PARF_DBI_BASE_ADDR); - - /* MAC PHY_POWERDOWN MUX DISABLE */ - val =3D readl(pcie->parf + PARF_SYS_CTRL); - val &=3D ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN; - writel(val, pcie->parf + PARF_SYS_CTRL); - - val =3D readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); - val |=3D BYPASS; - writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); - - val =3D readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); - val |=3D EN; - writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); - - return 0; -} - static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_3_3 *res =3D &pcie->res.v2_3_3; @@ -1276,7 +1248,7 @@ static const struct qcom_pcie_ops ops_2_3_2 =3D { static const struct qcom_pcie_ops ops_2_4_0 =3D { .get_resources =3D qcom_pcie_get_resources_2_4_0, .init =3D qcom_pcie_init_2_4_0, - .post_init =3D qcom_pcie_post_init_2_4_0, + .post_init =3D qcom_pcie_post_init_2_3_2, .deinit =3D qcom_pcie_deinit_2_4_0, .ltssm_enable =3D qcom_pcie_2_3_2_ltssm_enable, }; --=20 2.25.1 From nobody Mon Feb 9 17:07:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CDADC001DF for ; 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Mon, 19 Jun 2023 08:04:48 -0700 (PDT) Received: from localhost.localdomain ([117.217.183.37]) by smtp.gmail.com with ESMTPSA id 10-20020a17090a19ca00b0025efaf7a0d3sm2765480pjj.14.2023.06.19.08.04.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 08:04:47 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v4 8/9] PCI: qcom: Do not advertise hotplug capability for IP v1.0.0 Date: Mon, 19 Jun 2023 20:34:07 +0530 Message-Id: <20230619150408.8468-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> References: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SoCs making use of Qcom PCIe controller IP v1.0.0 do not support hotplug functionality. But the hotplug capability bit is set by default in the hardware. This causes the kernel PCI core to register hotplug service for the controller and send hotplug commands to it. But those commands will timeout generating messages as below during boot and suspend/resume. [ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x= 03c0 (issued 2020 msec ago) [ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x= 03c0 (issued 2048 msec ago) [ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x= 07c0 (issued 2020 msec ago) [ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x= 07c0 (issued 2052 msec ago) This not only spams the console output but also induces a delay of a couple of seconds. To fix this issue, let's clear the HPC bit in PCI_EXP_SLTCAP register as a part of the post init sequence to not advertise the hotplug capability for the controller. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index e6db9e551752..612266fb849a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -521,6 +521,8 @@ static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *= pcie) writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); } =20 + qcom_pcie_clear_hpc(pcie->pci); + return 0; } =20 --=20 2.25.1 From nobody Mon Feb 9 17:07:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B4CCC04A6A for ; Mon, 19 Jun 2023 15:06:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230484AbjFSPG0 (ORCPT ); Mon, 19 Jun 2023 11:06:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53770 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231555AbjFSPFY (ORCPT ); Mon, 19 Jun 2023 11:05:24 -0400 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ADBB610FE for ; Mon, 19 Jun 2023 08:04:52 -0700 (PDT) Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-25ec175b86bso2339538a91.1 for ; Mon, 19 Jun 2023 08:04:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687187092; x=1689779092; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BAHgbKUGLDFGyzp+XWYZ2sseIunYBsYQIO/Xldf05CU=; b=XvdhBRHXtdzN60JPoHiXZGxe3Wk8p3gEVy+80P/yCIUnn5q/UjEz6wGlLUXO/Tcp/B p8G1lcxkxYlP5xBp89pAbZZsu5TTC+qOgOXZx0qANDXGrqsKG5jlWFQVYeQMgog4GiVg wdxkf03RP9va75x46RLsvNHYZv9BMqmZ8LQqPta7Z6Zq8i+eA+ZPRky6UY20MUYFYLkr AiJCUirnH8hMizZurVOfFD4mTj3SdBbkydnp+kTqBxXNiyFRO5NJsTl5mYeFNPA5V9gf rSIvT9+E06Kh8dESXnCMURATxRR6WFsSxEu8qtTmzg8ahZcvAundvWcd7CY1HHfnvrf3 CsnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687187092; x=1689779092; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BAHgbKUGLDFGyzp+XWYZ2sseIunYBsYQIO/Xldf05CU=; b=RfWv/FxiTx/uYCqM6TamMbcZlMIqYb2LabKtlDsgGeN/axFPZhv3hoOmRTaViCLCf+ qgxomD7tDq9t9mr4+DA/swekWYzqC+nxn/nKTaCpbyy702kn2FM4UFhBJXxmZV6T+/nS Et2C8dLjJbYjRIdU8PmdHSu3sleCqJrZNdTRU+uyJ3+XdPzm5haNYIthhnQaU1FsUAq5 U8xoSlwg4tcrKE3F2g00pjB1+zEUd9Gt5iKGn5D9hGimZ+UqvqdTK+M++aL1sF5ao9tF Vi4tpqwuIGC6owpzzlyfy3GRorOFAvUQO27LE3bTORNVGOXxfAhDdSD6fiXOEgxI6ky2 w9rg== X-Gm-Message-State: AC+VfDxMe3LN5gzUZEL30Lff95RDkMu+u6VDo5XAaCfD+4ICzbRDVo+R nlj2OCHgBlbucu2wq3D6MRKB X-Google-Smtp-Source: ACHHUZ6mX5eL59bpG47z5VL6nwHLS8G/J72KGT7pv4yLTGgHpPgvjAqo6OiEFj63qn6HUCs8V7wiOA== X-Received: by 2002:a17:90a:df95:b0:25b:e216:bc15 with SMTP id p21-20020a17090adf9500b0025be216bc15mr10269006pjv.23.1687187092079; Mon, 19 Jun 2023 08:04:52 -0700 (PDT) Received: from localhost.localdomain ([117.217.183.37]) by smtp.gmail.com with ESMTPSA id 10-20020a17090a19ca00b0025efaf7a0d3sm2765480pjj.14.2023.06.19.08.04.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 08:04:51 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v4 9/9] PCI: qcom: Do not advertise hotplug capability for IP v2.1.0 Date: Mon, 19 Jun 2023 20:34:08 +0530 Message-Id: <20230619150408.8468-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> References: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SoCs making use of Qcom PCIe controller IP v2.1.0 do not support hotplug functionality. But the hotplug capability bit is set by default in the hardware. This causes the kernel PCI core to register hotplug service for the controller and send hotplug commands to it. But those commands will timeout generating messages as below during boot and suspend/resume. [ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x= 03c0 (issued 2020 msec ago) [ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x= 03c0 (issued 2048 msec ago) [ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x= 07c0 (issued 2020 msec ago) [ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x= 07c0 (issued 2052 msec ago) This not only spams the console output but also induces a delay of a couple of seconds. To fix this issue, let's clear the HPC bit in PCI_EXP_SLTCAP register as a part of the post init sequence to not advertise the hotplug capability for the controller. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 612266fb849a..7a87a47eb7ed 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -438,6 +438,8 @@ static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *= pcie) writel(CFG_BRIDGE_SB_INIT, pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL1); =20 + qcom_pcie_clear_hpc(pcie->pci); + return 0; } =20 --=20 2.25.1