From nobody Sat Feb 7 21:20:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C181EB64D9 for ; Mon, 19 Jun 2023 09:49:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230507AbjFSJtF (ORCPT ); Mon, 19 Jun 2023 05:49:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37688 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231699AbjFSJsQ (ORCPT ); Mon, 19 Jun 2023 05:48:16 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A88261BB; Mon, 19 Jun 2023 02:48:10 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id BCB8C855A; Mon, 19 Jun 2023 17:48:03 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 19 Jun 2023 17:48:03 +0800 Received: from ubuntu.localdomain (113.72.145.217) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 19 Jun 2023 17:48:02 +0800 From: Minda Chen To: Emil Renner Berthing , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Roger Quadros CC: , , , , "Paul Walmsley" , Palmer Dabbelt , Albert Ou , Minda Chen , Mason Huo Subject: [PATCH v7 2/5] dt-bindings: phy: Add StarFive JH7110 PCIe PHY Date: Mon, 19 Jun 2023 17:47:56 +0800 Message-ID: <20230619094759.21013-3-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230619094759.21013-1-minda.chen@starfivetech.com> References: <20230619094759.21013-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.145.217] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding. PCIe PHY0 (phy@10210000) can be used as USB 3.0 PHY. Signed-off-by: Minda Chen Reviewed-by: Hal Feng Reviewed-by: Rob Herring Reviewed-by: Roger Quadros --- .../phy/starfive,jh7110-pcie-phy.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-p= cie-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy= .yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml new file mode 100644 index 000000000000..2e83a6164cd1 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 PCIe 2.0 PHY + +maintainers: + - Minda Chen + +properties: + compatible: + const: starfive,jh7110-pcie-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + starfive,sys-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to System Register Controller sys_syscon = node. + - description: PHY connect offset of SYS_SYSCONSAIF__SYSCFG regi= ster for USB PHY. + description: + The phandle to System Register Controller syscon node and the PHY co= nnect offset + of SYS_SYSCONSAIF__SYSCFG register. Connect PHY to USB3 controller. + + starfive,stg-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to System Register Controller stg_syscon = node. + - description: PHY mode offset of STG_SYSCONSAIF__SYSCFG registe= r. + - description: PHY enable for USB offset of STG_SYSCONSAIF__SYSC= FG register. + description: + The phandle to System Register Controller syscon node and the offset + of STG_SYSCONSAIF__SYSCFG register for PCIe PHY. Total 2 regsisters = offset. + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@10210000 { + compatible =3D "starfive,jh7110-pcie-phy"; + reg =3D <0x10210000 0x10000>; + #phy-cells =3D <0>; + starfive,sys-syscon =3D <&sys_syscon 0x18>; + starfive,stg-syscon =3D <&stg_syscon 0x148 0x1f4>; + }; --=20 2.17.1