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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Andrew Halaney Cc: netdev@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Bartosz Golaszewski Subject: [RESEND PATCH v2 14/14] net: stmmac: dwmac-qcom-ethqos: add support for emac4 on sa8775p platforms Date: Mon, 19 Jun 2023 11:24:02 +0200 Message-Id: <20230619092402.195578-15-brgl@bgdev.pl> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230619092402.195578-1-brgl@bgdev.pl> References: <20230619092402.195578-1-brgl@bgdev.pl> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Bartosz Golaszewski sa8775p uses EMAC version 4, add the relevant defines, rename the has_emac3 switch to has_emac_ge_3 (has emac greater-or-equal than 3) and add the new compatible. Signed-off-by: Bartosz Golaszewski --- .../stmicro/stmmac/dwmac-qcom-ethqos.c | 65 +++++++++++++++---- 1 file changed, 51 insertions(+), 14 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/driv= ers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c index bdf59a179f87..fa0fc53c56a3 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c @@ -88,8 +88,9 @@ struct ethqos_emac_driver_data { const struct ethqos_emac_por *por; unsigned int num_por; bool rgmii_config_loopback_en; - bool has_emac3; + bool has_emac_ge_3; const char *link_clk_name; + bool has_integrated_pcs; struct dwmac4_addrs dwmac4_addrs; }; =20 @@ -108,7 +109,7 @@ struct qcom_ethqos { const struct ethqos_emac_por *por; unsigned int num_por; bool rgmii_config_loopback_en; - bool has_emac3; + bool has_emac_ge_3; }; =20 static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset) @@ -202,7 +203,7 @@ static const struct ethqos_emac_driver_data emac_v2_3_0= _data =3D { .por =3D emac_v2_3_0_por, .num_por =3D ARRAY_SIZE(emac_v2_3_0_por), .rgmii_config_loopback_en =3D true, - .has_emac3 =3D false, + .has_emac_ge_3 =3D false, }; =20 static const struct ethqos_emac_por emac_v2_1_0_por[] =3D { @@ -218,7 +219,7 @@ static const struct ethqos_emac_driver_data emac_v2_1_0= _data =3D { .por =3D emac_v2_1_0_por, .num_por =3D ARRAY_SIZE(emac_v2_1_0_por), .rgmii_config_loopback_en =3D false, - .has_emac3 =3D false, + .has_emac_ge_3 =3D false, }; =20 static const struct ethqos_emac_por emac_v3_0_0_por[] =3D { @@ -234,7 +235,41 @@ static const struct ethqos_emac_driver_data emac_v3_0_= 0_data =3D { .por =3D emac_v3_0_0_por, .num_por =3D ARRAY_SIZE(emac_v3_0_0_por), .rgmii_config_loopback_en =3D false, - .has_emac3 =3D true, + .has_emac_ge_3 =3D true, + .dwmac4_addrs =3D { + .dma_chan =3D 0x00008100, + .dma_chan_offset =3D 0x1000, + .mtl_chan =3D 0x00008000, + .mtl_chan_offset =3D 0x1000, + .mtl_ets_ctrl =3D 0x00008010, + .mtl_ets_ctrl_offset =3D 0x1000, + .mtl_txq_weight =3D 0x00008018, + .mtl_txq_weight_offset =3D 0x1000, + .mtl_send_slp_cred =3D 0x0000801c, + .mtl_send_slp_cred_offset =3D 0x1000, + .mtl_high_cred =3D 0x00008020, + .mtl_high_cred_offset =3D 0x1000, + .mtl_low_cred =3D 0x00008024, + .mtl_low_cred_offset =3D 0x1000, + }, +}; + +static const struct ethqos_emac_por emac_v4_0_0_por[] =3D { + { .offset =3D RGMII_IO_MACRO_CONFIG, .value =3D 0x40c01343 }, + { .offset =3D SDCC_HC_REG_DLL_CONFIG, .value =3D 0x2004642c }, + { .offset =3D SDCC_HC_REG_DDR_CONFIG, .value =3D 0x80040800 }, + { .offset =3D SDCC_HC_REG_DLL_CONFIG2, .value =3D 0x00200000 }, + { .offset =3D SDCC_USR_CTL, .value =3D 0x00010800 }, + { .offset =3D RGMII_IO_MACRO_CONFIG2, .value =3D 0x00002060 }, +}; + +static const struct ethqos_emac_driver_data emac_v4_0_0_data =3D { + .por =3D emac_v4_0_0_por, + .num_por =3D ARRAY_SIZE(emac_v3_0_0_por), + .rgmii_config_loopback_en =3D false, + .has_emac_ge_3 =3D true, + .link_clk_name =3D "phyaux", + .has_integrated_pcs =3D true, .dwmac4_addrs =3D { .dma_chan =3D 0x00008100, .dma_chan_offset =3D 0x1000, @@ -275,7 +310,7 @@ static int ethqos_dll_configure(struct qcom_ethqos *eth= qos) rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN, SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG); =20 - if (!ethqos->has_emac3) { + if (!ethqos->has_emac_ge_3) { rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN, 0, SDCC_HC_REG_DLL_CONFIG); =20 @@ -316,7 +351,7 @@ static int ethqos_dll_configure(struct qcom_ethqos *eth= qos) rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2); =20 - if (!ethqos->has_emac3) { + if (!ethqos->has_emac_ge_3) { rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS, 0, SDCC_HC_REG_DLL_CONFIG2); =20 @@ -386,7 +421,7 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *= ethqos) /* PRG_RCLK_DLY =3D TCXO period * TCXO_CYCLES_CNT / 2 * RX delay ns, * in practice this becomes PRG_RCLK_DLY =3D 52 * 4 / 2 * RX delay ns */ - if (ethqos->has_emac3) { + if (ethqos->has_emac_ge_3) { /* 0.9 ns */ rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY, 115, SDCC_HC_REG_DDR_CONFIG); @@ -421,7 +456,7 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *= ethqos) rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 0, RGMII_IO_MACRO_CONFIG2); =20 - if (ethqos->has_emac3) + if (ethqos->has_emac_ge_3) rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, RGMII_CONFIG2_RX_PROG_SWAP, RGMII_IO_MACRO_CONFIG2); @@ -461,7 +496,7 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *= ethqos) RGMII_IO_MACRO_CONFIG); rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 0, RGMII_IO_MACRO_CONFIG2); - if (ethqos->has_emac3) + if (ethqos->has_emac_ge_3) rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, RGMII_CONFIG2_RX_PROG_SWAP, RGMII_IO_MACRO_CONFIG2); @@ -510,7 +545,7 @@ static int ethqos_configure_rgmii(struct qcom_ethqos *e= thqos) rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG); =20 - if (ethqos->has_emac3) { + if (ethqos->has_emac_ge_3) { if (ethqos->speed =3D=3D SPEED_1000) { rgmii_writel(ethqos, 0x1800000, SDCC_TEST_CTL); rgmii_writel(ethqos, 0x2C010800, SDCC_USR_CTL); @@ -540,7 +575,7 @@ static int ethqos_configure_rgmii(struct qcom_ethqos *e= thqos) SDCC_HC_REG_DLL_CONFIG); =20 /* Set USR_CTL bit 26 with mask of 3 bits */ - if (!ethqos->has_emac3) + if (!ethqos->has_emac_ge_3) rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26), SDCC_USR_CTL); =20 @@ -719,7 +754,7 @@ static int qcom_ethqos_probe(struct platform_device *pd= ev) ethqos->por =3D data->por; ethqos->num_por =3D data->num_por; ethqos->rgmii_config_loopback_en =3D data->rgmii_config_loopback_en; - ethqos->has_emac3 =3D data->has_emac3; + ethqos->has_emac_ge_3 =3D data->has_emac_ge_3; =20 ethqos->link_clk =3D devm_clk_get(dev, data->link_clk_name ?: "rgmii"); if (IS_ERR(ethqos->link_clk)) { @@ -749,12 +784,13 @@ static int qcom_ethqos_probe(struct platform_device *= pdev) plat_dat->fix_mac_speed =3D ethqos_fix_mac_speed; plat_dat->dump_debug_regs =3D rgmii_dump; plat_dat->has_gmac4 =3D 1; - if (ethqos->has_emac3) + if (ethqos->has_emac_ge_3) plat_dat->dwmac4_addrs =3D &data->dwmac4_addrs; plat_dat->pmt =3D 1; plat_dat->tso_en =3D of_property_read_bool(np, "snps,tso"); if (of_device_is_compatible(np, "qcom,qcs404-ethqos")) plat_dat->rx_clk_runs_in_lpi =3D 1; + plat_dat->has_integrated_pcs =3D data->has_integrated_pcs; =20 if (ethqos->serdes_phy) { plat_dat->serdes_powerup =3D qcom_ethqos_serdes_powerup; @@ -775,6 +811,7 @@ static int qcom_ethqos_probe(struct platform_device *pd= ev) =20 static const struct of_device_id qcom_ethqos_match[] =3D { { .compatible =3D "qcom,qcs404-ethqos", .data =3D &emac_v2_3_0_data}, + { .compatible =3D "qcom,sa8775p-ethqos", .data =3D &emac_v4_0_0_data}, { .compatible =3D "qcom,sc8280xp-ethqos", .data =3D &emac_v3_0_0_data}, { .compatible =3D "qcom,sm8150-ethqos", .data =3D &emac_v2_1_0_data}, { } --=20 2.39.2