From nobody Thu Nov 14 16:54:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CF12EB64DB for ; Mon, 19 Jun 2023 08:55:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231294AbjFSIz6 (ORCPT ); Mon, 19 Jun 2023 04:55:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57798 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231407AbjFSIzD (ORCPT ); Mon, 19 Jun 2023 04:55:03 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB67110CE for ; Mon, 19 Jun 2023 01:54:19 -0700 (PDT) Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-988a076a7d3so143618466b.3 for ; Mon, 19 Jun 2023 01:54:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20221208.gappssmtp.com; s=20221208; t=1687164858; x=1689756858; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SPf+y2ctEZoMI72ckvhMmROgBE22+ZnhLuRaMNUscz8=; b=F64R/K5b0EadtnOiOYb2nUWFwjqy/DD2rMbote0vH67+ouDjC826VzJoxWZcGwsdnk 9muDCiKsoJbPer8L/kkf6N1BQZBkdBk3bvQimpZdfqUlsv6ajjnN+TkqeljkNVWhUYGQ OH0hhgNV1k04q8QJSk+XNGtE/YfK+AJXPrF0hUzL2CEZhYG4TYVhmq2daTJ1ywmtOy9Q nXLISjjAN9T4tkczbiXGulzCc+o+csIYSf24jd889J81rxdu5kGnPd7ST0lQvaHZAVJZ YpRa2A4UbS1YUmOWirRUwtskqEB65MjorIVlgWT2pu6JKSN5SEMGBPssR7doF3aXLkxC 83iA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687164858; x=1689756858; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SPf+y2ctEZoMI72ckvhMmROgBE22+ZnhLuRaMNUscz8=; b=QfH3q/rHjunel0FdIpsTZ3BXTvkKpLt5Qk8oOdhNxzB//A75SgjQd7JaBpAM5ZZVzq WGNOAhJHzc9FTMhm2TF/jZv2UlPT+FKHCbnVLz2KZ9G30YTC/nqA/N2fvGf2EWYN+EXY GfPQpc8fKpxa3YMjq/LRJp10MTpIaH2ESP0ZdnF4pDMwnjkkkY0ej0j452RapuG1ZvO3 tr33xUxix6YCt1kJHN2gIk2+OYa3be2a5uta0adV2DBGNHTlLpS/h3l6I7k44s11dQlU 40P4HIbWXOZ0iQf8Hc0vhYqf8iN3CMzvpOlgoYFywFtRvlIjJzVXvPOcH3K3n48+OPyw NjnQ== X-Gm-Message-State: AC+VfDyttvAk2OReJ7LIYb0qAB+eWuFCgcvEblt7SN6dvOuKTIBSxeRM NFlq+tLbrISJcqpL0G+H4Ml6iA== X-Google-Smtp-Source: ACHHUZ4xquicSAHJqPCvbaZI6t/3cxct9sf1uRZJnZNSgS5IGO+5UpgoU9/0zLRTgndvL4XX4DXcrg== X-Received: by 2002:a17:907:2d94:b0:96f:f046:9a92 with SMTP id gt20-20020a1709072d9400b0096ff0469a92mr9526606ejc.37.1687164858251; Mon, 19 Jun 2023 01:54:18 -0700 (PDT) Received: from blmsp.fritz.box ([2001:4090:a245:802c:bc2b:8db8:9210:41eb]) by smtp.gmail.com with ESMTPSA id h27-20020a17090619db00b00987a6e01e94sm2994339ejd.214.2023.06.19.01.54.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 01:54:17 -0700 (PDT) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger Cc: Chun-Jie Chen , AngeloGioacchino Del Regno , Tinghan Shen , Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Alexandre Bailon , Fabien Parent , Markus Schneider-Pargmann Subject: [PATCH v5 6/8] soc: mediatek: Add support for WAY_EN operations Date: Mon, 19 Jun 2023 10:53:42 +0200 Message-Id: <20230619085344.2885311-7-msp@baylibre.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230619085344.2885311-1-msp@baylibre.com> References: <20230619085344.2885311-1-msp@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Alexandre Bailon This updates the power domain to support WAY_EN operations. WAY_EN operations on mt8365 are using a different component to check for the acknowledgment, namely the infracfg-nao component. Also to enable a way it the bit needs to be cleared while disabling a way needs a bit to be set. To support these two operations two flags are added, BUS_PROT_INVERTED and BUS_PROT_STA_COMPONENT_INFRA_NAO. Additionally another regmap is created if the INFRA_NAO capability is set. This operation is required by the mt8365 for the MM power domain. Signed-off-by: Alexandre Bailon Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann --- drivers/soc/mediatek/mtk-pm-domains.c | 39 +++++++++++++++++++++++---- drivers/soc/mediatek/mtk-pm-domains.h | 7 +++-- 2 files changed, 39 insertions(+), 7 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index 3cdf62c0b6bd..4659f0a0aa08 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -44,6 +44,7 @@ struct scpsys_domain { struct clk_bulk_data *clks; int num_subsys_clks; struct clk_bulk_data *subsys_clks; + struct regmap *infracfg_nao; struct regmap *infracfg; struct regmap *smi; struct regulator *supply; @@ -127,13 +128,26 @@ static struct regmap *scpsys_bus_protect_get_regmap(s= truct scpsys_domain *pd, return pd->infracfg; } =20 +static struct regmap *scpsys_bus_protect_get_sta_regmap(struct scpsys_doma= in *pd, + const struct scpsys_bus_prot_data *bpd) +{ + if (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO) + return pd->infracfg_nao; + else + return scpsys_bus_protect_get_regmap(pd, bpd); +} + static int scpsys_bus_protect_clear(struct scpsys_domain *pd, const struct scpsys_bus_prot_data *bpd) { + struct regmap *sta_regmap =3D scpsys_bus_protect_get_sta_regmap(pd, bpd); struct regmap *regmap =3D scpsys_bus_protect_get_regmap(pd, bpd); + u32 expected_ack; u32 val; u32 sta_mask =3D bpd->bus_prot_sta_mask; =20 + expected_ack =3D (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO ? sta_mas= k : 0); + if (bpd->flags & BUS_PROT_REG_UPDATE) regmap_clear_bits(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask); else @@ -142,14 +156,15 @@ static int scpsys_bus_protect_clear(struct scpsys_dom= ain *pd, if (bpd->flags & BUS_PROT_IGNORE_CLR_ACK) return 0; =20 - return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta, - val, !(val & sta_mask), + return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta, + val, (val & sta_mask) =3D=3D expected_ack, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); } =20 static int scpsys_bus_protect_set(struct scpsys_domain *pd, const struct scpsys_bus_prot_data *bpd) { + struct regmap *sta_regmap =3D scpsys_bus_protect_get_sta_regmap(pd, bpd); struct regmap *regmap =3D scpsys_bus_protect_get_regmap(pd, bpd); u32 val; u32 sta_mask =3D bpd->bus_prot_sta_mask; @@ -159,7 +174,7 @@ static int scpsys_bus_protect_set(struct scpsys_domain = *pd, else regmap_write(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask); =20 - return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta, + return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta, val, (val & sta_mask) =3D=3D sta_mask, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); } @@ -173,7 +188,10 @@ static int scpsys_bus_protect_enable(struct scpsys_dom= ain *pd) if (!bpd->bus_prot_set_clr_mask) break; =20 - ret =3D scpsys_bus_protect_set(pd, bpd); + if (bpd->flags & BUS_PROT_INVERTED) + ret =3D scpsys_bus_protect_clear(pd, bpd); + else + ret =3D scpsys_bus_protect_set(pd, bpd); if (ret) return ret; } @@ -190,7 +208,10 @@ static int scpsys_bus_protect_disable(struct scpsys_do= main *pd) if (!bpd->bus_prot_set_clr_mask) continue; =20 - ret =3D scpsys_bus_protect_clear(pd, bpd); + if (bpd->flags & BUS_PROT_INVERTED) + ret =3D scpsys_bus_protect_set(pd, bpd); + else + ret =3D scpsys_bus_protect_clear(pd, bpd); if (ret) return ret; } @@ -377,6 +398,14 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys= *scpsys, struct device_no return ERR_CAST(pd->smi); } =20 + pd->infracfg_nao =3D syscon_regmap_lookup_by_phandle(node, "mediatek,infr= acfg-nao"); + if (IS_ERR(pd->infracfg_nao)) { + if (MTK_SCPD_CAPS(pd, MTK_SCPD_HAS_INFRA_NAO)) + return ERR_CAST(pd->infracfg_nao); + + pd->infracfg_nao =3D NULL; + } + num_clks =3D of_clk_get_parent_count(node); if (num_clks > 0) { /* Calculate number of subsys_clks */ diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/m= tk-pm-domains.h index 356788263db2..562d4e92ce16 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -11,6 +11,7 @@ /* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */ #define MTK_SCPD_ALWAYS_ON BIT(5) #define MTK_SCPD_EXT_BUCK_ISO BIT(6) +#define MTK_SCPD_HAS_INFRA_NAO BIT(7) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) =20 #define SPM_VDE_PWR_CON 0x0210 @@ -45,8 +46,10 @@ enum scpsys_bus_prot_flags { BUS_PROT_REG_UPDATE =3D BIT(1), BUS_PROT_IGNORE_CLR_ACK =3D BIT(2), - BUS_PROT_COMPONENT_INFRA =3D BIT(3), - BUS_PROT_COMPONENT_SMI =3D BIT(4), + BUS_PROT_INVERTED =3D BIT(3), + BUS_PROT_COMPONENT_INFRA =3D BIT(4), + BUS_PROT_COMPONENT_SMI =3D BIT(5), + BUS_PROT_STA_COMPONENT_INFRA_NAO =3D BIT(6), }; =20 #define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \ --=20 2.40.1