From nobody Thu Nov 14 05:48:50 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBC3EEB64DB for ; Mon, 19 Jun 2023 08:55:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231283AbjFSIzv (ORCPT ); Mon, 19 Jun 2023 04:55:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231346AbjFSIy6 (ORCPT ); Mon, 19 Jun 2023 04:54:58 -0400 Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [IPv6:2a00:1450:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DEF71198A for ; Mon, 19 Jun 2023 01:54:14 -0700 (PDT) Received: by mail-ej1-x636.google.com with SMTP id a640c23a62f3a-988c495f35fso64815666b.1 for ; Mon, 19 Jun 2023 01:54:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20221208.gappssmtp.com; s=20221208; t=1687164853; x=1689756853; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uCk2o78QJovxCBxHGCqUEI7lERo4Q9zzKKe3nZzi7bU=; b=XndUvNuLbXetnuwKNHQ/a99NjtlS5s/EIiqqyXeCg2JuEqvATrYp+JUWshqowAdVcE 4XbnFjJYSYwu0UHB07jr3eaRPtluoy8gkpAQ7pOOhXe0jnp2l35nOLauSw0v2mUdT148 cCj8cZqNpnjoMnh0PZhNVcrHf8KA7kgyPne03Q8hFnbaLVZRWcgPhNBQrLalfoaQu1lm lUJ0liBiWMY264PkZ+MKlS/XOK0/YT60gUS6vRRPOaCWydCGbXy1L9/PvdeOcGd6flKF 0Dm0+ZDPF7LxdHHi/xi6dUKjni1mtHhvtrpDxi4kdvsSXwV9FKeV614Y0Cop+ELygqM+ wlRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687164853; x=1689756853; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uCk2o78QJovxCBxHGCqUEI7lERo4Q9zzKKe3nZzi7bU=; b=cCkHyjeWJ41G03YcXiby0qt+FScxaBsZRW5vVcATgjeBVYgwl/ftOOVlHBlkVeDa81 CheMNuNtCmpTqzi3iaWk3ae8b6Np4Gc/3r7KnXRK3ECAHJL5pjlrDHG/wplVDovlFBPC fXoP37QaVzmO6lQrbwFbUWK1SZN4mmpUNKXMFCnT5j9xNJssCmq4R/eV+29mhuTos9Je yBeNw6HTBwt6CBGwOwlBLuaCoMPE8oE020FBqo2y5OpSzNhFZGGjl0hQvD0Jire2/jcG +4TR7FlC7Byf2OT0gTl638UgvVXLGJ0BmaiOnS0dRiaGXnyIoYaawdak5RnPCaticPH8 cw9w== X-Gm-Message-State: AC+VfDxA+3tJleIS6CCTjNk2iRhK/yYW2Pj3WOXq9o4mffoeM5rITBmk LjP9gi9MkxJMbOKcj6R1obboRQ== X-Google-Smtp-Source: ACHHUZ5sEfWqTzjCCenwo1ykE256kkZnCGe/9WTP+NkT0rg32qCzMppl/jPtMr517AIU2Zjl773h/g== X-Received: by 2002:a17:907:707:b0:966:634d:9d84 with SMTP id xb7-20020a170907070700b00966634d9d84mr8238442ejb.20.1687164853305; Mon, 19 Jun 2023 01:54:13 -0700 (PDT) Received: from blmsp.fritz.box ([2001:4090:a245:802c:bc2b:8db8:9210:41eb]) by smtp.gmail.com with ESMTPSA id h27-20020a17090619db00b00987a6e01e94sm2994339ejd.214.2023.06.19.01.54.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 01:54:12 -0700 (PDT) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger Cc: Chun-Jie Chen , AngeloGioacchino Del Regno , Tinghan Shen , Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Fabien Parent , Markus Schneider-Pargmann , Krzysztof Kozlowski , Rob Herring Subject: [PATCH v5 1/8] dt-bindings: power: Add MT8365 power domains Date: Mon, 19 Jun 2023 10:53:37 +0200 Message-Id: <20230619085344.2885311-2-msp@baylibre.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230619085344.2885311-1-msp@baylibre.com> References: <20230619085344.2885311-1-msp@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fabien Parent Add power domains dt-bindings for MT8365. Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann Acked-by: Krzysztof Kozlowski Reviewed-by: Rob Herring --- .../power/mediatek,power-controller.yaml | 6 ++++++ .../dt-bindings/power/mediatek,mt8365-power.h | 19 +++++++++++++++++++ 2 files changed, 25 insertions(+) create mode 100644 include/dt-bindings/power/mediatek,mt8365-power.h diff --git a/Documentation/devicetree/bindings/power/mediatek,power-control= ler.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controlle= r.yaml index c9acef80f452..8985e2df8a56 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -31,6 +31,7 @@ properties: - mediatek,mt8188-power-controller - mediatek,mt8192-power-controller - mediatek,mt8195-power-controller + - mediatek,mt8365-power-controller =20 '#power-domain-cells': const: 1 @@ -88,6 +89,7 @@ $defs: "include/dt-bindings/power/mediatek,mt8188-power.h" - for MT= 8188 type power domain. "include/dt-bindings/power/mt8192-power.h" - for MT8192 type= power domain. "include/dt-bindings/power/mt8195-power.h" - for MT8195 type= power domain. + "include/dt-bindings/power/mediatek,mt8365-power.h" - for MT= 8365 type power domain. maxItems: 1 =20 clocks: @@ -115,6 +117,10 @@ $defs: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the device containing the INFRACFG registe= r range. =20 + mediatek,infracfg-nao: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the device containing the INFRACFG-NAO reg= ister range. + mediatek,smi: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the device containing the SMI register ran= ge. diff --git a/include/dt-bindings/power/mediatek,mt8365-power.h b/include/dt= -bindings/power/mediatek,mt8365-power.h new file mode 100644 index 000000000000..e6cfd0ec7871 --- /dev/null +++ b/include/dt-bindings/power/mediatek,mt8365-power.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2022 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_POWER_MT8365_POWER_H +#define _DT_BINDINGS_POWER_MT8365_POWER_H + +#define MT8365_POWER_DOMAIN_MM 0 +#define MT8365_POWER_DOMAIN_CONN 1 +#define MT8365_POWER_DOMAIN_MFG 2 +#define MT8365_POWER_DOMAIN_AUDIO 3 +#define MT8365_POWER_DOMAIN_CAM 4 +#define MT8365_POWER_DOMAIN_DSP 5 +#define MT8365_POWER_DOMAIN_VDEC 6 +#define MT8365_POWER_DOMAIN_VENC 7 +#define MT8365_POWER_DOMAIN_APU 8 + +#endif /* _DT_BINDINGS_POWER_MT8365_POWER_H */ --=20 2.40.1 From nobody Thu Nov 14 05:48:50 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B8A1EB64D9 for ; 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Mon, 19 Jun 2023 01:54:14 -0700 (PDT) Received: from blmsp.fritz.box ([2001:4090:a245:802c:bc2b:8db8:9210:41eb]) by smtp.gmail.com with ESMTPSA id h27-20020a17090619db00b00987a6e01e94sm2994339ejd.214.2023.06.19.01.54.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 01:54:13 -0700 (PDT) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger Cc: Chun-Jie Chen , AngeloGioacchino Del Regno , Tinghan Shen , Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Markus Schneider-Pargmann Subject: [PATCH v5 2/8] soc: mediatek: pm-domains: Move bools to a flags field Date: Mon, 19 Jun 2023 10:53:38 +0200 Message-Id: <20230619085344.2885311-3-msp@baylibre.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230619085344.2885311-1-msp@baylibre.com> References: <20230619085344.2885311-1-msp@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To simplify the macros, use a flags field for simple bools. This is in preparation for more flags. Signed-off-by: Markus Schneider-Pargmann Reviewed-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-pm-domains.c | 6 +++--- drivers/soc/mediatek/mtk-pm-domains.h | 19 +++++++++++-------- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index 354249cc1b12..aa9ab413479e 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -128,7 +128,7 @@ static int _scpsys_bus_protect_enable(const struct scps= ys_bus_prot_data *bpd, st if (!mask) break; =20 - if (bpd[i].bus_prot_reg_update) + if (bpd[i].flags & BUS_PROT_REG_UPDATE) regmap_set_bits(regmap, bpd[i].bus_prot_set, mask); else regmap_write(regmap, bpd[i].bus_prot_set, mask); @@ -165,12 +165,12 @@ static int _scpsys_bus_protect_disable(const struct s= cpsys_bus_prot_data *bpd, if (!mask) continue; =20 - if (bpd[i].bus_prot_reg_update) + if (bpd[i].flags & BUS_PROT_REG_UPDATE) regmap_clear_bits(regmap, bpd[i].bus_prot_clr, mask); else regmap_write(regmap, bpd[i].bus_prot_clr, mask); =20 - if (bpd[i].ignore_clr_ack) + if (bpd[i].flags & BUS_PROT_IGNORE_CLR_ACK) continue; =20 ret =3D regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/m= tk-pm-domains.h index 5ec53ee073c4..e26c8c317a6b 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -42,23 +42,27 @@ =20 #define SPM_MAX_BUS_PROT_DATA 6 =20 -#define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) { \ +enum scpsys_bus_prot_flags { + BUS_PROT_REG_UPDATE =3D BIT(1), + BUS_PROT_IGNORE_CLR_ACK =3D BIT(2), +}; + +#define _BUS_PROT(_mask, _set, _clr, _sta, _flags) { \ .bus_prot_mask =3D (_mask), \ .bus_prot_set =3D _set, \ .bus_prot_clr =3D _clr, \ .bus_prot_sta =3D _sta, \ - .bus_prot_reg_update =3D _update, \ - .ignore_clr_ack =3D _ignore, \ + .flags =3D _flags \ } =20 #define BUS_PROT_WR(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, false, false) + _BUS_PROT(_mask, _set, _clr, _sta, 0) =20 #define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, false, true) + _BUS_PROT(_mask, _set, _clr, _sta, BUS_PROT_IGNORE_CLR_ACK) =20 #define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, true, false) + _BUS_PROT(_mask, _set, _clr, _sta, BUS_PROT_REG_UPDATE) =20 #define BUS_PROT_UPDATE_TOPAXI(_mask) \ BUS_PROT_UPDATE(_mask, \ @@ -71,8 +75,7 @@ struct scpsys_bus_prot_data { u32 bus_prot_set; u32 bus_prot_clr; u32 bus_prot_sta; - bool bus_prot_reg_update; - bool ignore_clr_ack; + u32 flags; }; =20 /** --=20 2.40.1 From nobody Thu Nov 14 05:48:50 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8ABC8EB64DC for ; Mon, 19 Jun 2023 08:55:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230517AbjFSIz3 (ORCPT ); Mon, 19 Jun 2023 04:55:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58500 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231373AbjFSIzA (ORCPT ); Mon, 19 Jun 2023 04:55:00 -0400 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 29BF8D1 for ; Mon, 19 Jun 2023 01:54:17 -0700 (PDT) Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-970028cfb6cso538322766b.1 for ; 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charset="utf-8" bus_prot_mask is used for all operations, set clear and acknowledge. In preparation of m8365 power domain support split this one mask into two, one mask for set and clear, another one for acknowledge. Signed-off-by: Markus Schneider-Pargmann --- drivers/soc/mediatek/mtk-pm-domains.c | 24 ++++++++++++++---------- drivers/soc/mediatek/mtk-pm-domains.h | 14 ++++++++------ 2 files changed, 22 insertions(+), 16 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index aa9ab413479e..c801fa763e89 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -123,18 +123,20 @@ static int _scpsys_bus_protect_enable(const struct sc= psys_bus_prot_data *bpd, st int i, ret; =20 for (i =3D 0; i < SPM_MAX_BUS_PROT_DATA; i++) { - u32 val, mask =3D bpd[i].bus_prot_mask; + u32 val; + u32 set_clr_mask =3D bpd[i].bus_prot_set_clr_mask; + u32 sta_mask =3D bpd[i].bus_prot_sta_mask; =20 - if (!mask) + if (!set_clr_mask) break; =20 if (bpd[i].flags & BUS_PROT_REG_UPDATE) - regmap_set_bits(regmap, bpd[i].bus_prot_set, mask); + regmap_set_bits(regmap, bpd[i].bus_prot_set, set_clr_mask); else - regmap_write(regmap, bpd[i].bus_prot_set, mask); + regmap_write(regmap, bpd[i].bus_prot_set, set_clr_mask); =20 ret =3D regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, - val, (val & mask) =3D=3D mask, + val, (val & sta_mask) =3D=3D sta_mask, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); if (ret) return ret; @@ -160,21 +162,23 @@ static int _scpsys_bus_protect_disable(const struct s= cpsys_bus_prot_data *bpd, int i, ret; =20 for (i =3D SPM_MAX_BUS_PROT_DATA - 1; i >=3D 0; i--) { - u32 val, mask =3D bpd[i].bus_prot_mask; + u32 val; + u32 set_clr_mask =3D bpd[i].bus_prot_set_clr_mask; + u32 sta_mask =3D bpd[i].bus_prot_sta_mask; =20 - if (!mask) + if (!set_clr_mask) continue; =20 if (bpd[i].flags & BUS_PROT_REG_UPDATE) - regmap_clear_bits(regmap, bpd[i].bus_prot_clr, mask); + regmap_clear_bits(regmap, bpd[i].bus_prot_clr, set_clr_mask); else - regmap_write(regmap, bpd[i].bus_prot_clr, mask); + regmap_write(regmap, bpd[i].bus_prot_clr, set_clr_mask); =20 if (bpd[i].flags & BUS_PROT_IGNORE_CLR_ACK) continue; =20 ret =3D regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, - val, !(val & mask), + val, !(val & sta_mask), MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); if (ret) return ret; diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/m= tk-pm-domains.h index e26c8c317a6b..4b6ae56e7c95 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -47,22 +47,23 @@ enum scpsys_bus_prot_flags { BUS_PROT_IGNORE_CLR_ACK =3D BIT(2), }; =20 -#define _BUS_PROT(_mask, _set, _clr, _sta, _flags) { \ - .bus_prot_mask =3D (_mask), \ +#define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \ + .bus_prot_set_clr_mask =3D (_set_clr_mask), \ .bus_prot_set =3D _set, \ .bus_prot_clr =3D _clr, \ + .bus_prot_sta_mask =3D (_sta_mask), \ .bus_prot_sta =3D _sta, \ .flags =3D _flags \ } =20 #define BUS_PROT_WR(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, 0) + _BUS_PROT(_mask, _set, _clr, _mask, _sta, 0) =20 #define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, BUS_PROT_IGNORE_CLR_ACK) + _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_IGNORE_CLR_ACK) =20 #define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, BUS_PROT_REG_UPDATE) + _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_REG_UPDATE) =20 #define BUS_PROT_UPDATE_TOPAXI(_mask) \ BUS_PROT_UPDATE(_mask, \ @@ -71,9 +72,10 @@ enum scpsys_bus_prot_flags { INFRA_TOPAXI_PROTECTSTA1) =20 struct scpsys_bus_prot_data { - u32 bus_prot_mask; + u32 bus_prot_set_clr_mask; u32 bus_prot_set; u32 bus_prot_clr; + u32 bus_prot_sta_mask; u32 bus_prot_sta; u32 flags; }; --=20 2.40.1 From nobody Thu Nov 14 05:48:50 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBB4CEB64D9 for ; Mon, 19 Jun 2023 08:56:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230332AbjFSI4r (ORCPT ); Mon, 19 Jun 2023 04:56:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231377AbjFSIzA (ORCPT ); Mon, 19 Jun 2023 04:55:00 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A938F1FFF for ; Mon, 19 Jun 2023 01:54:17 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-9875c2d949eso371350466b.0 for ; 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charset="utf-8" Separate the register access used for bus protection enable/disable into their own functions. These will be used later for WAY_EN support. Signed-off-by: Markus Schneider-Pargmann --- drivers/soc/mediatek/mtk-pm-domains.c | 68 +++++++++++++++------------ 1 file changed, 39 insertions(+), 29 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index c801fa763e89..69dc24a73ce9 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -118,26 +118,50 @@ static int scpsys_sram_disable(struct scpsys_domain *= pd) MTK_POLL_TIMEOUT); } =20 +static int scpsys_bus_protect_clear(const struct scpsys_bus_prot_data *bpd, + struct regmap *regmap) +{ + u32 val; + u32 sta_mask =3D bpd->bus_prot_sta_mask; + + if (bpd->flags & BUS_PROT_REG_UPDATE) + regmap_clear_bits(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask); + else + regmap_write(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask); + + if (bpd->flags & BUS_PROT_IGNORE_CLR_ACK) + return 0; + + return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta, + val, !(val & sta_mask), + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); +} + +static int scpsys_bus_protect_set(const struct scpsys_bus_prot_data *bpd, + struct regmap *regmap) +{ + u32 val; + u32 sta_mask =3D bpd->bus_prot_sta_mask; + + if (bpd->flags & BUS_PROT_REG_UPDATE) + regmap_set_bits(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask); + else + regmap_write(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask); + + return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta, + val, (val & sta_mask) =3D=3D sta_mask, + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); +} + static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *b= pd, struct regmap *regmap) { int i, ret; =20 for (i =3D 0; i < SPM_MAX_BUS_PROT_DATA; i++) { - u32 val; - u32 set_clr_mask =3D bpd[i].bus_prot_set_clr_mask; - u32 sta_mask =3D bpd[i].bus_prot_sta_mask; - - if (!set_clr_mask) + if (!bpd[i].bus_prot_set_clr_mask) break; =20 - if (bpd[i].flags & BUS_PROT_REG_UPDATE) - regmap_set_bits(regmap, bpd[i].bus_prot_set, set_clr_mask); - else - regmap_write(regmap, bpd[i].bus_prot_set, set_clr_mask); - - ret =3D regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, - val, (val & sta_mask) =3D=3D sta_mask, - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + ret =3D scpsys_bus_protect_set(&bpd[i], regmap); if (ret) return ret; } @@ -162,24 +186,10 @@ static int _scpsys_bus_protect_disable(const struct s= cpsys_bus_prot_data *bpd, int i, ret; =20 for (i =3D SPM_MAX_BUS_PROT_DATA - 1; i >=3D 0; i--) { - u32 val; - u32 set_clr_mask =3D bpd[i].bus_prot_set_clr_mask; - u32 sta_mask =3D bpd[i].bus_prot_sta_mask; - - if (!set_clr_mask) - continue; - - if (bpd[i].flags & BUS_PROT_REG_UPDATE) - regmap_clear_bits(regmap, bpd[i].bus_prot_clr, set_clr_mask); - else - regmap_write(regmap, bpd[i].bus_prot_clr, set_clr_mask); - - if (bpd[i].flags & BUS_PROT_IGNORE_CLR_ACK) + if (!bpd[i].bus_prot_set_clr_mask) continue; =20 - ret =3D regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, - val, !(val & sta_mask), - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + ret =3D scpsys_bus_protect_clear(&bpd[i], regmap); if (ret) return ret; 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Mon, 19 Jun 2023 01:54:17 -0700 (PDT) Received: from blmsp.fritz.box ([2001:4090:a245:802c:bc2b:8db8:9210:41eb]) by smtp.gmail.com with ESMTPSA id h27-20020a17090619db00b00987a6e01e94sm2994339ejd.214.2023.06.19.01.54.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 01:54:16 -0700 (PDT) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger Cc: Chun-Jie Chen , AngeloGioacchino Del Regno , Tinghan Shen , Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Markus Schneider-Pargmann Subject: [PATCH v5 5/8] soc: mediatek: pm-domains: Unify configuration for infracfg and smi Date: Mon, 19 Jun 2023 10:53:41 +0200 Message-Id: <20230619085344.2885311-6-msp@baylibre.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230619085344.2885311-1-msp@baylibre.com> References: <20230619085344.2885311-1-msp@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann --- drivers/soc/mediatek/mt6795-pm-domains.h | 16 +- drivers/soc/mediatek/mt8167-pm-domains.h | 20 +- drivers/soc/mediatek/mt8173-pm-domains.h | 16 +- drivers/soc/mediatek/mt8183-pm-domains.h | 198 ++++----- drivers/soc/mediatek/mt8186-pm-domains.h | 212 +++++----- drivers/soc/mediatek/mt8188-pm-domains.h | 518 +++++++++++------------ drivers/soc/mediatek/mt8192-pm-domains.h | 262 ++++++------ drivers/soc/mediatek/mt8195-pm-domains.h | 464 ++++++++++---------- drivers/soc/mediatek/mtk-pm-domains.c | 64 ++- drivers/soc/mediatek/mtk-pm-domains.h | 37 +- 10 files changed, 908 insertions(+), 899 deletions(-) diff --git a/drivers/soc/mediatek/mt6795-pm-domains.h b/drivers/soc/mediate= k/mt6795-pm-domains.h index ef07c9dfdd9b..a3f7785b04bd 100644 --- a/drivers/soc/mediatek/mt6795-pm-domains.h +++ b/drivers/soc/mediatek/mt6795-pm-domains.h @@ -46,9 +46,9 @@ static const struct scpsys_domain_data scpsys_domain_data= _mt6795[] =3D { .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, .sram_pdn_bits =3D GENMASK(11, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 | - MT8173_TOP_AXI_PROT_EN_MM_M1), + .bp_cfg =3D { + BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 | + MT8173_TOP_AXI_PROT_EN_MM_M1), }, }, [MT6795_POWER_DOMAIN_MJC] =3D { @@ -95,11 +95,11 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt6795[] =3D { .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, .sram_pdn_bits =3D GENMASK(13, 8), .sram_pdn_ack_bits =3D GENMASK(21, 16), - .bp_infracfg =3D { - BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S | - MT8173_TOP_AXI_PROT_EN_MFG_M0 | - MT8173_TOP_AXI_PROT_EN_MFG_M1 | - MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT), + .bp_cfg =3D { + BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S | + MT8173_TOP_AXI_PROT_EN_MFG_M0 | + MT8173_TOP_AXI_PROT_EN_MFG_M1 | + MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT), }, }, }; diff --git a/drivers/soc/mediatek/mt8167-pm-domains.h b/drivers/soc/mediate= k/mt8167-pm-domains.h index 4d6c32759606..8a0e898b79ab 100644 --- a/drivers/soc/mediatek/mt8167-pm-domains.h +++ b/drivers/soc/mediatek/mt8167-pm-domains.h @@ -22,9 +22,9 @@ static const struct scpsys_domain_data scpsys_domain_data= _mt8167[] =3D { .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, .sram_pdn_bits =3D GENMASK(11, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MM_EMI | - MT8167_TOP_AXI_PROT_EN_MCU_MM), + .bp_cfg =3D { + BUS_PROT_INFRA_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MM_EMI | + MT8167_TOP_AXI_PROT_EN_MCU_MM), }, .caps =3D MTK_SCPD_ACTIVE_WAKEUP, }, @@ -56,9 +56,9 @@ static const struct scpsys_domain_data scpsys_domain_data= _mt8167[] =3D { .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, .sram_pdn_bits =3D 0, .sram_pdn_ack_bits =3D 0, - .bp_infracfg =3D { - BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MCU_MFG | - MT8167_TOP_AXI_PROT_EN_MFG_EMI), + .bp_cfg =3D { + BUS_PROT_INFRA_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MCU_MFG | + MT8167_TOP_AXI_PROT_EN_MFG_EMI), }, }, [MT8167_POWER_DOMAIN_MFG_2D] =3D { @@ -88,10 +88,10 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8167[] =3D { .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D 0, .caps =3D MTK_SCPD_ACTIVE_WAKEUP, - .bp_infracfg =3D { - BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_CONN_EMI | - MT8167_TOP_AXI_PROT_EN_CONN_MCU | - MT8167_TOP_AXI_PROT_EN_MCU_CONN), + .bp_cfg =3D { + BUS_PROT_INFRA_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_CONN_EMI | + MT8167_TOP_AXI_PROT_EN_CONN_MCU | + MT8167_TOP_AXI_PROT_EN_MCU_CONN), }, }, }; diff --git a/drivers/soc/mediatek/mt8173-pm-domains.h b/drivers/soc/mediate= k/mt8173-pm-domains.h index 1a5dc63b7357..7be0f47f5214 100644 --- a/drivers/soc/mediatek/mt8173-pm-domains.h +++ b/drivers/soc/mediatek/mt8173-pm-domains.h @@ -46,9 +46,9 @@ static const struct scpsys_domain_data scpsys_domain_data= _mt8173[] =3D { .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, .sram_pdn_bits =3D GENMASK(11, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 | - MT8173_TOP_AXI_PROT_EN_MM_M1), + .bp_cfg =3D { + BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 | + MT8173_TOP_AXI_PROT_EN_MM_M1), }, }, [MT8173_POWER_DOMAIN_VENC_LT] =3D { @@ -106,11 +106,11 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8173[] =3D { .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, .sram_pdn_bits =3D GENMASK(13, 8), .sram_pdn_ack_bits =3D GENMASK(21, 16), - .bp_infracfg =3D { - BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S | - MT8173_TOP_AXI_PROT_EN_MFG_M0 | - MT8173_TOP_AXI_PROT_EN_MFG_M1 | - MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT), + .bp_cfg =3D { + BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S | + MT8173_TOP_AXI_PROT_EN_MFG_M0 | + MT8173_TOP_AXI_PROT_EN_MFG_M1 | + MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT), }, }, }; diff --git a/drivers/soc/mediatek/mt8183-pm-domains.h b/drivers/soc/mediate= k/mt8183-pm-domains.h index 99de67fe5de8..5d5c0a620da4 100644 --- a/drivers/soc/mediatek/mt8183-pm-domains.h +++ b/drivers/soc/mediatek/mt8183-pm-domains.h @@ -28,9 +28,11 @@ static const struct scpsys_domain_data scpsys_domain_dat= a_mt8183[] =3D { .pwr_sta2nd_offs =3D 0x0184, .sram_pdn_bits =3D 0, .sram_pdn_ack_bits =3D 0, - .bp_infracfg =3D { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CONN, MT8183_TOP_AXI_PROT_EN_SET, - MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_CONN, + MT8183_TOP_AXI_PROT_EN_SET, + MT8183_TOP_AXI_PROT_EN_CLR, + MT8183_TOP_AXI_PROT_EN_STA1), }, }, [MT8183_POWER_DOMAIN_MFG_ASYNC] =3D { @@ -79,11 +81,15 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8183[] =3D { .pwr_sta2nd_offs =3D 0x0184, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_MFG, MT8183_TOP_AXI_PROT_EN_1_SET, - MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1), - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MFG, MT8183_TOP_AXI_PROT_EN_SET, - MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_1_MFG, + MT8183_TOP_AXI_PROT_EN_1_SET, + MT8183_TOP_AXI_PROT_EN_1_CLR, + MT8183_TOP_AXI_PROT_EN_STA1_1), + BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_MFG, + MT8183_TOP_AXI_PROT_EN_SET, + MT8183_TOP_AXI_PROT_EN_CLR, + MT8183_TOP_AXI_PROT_EN_STA1), }, }, [MT8183_POWER_DOMAIN_DISP] =3D { @@ -94,17 +100,19 @@ static const struct scpsys_domain_data scpsys_domain_d= ata_mt8183[] =3D { .pwr_sta2nd_offs =3D 0x0184, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_DISP, MT8183_TOP_AXI_PROT_EN_1_SET, - MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1), - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_DISP, MT8183_TOP_AXI_PROT_EN_SET, - MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), - }, - .bp_smi =3D { - BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_DISP, - MT8183_SMI_COMMON_CLAMP_EN_SET, - MT8183_SMI_COMMON_CLAMP_EN_CLR, - MT8183_SMI_COMMON_CLAMP_EN), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_1_DISP, + MT8183_TOP_AXI_PROT_EN_1_SET, + MT8183_TOP_AXI_PROT_EN_1_CLR, + MT8183_TOP_AXI_PROT_EN_STA1_1), + BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_DISP, + MT8183_TOP_AXI_PROT_EN_SET, + MT8183_TOP_AXI_PROT_EN_CLR, + MT8183_TOP_AXI_PROT_EN_STA1), + BUS_PROT_SMI_WR(MT8183_SMI_COMMON_SMI_CLAMP_DISP, + MT8183_SMI_COMMON_CLAMP_EN_SET, + MT8183_SMI_COMMON_CLAMP_EN_CLR, + MT8183_SMI_COMMON_CLAMP_EN), }, }, [MT8183_POWER_DOMAIN_CAM] =3D { @@ -115,21 +123,23 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8183[] =3D { .pwr_sta2nd_offs =3D 0x0184, .sram_pdn_bits =3D GENMASK(9, 8), .sram_pdn_ack_bits =3D GENMASK(13, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_CAM, MT8183_TOP_AXI_PROT_EN_MM_SE= T, - MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CAM, MT8183_TOP_AXI_PROT_EN_SET, - MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND, - MT8183_TOP_AXI_PROT_EN_MM_SET, - MT8183_TOP_AXI_PROT_EN_MM_CLR, - MT8183_TOP_AXI_PROT_EN_MM_STA1), - }, - .bp_smi =3D { - BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_CAM, - MT8183_SMI_COMMON_CLAMP_EN_SET, - MT8183_SMI_COMMON_CLAMP_EN_CLR, - MT8183_SMI_COMMON_CLAMP_EN), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_MM_CAM, + MT8183_TOP_AXI_PROT_EN_MM_SET, + MT8183_TOP_AXI_PROT_EN_MM_CLR, + MT8183_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_CAM, + MT8183_TOP_AXI_PROT_EN_SET, + MT8183_TOP_AXI_PROT_EN_CLR, + MT8183_TOP_AXI_PROT_EN_STA1), + BUS_PROT_INFRA_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND, + MT8183_TOP_AXI_PROT_EN_MM_SET, + MT8183_TOP_AXI_PROT_EN_MM_CLR, + MT8183_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_SMI_WR(MT8183_SMI_COMMON_SMI_CLAMP_CAM, + MT8183_SMI_COMMON_CLAMP_EN_SET, + MT8183_SMI_COMMON_CLAMP_EN_CLR, + MT8183_SMI_COMMON_CLAMP_EN), }, }, [MT8183_POWER_DOMAIN_ISP] =3D { @@ -140,21 +150,19 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8183[] =3D { .pwr_sta2nd_offs =3D 0x0184, .sram_pdn_bits =3D GENMASK(9, 8), .sram_pdn_ack_bits =3D GENMASK(13, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_ISP, - MT8183_TOP_AXI_PROT_EN_MM_SET, - MT8183_TOP_AXI_PROT_EN_MM_CLR, - MT8183_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND, - MT8183_TOP_AXI_PROT_EN_MM_SET, - MT8183_TOP_AXI_PROT_EN_MM_CLR, - MT8183_TOP_AXI_PROT_EN_MM_STA1), - }, - .bp_smi =3D { - BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_ISP, - MT8183_SMI_COMMON_CLAMP_EN_SET, - MT8183_SMI_COMMON_CLAMP_EN_CLR, - MT8183_SMI_COMMON_CLAMP_EN), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_MM_ISP, + MT8183_TOP_AXI_PROT_EN_MM_SET, + MT8183_TOP_AXI_PROT_EN_MM_CLR, + MT8183_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_INFRA_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND, + MT8183_TOP_AXI_PROT_EN_MM_SET, + MT8183_TOP_AXI_PROT_EN_MM_CLR, + MT8183_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_SMI_WR(MT8183_SMI_COMMON_SMI_CLAMP_ISP, + MT8183_SMI_COMMON_CLAMP_EN_SET, + MT8183_SMI_COMMON_CLAMP_EN_CLR, + MT8183_SMI_COMMON_CLAMP_EN), }, }, [MT8183_POWER_DOMAIN_VDEC] =3D { @@ -165,11 +173,11 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8183[] =3D { .pwr_sta2nd_offs =3D 0x0184, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_smi =3D { - BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VDEC, - MT8183_SMI_COMMON_CLAMP_EN_SET, - MT8183_SMI_COMMON_CLAMP_EN_CLR, - MT8183_SMI_COMMON_CLAMP_EN), + .bp_cfg =3D { + BUS_PROT_SMI_WR(MT8183_SMI_COMMON_SMI_CLAMP_VDEC, + MT8183_SMI_COMMON_CLAMP_EN_SET, + MT8183_SMI_COMMON_CLAMP_EN_CLR, + MT8183_SMI_COMMON_CLAMP_EN), }, }, [MT8183_POWER_DOMAIN_VENC] =3D { @@ -180,11 +188,11 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8183[] =3D { .pwr_sta2nd_offs =3D 0x0184, .sram_pdn_bits =3D GENMASK(11, 8), .sram_pdn_ack_bits =3D GENMASK(15, 12), - .bp_smi =3D { - BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VENC, - MT8183_SMI_COMMON_CLAMP_EN_SET, - MT8183_SMI_COMMON_CLAMP_EN_CLR, - MT8183_SMI_COMMON_CLAMP_EN), + .bp_cfg =3D { + BUS_PROT_SMI_WR(MT8183_SMI_COMMON_SMI_CLAMP_VENC, + MT8183_SMI_COMMON_CLAMP_EN_SET, + MT8183_SMI_COMMON_CLAMP_EN_CLR, + MT8183_SMI_COMMON_CLAMP_EN), }, }, [MT8183_POWER_DOMAIN_VPU_TOP] =3D { @@ -195,25 +203,23 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8183[] =3D { .pwr_sta2nd_offs =3D 0x0184, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP, - MT8183_TOP_AXI_PROT_EN_MM_SET, - MT8183_TOP_AXI_PROT_EN_MM_CLR, - MT8183_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_VPU_TOP, - MT8183_TOP_AXI_PROT_EN_SET, - MT8183_TOP_AXI_PROT_EN_CLR, - MT8183_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND, - MT8183_TOP_AXI_PROT_EN_MM_SET, - MT8183_TOP_AXI_PROT_EN_MM_CLR, - MT8183_TOP_AXI_PROT_EN_MM_STA1), - }, - .bp_smi =3D { - BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP, - MT8183_SMI_COMMON_CLAMP_EN_SET, - MT8183_SMI_COMMON_CLAMP_EN_CLR, - MT8183_SMI_COMMON_CLAMP_EN), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP, + MT8183_TOP_AXI_PROT_EN_MM_SET, + MT8183_TOP_AXI_PROT_EN_MM_CLR, + MT8183_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_VPU_TOP, + MT8183_TOP_AXI_PROT_EN_SET, + MT8183_TOP_AXI_PROT_EN_CLR, + MT8183_TOP_AXI_PROT_EN_STA1), + BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND, + MT8183_TOP_AXI_PROT_EN_MM_SET, + MT8183_TOP_AXI_PROT_EN_MM_CLR, + MT8183_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_SMI_WR(MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP, + MT8183_SMI_COMMON_CLAMP_EN_SET, + MT8183_SMI_COMMON_CLAMP_EN_CLR, + MT8183_SMI_COMMON_CLAMP_EN), }, }, [MT8183_POWER_DOMAIN_VPU_CORE0] =3D { @@ -224,15 +230,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8183[] =3D { .pwr_sta2nd_offs =3D 0x0184, .sram_pdn_bits =3D GENMASK(11, 8), .sram_pdn_ack_bits =3D GENMASK(13, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0, - MT8183_TOP_AXI_PROT_EN_MCU_SET, - MT8183_TOP_AXI_PROT_EN_MCU_CLR, - MT8183_TOP_AXI_PROT_EN_MCU_STA1), - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND, - MT8183_TOP_AXI_PROT_EN_MCU_SET, - MT8183_TOP_AXI_PROT_EN_MCU_CLR, - MT8183_TOP_AXI_PROT_EN_MCU_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0, + MT8183_TOP_AXI_PROT_EN_MCU_SET, + MT8183_TOP_AXI_PROT_EN_MCU_CLR, + MT8183_TOP_AXI_PROT_EN_MCU_STA1), + BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND, + MT8183_TOP_AXI_PROT_EN_MCU_SET, + MT8183_TOP_AXI_PROT_EN_MCU_CLR, + MT8183_TOP_AXI_PROT_EN_MCU_STA1), }, .caps =3D MTK_SCPD_SRAM_ISO, }, @@ -244,15 +250,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8183[] =3D { .pwr_sta2nd_offs =3D 0x0184, .sram_pdn_bits =3D GENMASK(11, 8), .sram_pdn_ack_bits =3D GENMASK(13, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1, - MT8183_TOP_AXI_PROT_EN_MCU_SET, - MT8183_TOP_AXI_PROT_EN_MCU_CLR, - MT8183_TOP_AXI_PROT_EN_MCU_STA1), - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND, - MT8183_TOP_AXI_PROT_EN_MCU_SET, - MT8183_TOP_AXI_PROT_EN_MCU_CLR, - MT8183_TOP_AXI_PROT_EN_MCU_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1, + MT8183_TOP_AXI_PROT_EN_MCU_SET, + MT8183_TOP_AXI_PROT_EN_MCU_CLR, + MT8183_TOP_AXI_PROT_EN_MCU_STA1), + BUS_PROT_INFRA_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND, + MT8183_TOP_AXI_PROT_EN_MCU_SET, + MT8183_TOP_AXI_PROT_EN_MCU_CLR, + MT8183_TOP_AXI_PROT_EN_MCU_STA1), }, .caps =3D MTK_SCPD_SRAM_ISO, }, diff --git a/drivers/soc/mediatek/mt8186-pm-domains.h b/drivers/soc/mediate= k/mt8186-pm-domains.h index fce86f79c505..25b5651f0ae2 100644 --- a/drivers/soc/mediatek/mt8186-pm-domains.h +++ b/drivers/soc/mediatek/mt8186-pm-domains.h @@ -33,23 +33,23 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8186[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP2, - MT8186_TOP_AXI_PROT_EN_SET, - MT8186_TOP_AXI_PROT_EN_CLR, - MT8186_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP3, - MT8186_TOP_AXI_PROT_EN_SET, - MT8186_TOP_AXI_PROT_EN_CLR, - MT8186_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP2, + MT8186_TOP_AXI_PROT_EN_SET, + MT8186_TOP_AXI_PROT_EN_CLR, + MT8186_TOP_AXI_PROT_EN_STA), + BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP3, + MT8186_TOP_AXI_PROT_EN_SET, + MT8186_TOP_AXI_PROT_EN_CLR, + MT8186_TOP_AXI_PROT_EN_STA), + BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, }, @@ -101,15 +101,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8186[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_DIS_STEP2, - MT8186_TOP_AXI_PROT_EN_SET, - MT8186_TOP_AXI_PROT_EN_CLR, - MT8186_TOP_AXI_PROT_EN_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_DIS_STEP2, + MT8186_TOP_AXI_PROT_EN_SET, + MT8186_TOP_AXI_PROT_EN_CLR, + MT8186_TOP_AXI_PROT_EN_STA), }, }, [MT8186_POWER_DOMAIN_IMG] =3D { @@ -120,15 +120,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8186[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -150,15 +150,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8186[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -170,15 +170,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8186[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -210,15 +210,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8186[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -230,15 +230,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8186[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -250,15 +250,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8186[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1, - MT8186_TOP_AXI_PROT_EN_2_SET, - MT8186_TOP_AXI_PROT_EN_2_CLR, - MT8186_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2, - MT8186_TOP_AXI_PROT_EN_2_SET, - MT8186_TOP_AXI_PROT_EN_2_CLR, - MT8186_TOP_AXI_PROT_EN_2_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1, + MT8186_TOP_AXI_PROT_EN_2_SET, + MT8186_TOP_AXI_PROT_EN_2_CLR, + MT8186_TOP_AXI_PROT_EN_2_STA), + BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2, + MT8186_TOP_AXI_PROT_EN_2_SET, + MT8186_TOP_AXI_PROT_EN_2_CLR, + MT8186_TOP_AXI_PROT_EN_2_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -268,23 +268,23 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8186[] =3D { .ctl_offs =3D 0x304, .pwr_sta_offs =3D 0x16C, .pwr_sta2nd_offs =3D 0x170, - .bp_infracfg =3D { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2, - MT8186_TOP_AXI_PROT_EN_SET, - MT8186_TOP_AXI_PROT_EN_CLR, - MT8186_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3, - MT8186_TOP_AXI_PROT_EN_SET, - MT8186_TOP_AXI_PROT_EN_CLR, - MT8186_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4, - MT8186_TOP_AXI_PROT_EN_SET, - MT8186_TOP_AXI_PROT_EN_CLR, - MT8186_TOP_AXI_PROT_EN_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2, + MT8186_TOP_AXI_PROT_EN_SET, + MT8186_TOP_AXI_PROT_EN_CLR, + MT8186_TOP_AXI_PROT_EN_STA), + BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3, + MT8186_TOP_AXI_PROT_EN_SET, + MT8186_TOP_AXI_PROT_EN_CLR, + MT8186_TOP_AXI_PROT_EN_STA), + BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4, + MT8186_TOP_AXI_PROT_EN_SET, + MT8186_TOP_AXI_PROT_EN_CLR, + MT8186_TOP_AXI_PROT_EN_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, }, @@ -320,15 +320,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8186[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1, - MT8186_TOP_AXI_PROT_EN_3_SET, - MT8186_TOP_AXI_PROT_EN_3_CLR, - MT8186_TOP_AXI_PROT_EN_3_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2, - MT8186_TOP_AXI_PROT_EN_3_SET, - MT8186_TOP_AXI_PROT_EN_3_CLR, - MT8186_TOP_AXI_PROT_EN_3_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1, + MT8186_TOP_AXI_PROT_EN_3_SET, + MT8186_TOP_AXI_PROT_EN_3_CLR, + MT8186_TOP_AXI_PROT_EN_3_STA), + BUS_PROT_INFRA_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2, + MT8186_TOP_AXI_PROT_EN_3_SET, + MT8186_TOP_AXI_PROT_EN_3_CLR, + MT8186_TOP_AXI_PROT_EN_3_STA), }, .caps =3D MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP, }, diff --git a/drivers/soc/mediatek/mt8188-pm-domains.h b/drivers/soc/mediate= k/mt8188-pm-domains.h index 0692cb444ed0..aa56ba31327d 100644 --- a/drivers/soc/mediatek/mt8188-pm-domains.h +++ b/drivers/soc/mediatek/mt8188-pm-domains.h @@ -33,31 +33,31 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x178, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP1, - MT8188_TOP_AXI_PROT_EN_SET, - MT8188_TOP_AXI_PROT_EN_CLR, - MT8188_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2, - MT8188_TOP_AXI_PROT_EN_2_SET, - MT8188_TOP_AXI_PROT_EN_2_CLR, - MT8188_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3, - MT8188_TOP_AXI_PROT_EN_1_SET, - MT8188_TOP_AXI_PROT_EN_1_CLR, - MT8188_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4, - MT8188_TOP_AXI_PROT_EN_2_SET, - MT8188_TOP_AXI_PROT_EN_2_CLR, - MT8188_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP5, - MT8188_TOP_AXI_PROT_EN_SET, - MT8188_TOP_AXI_PROT_EN_CLR, - MT8188_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6, - MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, - MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, - MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP1, + MT8188_TOP_AXI_PROT_EN_SET, + MT8188_TOP_AXI_PROT_EN_CLR, + MT8188_TOP_AXI_PROT_EN_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3, + MT8188_TOP_AXI_PROT_EN_1_SET, + MT8188_TOP_AXI_PROT_EN_1_CLR, + MT8188_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP5, + MT8188_TOP_AXI_PROT_EN_SET, + MT8188_TOP_AXI_PROT_EN_CLR, + MT8188_TOP_AXI_PROT_EN_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6, + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, }, @@ -99,15 +99,15 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x178, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0_STEP1, - MT8188_TOP_AXI_PROT_EN_SET, - MT8188_TOP_AXI_PROT_EN_CLR, - MT8188_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2, - MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, - MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, - MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0_STEP1, + MT8188_TOP_AXI_PROT_EN_SET, + MT8188_TOP_AXI_PROT_EN_CLR, + MT8188_TOP_AXI_PROT_EN_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -135,11 +135,11 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_ETHER_STEP1, - MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, - MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, - MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_ETHER_STEP1, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, }, @@ -151,11 +151,11 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_HDMI_TX_STEP1, - MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, - MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, - MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_HDMI_TX_STEP1, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, }, @@ -165,15 +165,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .ctl_offs =3D 0x35C, .pwr_sta_offs =3D 0x16C, .pwr_sta2nd_offs =3D 0x170, - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1, - MT8188_TOP_AXI_PROT_EN_2_SET, - MT8188_TOP_AXI_PROT_EN_2_CLR, - MT8188_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2, - MT8188_TOP_AXI_PROT_EN_2_SET, - MT8188_TOP_AXI_PROT_EN_2_CLR, - MT8188_TOP_AXI_PROT_EN_2_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), }, .caps =3D MTK_SCPD_ALWAYS_ON, }, @@ -185,15 +185,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1, - MT8188_TOP_AXI_PROT_EN_2_SET, - MT8188_TOP_AXI_PROT_EN_2_CLR, - MT8188_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2, - MT8188_TOP_AXI_PROT_EN_2_SET, - MT8188_TOP_AXI_PROT_EN_2_CLR, - MT8188_TOP_AXI_PROT_EN_2_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), }, .caps =3D MTK_SCPD_SRAM_ISO | MTK_SCPD_ALWAYS_ON, }, @@ -205,15 +205,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1, - MT8188_TOP_AXI_PROT_EN_2_SET, - MT8188_TOP_AXI_PROT_EN_2_CLR, - MT8188_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2, - MT8188_TOP_AXI_PROT_EN_2_SET, - MT8188_TOP_AXI_PROT_EN_2_CLR, - MT8188_TOP_AXI_PROT_EN_2_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIV= E_WAKEUP, }, @@ -225,15 +225,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1, - MT8188_TOP_AXI_PROT_EN_2_SET, - MT8188_TOP_AXI_PROT_EN_2_CLR, - MT8188_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2, - MT8188_TOP_AXI_PROT_EN_2_SET, - MT8188_TOP_AXI_PROT_EN_2_CLR, - MT8188_TOP_AXI_PROT_EN_2_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, }, @@ -245,15 +245,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP1, - MT8188_TOP_AXI_PROT_EN_2_SET, - MT8188_TOP_AXI_PROT_EN_2_CLR, - MT8188_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP2, - MT8188_TOP_AXI_PROT_EN_2_SET, - MT8188_TOP_AXI_PROT_EN_2_CLR, - MT8188_TOP_AXI_PROT_EN_2_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP1, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP2, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -265,27 +265,27 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP1, - MT8188_TOP_AXI_PROT_EN_SET, - MT8188_TOP_AXI_PROT_EN_CLR, - MT8188_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2, - MT8188_TOP_AXI_PROT_EN_MM_2_SET, - MT8188_TOP_AXI_PROT_EN_MM_2_CLR, - MT8188_TOP_AXI_PROT_EN_MM_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP3, - MT8188_TOP_AXI_PROT_EN_SET, - MT8188_TOP_AXI_PROT_EN_CLR, - MT8188_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4, - MT8188_TOP_AXI_PROT_EN_MM_2_SET, - MT8188_TOP_AXI_PROT_EN_MM_2_CLR, - MT8188_TOP_AXI_PROT_EN_MM_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0_STEP5, - MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, - MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, - MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP1, + MT8188_TOP_AXI_PROT_EN_SET, + MT8188_TOP_AXI_PROT_EN_CLR, + MT8188_TOP_AXI_PROT_EN_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2, + MT8188_TOP_AXI_PROT_EN_MM_2_SET, + MT8188_TOP_AXI_PROT_EN_MM_2_CLR, + MT8188_TOP_AXI_PROT_EN_MM_2_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP3, + MT8188_TOP_AXI_PROT_EN_SET, + MT8188_TOP_AXI_PROT_EN_CLR, + MT8188_TOP_AXI_PROT_EN_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4, + MT8188_TOP_AXI_PROT_EN_MM_2_SET, + MT8188_TOP_AXI_PROT_EN_MM_2_CLR, + MT8188_TOP_AXI_PROT_EN_MM_2_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0_STEP5, + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA), }, }, [MT8188_POWER_DOMAIN_VDOSYS0] =3D { @@ -296,19 +296,19 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1, - MT8188_TOP_AXI_PROT_EN_MM_SET, - MT8188_TOP_AXI_PROT_EN_MM_CLR, - MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP2, - MT8188_TOP_AXI_PROT_EN_SET, - MT8188_TOP_AXI_PROT_EN_CLR, - MT8188_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0_STEP3, - MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, - MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, - MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1, + MT8188_TOP_AXI_PROT_EN_MM_SET, + MT8188_TOP_AXI_PROT_EN_MM_CLR, + MT8188_TOP_AXI_PROT_EN_MM_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP2, + MT8188_TOP_AXI_PROT_EN_SET, + MT8188_TOP_AXI_PROT_EN_CLR, + MT8188_TOP_AXI_PROT_EN_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0_STEP3, + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA), }, }, [MT8188_POWER_DOMAIN_VDOSYS1] =3D { @@ -319,19 +319,19 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1, - MT8188_TOP_AXI_PROT_EN_MM_SET, - MT8188_TOP_AXI_PROT_EN_MM_CLR, - MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP2, - MT8188_TOP_AXI_PROT_EN_MM_SET, - MT8188_TOP_AXI_PROT_EN_MM_CLR, - MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1_STEP3, - MT8188_TOP_AXI_PROT_EN_MM_2_SET, - MT8188_TOP_AXI_PROT_EN_MM_2_CLR, - MT8188_TOP_AXI_PROT_EN_MM_2_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1, + MT8188_TOP_AXI_PROT_EN_MM_SET, + MT8188_TOP_AXI_PROT_EN_MM_CLR, + MT8188_TOP_AXI_PROT_EN_MM_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP2, + MT8188_TOP_AXI_PROT_EN_MM_SET, + MT8188_TOP_AXI_PROT_EN_MM_CLR, + MT8188_TOP_AXI_PROT_EN_MM_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1_STEP3, + MT8188_TOP_AXI_PROT_EN_MM_2_SET, + MT8188_TOP_AXI_PROT_EN_MM_2_CLR, + MT8188_TOP_AXI_PROT_EN_MM_2_STA), }, }, [MT8188_POWER_DOMAIN_DP_TX] =3D { @@ -342,11 +342,11 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_DP_TX_STEP1, - MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, - MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, - MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_DP_TX_STEP1, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -358,11 +358,11 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_EDP_TX_STEP1, - MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, - MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, - MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_EDP_TX_STEP1, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -374,19 +374,19 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1, - MT8188_TOP_AXI_PROT_EN_MM_SET, - MT8188_TOP_AXI_PROT_EN_MM_CLR, - MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP2, - MT8188_TOP_AXI_PROT_EN_MM_SET, - MT8188_TOP_AXI_PROT_EN_MM_CLR, - MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1_STEP3, - MT8188_TOP_AXI_PROT_EN_MM_2_SET, - MT8188_TOP_AXI_PROT_EN_MM_2_CLR, - MT8188_TOP_AXI_PROT_EN_MM_2_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1, + MT8188_TOP_AXI_PROT_EN_MM_SET, + MT8188_TOP_AXI_PROT_EN_MM_CLR, + MT8188_TOP_AXI_PROT_EN_MM_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP2, + MT8188_TOP_AXI_PROT_EN_MM_SET, + MT8188_TOP_AXI_PROT_EN_MM_CLR, + MT8188_TOP_AXI_PROT_EN_MM_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1_STEP3, + MT8188_TOP_AXI_PROT_EN_MM_2_SET, + MT8188_TOP_AXI_PROT_EN_MM_2_CLR, + MT8188_TOP_AXI_PROT_EN_MM_2_STA), }, }, [MT8188_POWER_DOMAIN_WPE] =3D { @@ -397,15 +397,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP1, - MT8188_TOP_AXI_PROT_EN_MM_2_SET, - MT8188_TOP_AXI_PROT_EN_MM_2_CLR, - MT8188_TOP_AXI_PROT_EN_MM_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP2, - MT8188_TOP_AXI_PROT_EN_MM_2_SET, - MT8188_TOP_AXI_PROT_EN_MM_2_CLR, - MT8188_TOP_AXI_PROT_EN_MM_2_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP1, + MT8188_TOP_AXI_PROT_EN_MM_2_SET, + MT8188_TOP_AXI_PROT_EN_MM_2_CLR, + MT8188_TOP_AXI_PROT_EN_MM_2_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP2, + MT8188_TOP_AXI_PROT_EN_MM_2_SET, + MT8188_TOP_AXI_PROT_EN_MM_2_CLR, + MT8188_TOP_AXI_PROT_EN_MM_2_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -417,15 +417,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STEP1, - MT8188_TOP_AXI_PROT_EN_MM_SET, - MT8188_TOP_AXI_PROT_EN_MM_CLR, - MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2, - MT8188_TOP_AXI_PROT_EN_MM_2_SET, - MT8188_TOP_AXI_PROT_EN_MM_2_CLR, - MT8188_TOP_AXI_PROT_EN_MM_2_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STEP1, + MT8188_TOP_AXI_PROT_EN_MM_SET, + MT8188_TOP_AXI_PROT_EN_MM_CLR, + MT8188_TOP_AXI_PROT_EN_MM_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2, + MT8188_TOP_AXI_PROT_EN_MM_2_SET, + MT8188_TOP_AXI_PROT_EN_MM_2_CLR, + MT8188_TOP_AXI_PROT_EN_MM_2_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -437,15 +437,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP1, - MT8188_TOP_AXI_PROT_EN_MM_SET, - MT8188_TOP_AXI_PROT_EN_MM_CLR, - MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP2, - MT8188_TOP_AXI_PROT_EN_MM_SET, - MT8188_TOP_AXI_PROT_EN_MM_CLR, - MT8188_TOP_AXI_PROT_EN_MM_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP1, + MT8188_TOP_AXI_PROT_EN_MM_SET, + MT8188_TOP_AXI_PROT_EN_MM_CLR, + MT8188_TOP_AXI_PROT_EN_MM_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP2, + MT8188_TOP_AXI_PROT_EN_MM_SET, + MT8188_TOP_AXI_PROT_EN_MM_CLR, + MT8188_TOP_AXI_PROT_EN_MM_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -457,19 +457,19 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP1, - MT8188_TOP_AXI_PROT_EN_MM_SET, - MT8188_TOP_AXI_PROT_EN_MM_CLR, - MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP2, - MT8188_TOP_AXI_PROT_EN_MM_SET, - MT8188_TOP_AXI_PROT_EN_MM_CLR, - MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VENC_STEP3, - MT8188_TOP_AXI_PROT_EN_MM_2_SET, - MT8188_TOP_AXI_PROT_EN_MM_2_CLR, - MT8188_TOP_AXI_PROT_EN_MM_2_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP1, + MT8188_TOP_AXI_PROT_EN_MM_SET, + MT8188_TOP_AXI_PROT_EN_MM_CLR, + MT8188_TOP_AXI_PROT_EN_MM_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP2, + MT8188_TOP_AXI_PROT_EN_MM_SET, + MT8188_TOP_AXI_PROT_EN_MM_CLR, + MT8188_TOP_AXI_PROT_EN_MM_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VENC_STEP3, + MT8188_TOP_AXI_PROT_EN_MM_2_SET, + MT8188_TOP_AXI_PROT_EN_MM_2_CLR, + MT8188_TOP_AXI_PROT_EN_MM_2_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -479,19 +479,19 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .ctl_offs =3D 0x3A4, .pwr_sta_offs =3D 0x16C, .pwr_sta2nd_offs =3D 0x170, - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1, - MT8188_TOP_AXI_PROT_EN_MM_SET, - MT8188_TOP_AXI_PROT_EN_MM_CLR, - MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP2, - MT8188_TOP_AXI_PROT_EN_MM_SET, - MT8188_TOP_AXI_PROT_EN_MM_CLR, - MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCORE_STEP3, - MT8188_TOP_AXI_PROT_EN_MM_2_SET, - MT8188_TOP_AXI_PROT_EN_MM_2_CLR, - MT8188_TOP_AXI_PROT_EN_MM_2_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1, + MT8188_TOP_AXI_PROT_EN_MM_SET, + MT8188_TOP_AXI_PROT_EN_MM_CLR, + MT8188_TOP_AXI_PROT_EN_MM_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP2, + MT8188_TOP_AXI_PROT_EN_MM_SET, + MT8188_TOP_AXI_PROT_EN_MM_CLR, + MT8188_TOP_AXI_PROT_EN_MM_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCORE_STEP3, + MT8188_TOP_AXI_PROT_EN_MM_2_SET, + MT8188_TOP_AXI_PROT_EN_MM_2_CLR, + MT8188_TOP_AXI_PROT_EN_MM_2_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, }, @@ -503,15 +503,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1, - MT8188_TOP_AXI_PROT_EN_MM_2_SET, - MT8188_TOP_AXI_PROT_EN_MM_2_CLR, - MT8188_TOP_AXI_PROT_EN_MM_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2, - MT8188_TOP_AXI_PROT_EN_MM_2_SET, - MT8188_TOP_AXI_PROT_EN_MM_2_CLR, - MT8188_TOP_AXI_PROT_EN_MM_2_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1, + MT8188_TOP_AXI_PROT_EN_MM_2_SET, + MT8188_TOP_AXI_PROT_EN_MM_2_CLR, + MT8188_TOP_AXI_PROT_EN_MM_2_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2, + MT8188_TOP_AXI_PROT_EN_MM_2_SET, + MT8188_TOP_AXI_PROT_EN_MM_2_CLR, + MT8188_TOP_AXI_PROT_EN_MM_2_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -541,27 +541,27 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .ctl_offs =3D 0x3A0, .pwr_sta_offs =3D 0x16C, .pwr_sta2nd_offs =3D 0x170, - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1, - MT8188_TOP_AXI_PROT_EN_MM_SET, - MT8188_TOP_AXI_PROT_EN_MM_CLR, - MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2, - MT8188_TOP_AXI_PROT_EN_2_SET, - MT8188_TOP_AXI_PROT_EN_2_CLR, - MT8188_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_STEP3, - MT8188_TOP_AXI_PROT_EN_1_SET, - MT8188_TOP_AXI_PROT_EN_1_CLR, - MT8188_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP4, - MT8188_TOP_AXI_PROT_EN_MM_SET, - MT8188_TOP_AXI_PROT_EN_MM_CLR, - MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCORE_STEP5, - MT8188_TOP_AXI_PROT_EN_MM_2_SET, - MT8188_TOP_AXI_PROT_EN_MM_2_CLR, - MT8188_TOP_AXI_PROT_EN_MM_2_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1, + MT8188_TOP_AXI_PROT_EN_MM_SET, + MT8188_TOP_AXI_PROT_EN_MM_CLR, + MT8188_TOP_AXI_PROT_EN_MM_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_STEP3, + MT8188_TOP_AXI_PROT_EN_1_SET, + MT8188_TOP_AXI_PROT_EN_1_CLR, + MT8188_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP4, + MT8188_TOP_AXI_PROT_EN_MM_SET, + MT8188_TOP_AXI_PROT_EN_MM_CLR, + MT8188_TOP_AXI_PROT_EN_MM_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCORE_STEP5, + MT8188_TOP_AXI_PROT_EN_MM_2_SET, + MT8188_TOP_AXI_PROT_EN_MM_2_CLR, + MT8188_TOP_AXI_PROT_EN_MM_2_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, }, @@ -573,23 +573,23 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1, - MT8188_TOP_AXI_PROT_EN_MM_2_SET, - MT8188_TOP_AXI_PROT_EN_MM_2_CLR, - MT8188_TOP_AXI_PROT_EN_MM_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP2, - MT8188_TOP_AXI_PROT_EN_2_SET, - MT8188_TOP_AXI_PROT_EN_2_CLR, - MT8188_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3, - MT8188_TOP_AXI_PROT_EN_MM_2_SET, - MT8188_TOP_AXI_PROT_EN_MM_2_CLR, - MT8188_TOP_AXI_PROT_EN_MM_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP4, - MT8188_TOP_AXI_PROT_EN_2_SET, - MT8188_TOP_AXI_PROT_EN_2_CLR, - MT8188_TOP_AXI_PROT_EN_2_STA), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1, + MT8188_TOP_AXI_PROT_EN_MM_2_SET, + MT8188_TOP_AXI_PROT_EN_MM_2_CLR, + MT8188_TOP_AXI_PROT_EN_MM_2_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP2, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3, + MT8188_TOP_AXI_PROT_EN_MM_2_SET, + MT8188_TOP_AXI_PROT_EN_MM_2_CLR, + MT8188_TOP_AXI_PROT_EN_MM_2_STA), + BUS_PROT_INFRA_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP4, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, diff --git a/drivers/soc/mediatek/mt8192-pm-domains.h b/drivers/soc/mediate= k/mt8192-pm-domains.h index b97b2051920f..17ee852cfc26 100644 --- a/drivers/soc/mediatek/mt8192-pm-domains.h +++ b/drivers/soc/mediatek/mt8192-pm-domains.h @@ -19,11 +19,11 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8192[] =3D { .pwr_sta2nd_offs =3D 0x0170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_AUDIO, - MT8192_TOP_AXI_PROT_EN_2_SET, - MT8192_TOP_AXI_PROT_EN_2_CLR, - MT8192_TOP_AXI_PROT_EN_2_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_2_AUDIO, + MT8192_TOP_AXI_PROT_EN_2_SET, + MT8192_TOP_AXI_PROT_EN_2_CLR, + MT8192_TOP_AXI_PROT_EN_2_STA1), }, }, [MT8192_POWER_DOMAIN_CONN] =3D { @@ -34,19 +34,19 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8192[] =3D { .pwr_sta2nd_offs =3D 0x0170, .sram_pdn_bits =3D 0, .sram_pdn_ack_bits =3D 0, - .bp_infracfg =3D { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN, - MT8192_TOP_AXI_PROT_EN_SET, - MT8192_TOP_AXI_PROT_EN_CLR, - MT8192_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN_2ND, - MT8192_TOP_AXI_PROT_EN_SET, - MT8192_TOP_AXI_PROT_EN_CLR, - MT8192_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CONN, - MT8192_TOP_AXI_PROT_EN_1_SET, - MT8192_TOP_AXI_PROT_EN_1_CLR, - MT8192_TOP_AXI_PROT_EN_1_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_CONN, + MT8192_TOP_AXI_PROT_EN_SET, + MT8192_TOP_AXI_PROT_EN_CLR, + MT8192_TOP_AXI_PROT_EN_STA1), + BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_CONN_2ND, + MT8192_TOP_AXI_PROT_EN_SET, + MT8192_TOP_AXI_PROT_EN_CLR, + MT8192_TOP_AXI_PROT_EN_STA1), + BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_1_CONN, + MT8192_TOP_AXI_PROT_EN_1_SET, + MT8192_TOP_AXI_PROT_EN_1_CLR, + MT8192_TOP_AXI_PROT_EN_1_STA1), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -68,23 +68,23 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8192[] =3D { .pwr_sta2nd_offs =3D 0x0170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_MFG1, - MT8192_TOP_AXI_PROT_EN_1_SET, - MT8192_TOP_AXI_PROT_EN_1_CLR, - MT8192_TOP_AXI_PROT_EN_1_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1, - MT8192_TOP_AXI_PROT_EN_2_SET, - MT8192_TOP_AXI_PROT_EN_2_CLR, - MT8192_TOP_AXI_PROT_EN_2_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MFG1, - MT8192_TOP_AXI_PROT_EN_SET, - MT8192_TOP_AXI_PROT_EN_CLR, - MT8192_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND, - MT8192_TOP_AXI_PROT_EN_2_SET, - MT8192_TOP_AXI_PROT_EN_2_CLR, - MT8192_TOP_AXI_PROT_EN_2_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_1_MFG1, + MT8192_TOP_AXI_PROT_EN_1_SET, + MT8192_TOP_AXI_PROT_EN_1_CLR, + MT8192_TOP_AXI_PROT_EN_1_STA1), + BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1, + MT8192_TOP_AXI_PROT_EN_2_SET, + MT8192_TOP_AXI_PROT_EN_2_CLR, + MT8192_TOP_AXI_PROT_EN_2_STA1), + BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MFG1, + MT8192_TOP_AXI_PROT_EN_SET, + MT8192_TOP_AXI_PROT_EN_CLR, + MT8192_TOP_AXI_PROT_EN_STA1), + BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND, + MT8192_TOP_AXI_PROT_EN_2_SET, + MT8192_TOP_AXI_PROT_EN_2_CLR, + MT8192_TOP_AXI_PROT_EN_2_STA1), }, .caps =3D MTK_SCPD_DOMAIN_SUPPLY, }, @@ -141,27 +141,27 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8192[] =3D { .pwr_sta2nd_offs =3D 0x0170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_DISP, - MT8192_TOP_AXI_PROT_EN_MM_SET, - MT8192_TOP_AXI_PROT_EN_MM_CLR, - MT8192_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_2_DISP, - MT8192_TOP_AXI_PROT_EN_MM_2_SET, - MT8192_TOP_AXI_PROT_EN_MM_2_CLR, - MT8192_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_DISP, - MT8192_TOP_AXI_PROT_EN_SET, - MT8192_TOP_AXI_PROT_EN_CLR, - MT8192_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND, - MT8192_TOP_AXI_PROT_EN_MM_SET, - MT8192_TOP_AXI_PROT_EN_MM_CLR, - MT8192_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND, - MT8192_TOP_AXI_PROT_EN_MM_2_SET, - MT8192_TOP_AXI_PROT_EN_MM_2_CLR, - MT8192_TOP_AXI_PROT_EN_MM_2_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_DISP, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_INFRA_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_2_DISP, + MT8192_TOP_AXI_PROT_EN_MM_2_SET, + MT8192_TOP_AXI_PROT_EN_MM_2_CLR, + MT8192_TOP_AXI_PROT_EN_MM_2_STA1), + BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_DISP, + MT8192_TOP_AXI_PROT_EN_SET, + MT8192_TOP_AXI_PROT_EN_CLR, + MT8192_TOP_AXI_PROT_EN_STA1), + BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND, + MT8192_TOP_AXI_PROT_EN_MM_2_SET, + MT8192_TOP_AXI_PROT_EN_MM_2_CLR, + MT8192_TOP_AXI_PROT_EN_MM_2_STA1), }, }, [MT8192_POWER_DOMAIN_IPE] =3D { @@ -172,15 +172,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8192[] =3D { .pwr_sta2nd_offs =3D 0x0170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE, - MT8192_TOP_AXI_PROT_EN_MM_SET, - MT8192_TOP_AXI_PROT_EN_MM_CLR, - MT8192_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND, - MT8192_TOP_AXI_PROT_EN_MM_SET, - MT8192_TOP_AXI_PROT_EN_MM_CLR, - MT8192_TOP_AXI_PROT_EN_MM_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), }, }, [MT8192_POWER_DOMAIN_ISP] =3D { @@ -191,15 +191,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8192[] =3D { .pwr_sta2nd_offs =3D 0x0170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP, - MT8192_TOP_AXI_PROT_EN_MM_2_SET, - MT8192_TOP_AXI_PROT_EN_MM_2_CLR, - MT8192_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND, - MT8192_TOP_AXI_PROT_EN_MM_2_SET, - MT8192_TOP_AXI_PROT_EN_MM_2_CLR, - MT8192_TOP_AXI_PROT_EN_MM_2_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP, + MT8192_TOP_AXI_PROT_EN_MM_2_SET, + MT8192_TOP_AXI_PROT_EN_MM_2_CLR, + MT8192_TOP_AXI_PROT_EN_MM_2_STA1), + BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND, + MT8192_TOP_AXI_PROT_EN_MM_2_SET, + MT8192_TOP_AXI_PROT_EN_MM_2_CLR, + MT8192_TOP_AXI_PROT_EN_MM_2_STA1), }, }, [MT8192_POWER_DOMAIN_ISP2] =3D { @@ -210,15 +210,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8192[] =3D { .pwr_sta2nd_offs =3D 0x0170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2, - MT8192_TOP_AXI_PROT_EN_MM_SET, - MT8192_TOP_AXI_PROT_EN_MM_CLR, - MT8192_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND, - MT8192_TOP_AXI_PROT_EN_MM_SET, - MT8192_TOP_AXI_PROT_EN_MM_CLR, - MT8192_TOP_AXI_PROT_EN_MM_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), }, }, [MT8192_POWER_DOMAIN_MDP] =3D { @@ -229,15 +229,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8192[] =3D { .pwr_sta2nd_offs =3D 0x0170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP, - MT8192_TOP_AXI_PROT_EN_MM_2_SET, - MT8192_TOP_AXI_PROT_EN_MM_2_CLR, - MT8192_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND, - MT8192_TOP_AXI_PROT_EN_MM_2_SET, - MT8192_TOP_AXI_PROT_EN_MM_2_CLR, - MT8192_TOP_AXI_PROT_EN_MM_2_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP, + MT8192_TOP_AXI_PROT_EN_MM_2_SET, + MT8192_TOP_AXI_PROT_EN_MM_2_CLR, + MT8192_TOP_AXI_PROT_EN_MM_2_STA1), + BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND, + MT8192_TOP_AXI_PROT_EN_MM_2_SET, + MT8192_TOP_AXI_PROT_EN_MM_2_CLR, + MT8192_TOP_AXI_PROT_EN_MM_2_STA1), }, }, [MT8192_POWER_DOMAIN_VENC] =3D { @@ -248,15 +248,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8192[] =3D { .pwr_sta2nd_offs =3D 0x0170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC, - MT8192_TOP_AXI_PROT_EN_MM_SET, - MT8192_TOP_AXI_PROT_EN_MM_CLR, - MT8192_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND, - MT8192_TOP_AXI_PROT_EN_MM_SET, - MT8192_TOP_AXI_PROT_EN_MM_CLR, - MT8192_TOP_AXI_PROT_EN_MM_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), }, }, [MT8192_POWER_DOMAIN_VDEC] =3D { @@ -267,15 +267,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8192[] =3D { .pwr_sta2nd_offs =3D 0x0170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC, - MT8192_TOP_AXI_PROT_EN_MM_SET, - MT8192_TOP_AXI_PROT_EN_MM_CLR, - MT8192_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND, - MT8192_TOP_AXI_PROT_EN_MM_SET, - MT8192_TOP_AXI_PROT_EN_MM_CLR, - MT8192_TOP_AXI_PROT_EN_MM_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), }, }, [MT8192_POWER_DOMAIN_VDEC2] =3D { @@ -295,27 +295,27 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8192[] =3D { .pwr_sta2nd_offs =3D 0x0170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_CAM, - MT8192_TOP_AXI_PROT_EN_2_SET, - MT8192_TOP_AXI_PROT_EN_2_CLR, - MT8192_TOP_AXI_PROT_EN_2_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM, - MT8192_TOP_AXI_PROT_EN_MM_SET, - MT8192_TOP_AXI_PROT_EN_MM_CLR, - MT8192_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CAM, - MT8192_TOP_AXI_PROT_EN_1_SET, - MT8192_TOP_AXI_PROT_EN_1_CLR, - MT8192_TOP_AXI_PROT_EN_1_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND, - MT8192_TOP_AXI_PROT_EN_MM_SET, - MT8192_TOP_AXI_PROT_EN_MM_CLR, - MT8192_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_VDNR_CAM, - MT8192_TOP_AXI_PROT_EN_VDNR_SET, - MT8192_TOP_AXI_PROT_EN_VDNR_CLR, - MT8192_TOP_AXI_PROT_EN_VDNR_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_2_CAM, + MT8192_TOP_AXI_PROT_EN_2_SET, + MT8192_TOP_AXI_PROT_EN_2_CLR, + MT8192_TOP_AXI_PROT_EN_2_STA1), + BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_1_CAM, + MT8192_TOP_AXI_PROT_EN_1_SET, + MT8192_TOP_AXI_PROT_EN_1_CLR, + MT8192_TOP_AXI_PROT_EN_1_STA1), + BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_INFRA_WR(MT8192_TOP_AXI_PROT_EN_VDNR_CAM, + MT8192_TOP_AXI_PROT_EN_VDNR_SET, + MT8192_TOP_AXI_PROT_EN_VDNR_CLR, + MT8192_TOP_AXI_PROT_EN_VDNR_STA1), }, }, [MT8192_POWER_DOMAIN_CAM_RAWA] =3D { diff --git a/drivers/soc/mediatek/mt8195-pm-domains.h b/drivers/soc/mediate= k/mt8195-pm-domains.h index d7387ea1b9c9..8360d79bc1b4 100644 --- a/drivers/soc/mediatek/mt8195-pm-domains.h +++ b/drivers/soc/mediatek/mt8195-pm-domains.h @@ -23,15 +23,15 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x178, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0, - MT8195_TOP_AXI_PROT_EN_VDNR_SET, - MT8195_TOP_AXI_PROT_EN_VDNR_CLR, - MT8195_TOP_AXI_PROT_EN_VDNR_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0, - MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, - MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, - MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0, + MT8195_TOP_AXI_PROT_EN_VDNR_SET, + MT8195_TOP_AXI_PROT_EN_VDNR_CLR, + MT8195_TOP_AXI_PROT_EN_VDNR_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0, + MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, + MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, + MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), }, }, [MT8195_POWER_DOMAIN_PCIE_MAC_P1] =3D { @@ -42,15 +42,15 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x178, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1, - MT8195_TOP_AXI_PROT_EN_VDNR_SET, - MT8195_TOP_AXI_PROT_EN_VDNR_CLR, - MT8195_TOP_AXI_PROT_EN_VDNR_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1, - MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, - MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, - MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1, + MT8195_TOP_AXI_PROT_EN_VDNR_SET, + MT8195_TOP_AXI_PROT_EN_VDNR_CLR, + MT8195_TOP_AXI_PROT_EN_VDNR_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1, + MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, + MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, + MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), }, }, [MT8195_POWER_DOMAIN_PCIE_PHY] =3D { @@ -95,11 +95,11 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_ADSP, - MT8195_TOP_AXI_PROT_EN_2_SET, - MT8195_TOP_AXI_PROT_EN_2_CLR, - MT8195_TOP_AXI_PROT_EN_2_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_2_ADSP, + MT8195_TOP_AXI_PROT_EN_2_SET, + MT8195_TOP_AXI_PROT_EN_2_CLR, + MT8195_TOP_AXI_PROT_EN_2_STA1), }, .caps =3D MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP, }, @@ -111,11 +111,11 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_AUDIO, - MT8195_TOP_AXI_PROT_EN_2_SET, - MT8195_TOP_AXI_PROT_EN_2_CLR, - MT8195_TOP_AXI_PROT_EN_2_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_2_AUDIO, + MT8195_TOP_AXI_PROT_EN_2_SET, + MT8195_TOP_AXI_PROT_EN_2_CLR, + MT8195_TOP_AXI_PROT_EN_2_STA1), }, }, [MT8195_POWER_DOMAIN_MFG0] =3D { @@ -136,31 +136,31 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x178, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1, - MT8195_TOP_AXI_PROT_EN_SET, - MT8195_TOP_AXI_PROT_EN_CLR, - MT8195_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1, - MT8195_TOP_AXI_PROT_EN_2_SET, - MT8195_TOP_AXI_PROT_EN_2_CLR, - MT8195_TOP_AXI_PROT_EN_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_MFG1, - MT8195_TOP_AXI_PROT_EN_1_SET, - MT8195_TOP_AXI_PROT_EN_1_CLR, - MT8195_TOP_AXI_PROT_EN_1_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND, - MT8195_TOP_AXI_PROT_EN_2_SET, - MT8195_TOP_AXI_PROT_EN_2_CLR, - MT8195_TOP_AXI_PROT_EN_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1_2ND, - MT8195_TOP_AXI_PROT_EN_SET, - MT8195_TOP_AXI_PROT_EN_CLR, - MT8195_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1, - MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, - MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, - MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MFG1, + MT8195_TOP_AXI_PROT_EN_SET, + MT8195_TOP_AXI_PROT_EN_CLR, + MT8195_TOP_AXI_PROT_EN_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1, + MT8195_TOP_AXI_PROT_EN_2_SET, + MT8195_TOP_AXI_PROT_EN_2_CLR, + MT8195_TOP_AXI_PROT_EN_2_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_1_MFG1, + MT8195_TOP_AXI_PROT_EN_1_SET, + MT8195_TOP_AXI_PROT_EN_1_CLR, + MT8195_TOP_AXI_PROT_EN_1_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND, + MT8195_TOP_AXI_PROT_EN_2_SET, + MT8195_TOP_AXI_PROT_EN_2_CLR, + MT8195_TOP_AXI_PROT_EN_2_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MFG1_2ND, + MT8195_TOP_AXI_PROT_EN_SET, + MT8195_TOP_AXI_PROT_EN_CLR, + MT8195_TOP_AXI_PROT_EN_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, }, @@ -222,27 +222,27 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0, - MT8195_TOP_AXI_PROT_EN_SET, - MT8195_TOP_AXI_PROT_EN_CLR, - MT8195_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0, - MT8195_TOP_AXI_PROT_EN_MM_2_SET, - MT8195_TOP_AXI_PROT_EN_MM_2_CLR, - MT8195_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND, - MT8195_TOP_AXI_PROT_EN_SET, - MT8195_TOP_AXI_PROT_EN_CLR, - MT8195_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND, - MT8195_TOP_AXI_PROT_EN_MM_2_SET, - MT8195_TOP_AXI_PROT_EN_MM_2_CLR, - MT8195_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0, - MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, - MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, - MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0, + MT8195_TOP_AXI_PROT_EN_SET, + MT8195_TOP_AXI_PROT_EN_CLR, + MT8195_TOP_AXI_PROT_EN_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND, + MT8195_TOP_AXI_PROT_EN_SET, + MT8195_TOP_AXI_PROT_EN_CLR, + MT8195_TOP_AXI_PROT_EN_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), }, }, [MT8195_POWER_DOMAIN_VDOSYS0] =3D { @@ -253,19 +253,19 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0, - MT8195_TOP_AXI_PROT_EN_MM_SET, - MT8195_TOP_AXI_PROT_EN_MM_CLR, - MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDOSYS0, - MT8195_TOP_AXI_PROT_EN_SET, - MT8195_TOP_AXI_PROT_EN_CLR, - MT8195_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0, - MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, - MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, - MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_VDOSYS0, + MT8195_TOP_AXI_PROT_EN_SET, + MT8195_TOP_AXI_PROT_EN_CLR, + MT8195_TOP_AXI_PROT_EN_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), }, }, [MT8195_POWER_DOMAIN_VPPSYS1] =3D { @@ -276,19 +276,19 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1, - MT8195_TOP_AXI_PROT_EN_MM_SET, - MT8195_TOP_AXI_PROT_EN_MM_CLR, - MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND, - MT8195_TOP_AXI_PROT_EN_MM_SET, - MT8195_TOP_AXI_PROT_EN_MM_CLR, - MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1, - MT8195_TOP_AXI_PROT_EN_MM_2_SET, - MT8195_TOP_AXI_PROT_EN_MM_2_CLR, - MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), }, }, [MT8195_POWER_DOMAIN_VDOSYS1] =3D { @@ -299,19 +299,19 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1, - MT8195_TOP_AXI_PROT_EN_MM_SET, - MT8195_TOP_AXI_PROT_EN_MM_CLR, - MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND, - MT8195_TOP_AXI_PROT_EN_MM_SET, - MT8195_TOP_AXI_PROT_EN_MM_CLR, - MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1, - MT8195_TOP_AXI_PROT_EN_MM_2_SET, - MT8195_TOP_AXI_PROT_EN_MM_2_CLR, - MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), }, }, [MT8195_POWER_DOMAIN_DP_TX] =3D { @@ -322,11 +322,11 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX, - MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, - MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, - MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX, + MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, + MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, + MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -338,11 +338,11 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX, - MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, - MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, - MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX, + MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, + MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, + MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -364,19 +364,19 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS, - MT8195_TOP_AXI_PROT_EN_MM_2_SET, - MT8195_TOP_AXI_PROT_EN_MM_2_CLR, - MT8195_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_WPESYS, - MT8195_TOP_AXI_PROT_EN_MM_SET, - MT8195_TOP_AXI_PROT_EN_MM_CLR, - MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND, - MT8195_TOP_AXI_PROT_EN_MM_2_SET, - MT8195_TOP_AXI_PROT_EN_MM_2_CLR, - MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_WPESYS, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), }, }, [MT8195_POWER_DOMAIN_VDEC0] =3D { @@ -387,23 +387,23 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0, - MT8195_TOP_AXI_PROT_EN_MM_SET, - MT8195_TOP_AXI_PROT_EN_MM_CLR, - MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0, - MT8195_TOP_AXI_PROT_EN_MM_2_SET, - MT8195_TOP_AXI_PROT_EN_MM_2_CLR, - MT8195_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND, - MT8195_TOP_AXI_PROT_EN_MM_SET, - MT8195_TOP_AXI_PROT_EN_MM_CLR, - MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND, - MT8195_TOP_AXI_PROT_EN_MM_2_SET, - MT8195_TOP_AXI_PROT_EN_MM_2_CLR, - MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -415,15 +415,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1, - MT8195_TOP_AXI_PROT_EN_MM_SET, - MT8195_TOP_AXI_PROT_EN_MM_CLR, - MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND, - MT8195_TOP_AXI_PROT_EN_MM_SET, - MT8195_TOP_AXI_PROT_EN_MM_CLR, - MT8195_TOP_AXI_PROT_EN_MM_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -435,15 +435,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2, - MT8195_TOP_AXI_PROT_EN_MM_2_SET, - MT8195_TOP_AXI_PROT_EN_MM_2_CLR, - MT8195_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND, - MT8195_TOP_AXI_PROT_EN_MM_2_SET, - MT8195_TOP_AXI_PROT_EN_MM_2_CLR, - MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -455,19 +455,19 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC, - MT8195_TOP_AXI_PROT_EN_MM_SET, - MT8195_TOP_AXI_PROT_EN_MM_CLR, - MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND, - MT8195_TOP_AXI_PROT_EN_MM_SET, - MT8195_TOP_AXI_PROT_EN_MM_CLR, - MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC, - MT8195_TOP_AXI_PROT_EN_MM_2_SET, - MT8195_TOP_AXI_PROT_EN_MM_2_CLR, - MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -479,15 +479,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1, - MT8195_TOP_AXI_PROT_EN_MM_SET, - MT8195_TOP_AXI_PROT_EN_MM_CLR, - MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1, - MT8195_TOP_AXI_PROT_EN_MM_2_SET, - MT8195_TOP_AXI_PROT_EN_MM_2_CLR, - MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -499,15 +499,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG, - MT8195_TOP_AXI_PROT_EN_MM_SET, - MT8195_TOP_AXI_PROT_EN_MM_CLR, - MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND, - MT8195_TOP_AXI_PROT_EN_MM_SET, - MT8195_TOP_AXI_PROT_EN_MM_CLR, - MT8195_TOP_AXI_PROT_EN_MM_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -529,15 +529,15 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IPE, - MT8195_TOP_AXI_PROT_EN_MM_SET, - MT8195_TOP_AXI_PROT_EN_MM_CLR, - MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_IPE, - MT8195_TOP_AXI_PROT_EN_MM_2_SET, - MT8195_TOP_AXI_PROT_EN_MM_2_CLR, - MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_IPE, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_IPE, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -549,27 +549,27 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_CAM, - MT8195_TOP_AXI_PROT_EN_2_SET, - MT8195_TOP_AXI_PROT_EN_2_CLR, - MT8195_TOP_AXI_PROT_EN_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM, - MT8195_TOP_AXI_PROT_EN_MM_SET, - MT8195_TOP_AXI_PROT_EN_MM_CLR, - MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_CAM, - MT8195_TOP_AXI_PROT_EN_1_SET, - MT8195_TOP_AXI_PROT_EN_1_CLR, - MT8195_TOP_AXI_PROT_EN_1_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND, - MT8195_TOP_AXI_PROT_EN_MM_SET, - MT8195_TOP_AXI_PROT_EN_MM_CLR, - MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_CAM, - MT8195_TOP_AXI_PROT_EN_MM_2_SET, - MT8195_TOP_AXI_PROT_EN_MM_2_CLR, - MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + .bp_cfg =3D { + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_2_CAM, + MT8195_TOP_AXI_PROT_EN_2_SET, + MT8195_TOP_AXI_PROT_EN_2_CLR, + MT8195_TOP_AXI_PROT_EN_2_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_1_CAM, + MT8195_TOP_AXI_PROT_EN_1_SET, + MT8195_TOP_AXI_PROT_EN_1_CLR, + MT8195_TOP_AXI_PROT_EN_1_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_INFRA_WR(MT8195_TOP_AXI_PROT_EN_MM_2_CAM, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index 69dc24a73ce9..3cdf62c0b6bd 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -118,9 +118,19 @@ static int scpsys_sram_disable(struct scpsys_domain *p= d) MTK_POLL_TIMEOUT); } =20 -static int scpsys_bus_protect_clear(const struct scpsys_bus_prot_data *bpd, - struct regmap *regmap) +static struct regmap *scpsys_bus_protect_get_regmap(struct scpsys_domain *= pd, + const struct scpsys_bus_prot_data *bpd) { + if (bpd->flags & BUS_PROT_COMPONENT_SMI) + return pd->smi; + else + return pd->infracfg; +} + +static int scpsys_bus_protect_clear(struct scpsys_domain *pd, + const struct scpsys_bus_prot_data *bpd) +{ + struct regmap *regmap =3D scpsys_bus_protect_get_regmap(pd, bpd); u32 val; u32 sta_mask =3D bpd->bus_prot_sta_mask; =20 @@ -137,9 +147,10 @@ static int scpsys_bus_protect_clear(const struct scpsy= s_bus_prot_data *bpd, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); } =20 -static int scpsys_bus_protect_set(const struct scpsys_bus_prot_data *bpd, - struct regmap *regmap) +static int scpsys_bus_protect_set(struct scpsys_domain *pd, + const struct scpsys_bus_prot_data *bpd) { + struct regmap *regmap =3D scpsys_bus_protect_get_regmap(pd, bpd); u32 val; u32 sta_mask =3D bpd->bus_prot_sta_mask; =20 @@ -153,15 +164,16 @@ static int scpsys_bus_protect_set(const struct scpsys= _bus_prot_data *bpd, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); } =20 -static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *b= pd, struct regmap *regmap) +static int scpsys_bus_protect_enable(struct scpsys_domain *pd) { - int i, ret; + for (int i =3D 0; i < SPM_MAX_BUS_PROT_DATA; i++) { + const struct scpsys_bus_prot_data *bpd =3D &pd->data->bp_cfg[i]; + int ret; =20 - for (i =3D 0; i < SPM_MAX_BUS_PROT_DATA; i++) { - if (!bpd[i].bus_prot_set_clr_mask) + if (!bpd->bus_prot_set_clr_mask) break; =20 - ret =3D scpsys_bus_protect_set(&bpd[i], regmap); + ret =3D scpsys_bus_protect_set(pd, bpd); if (ret) return ret; } @@ -169,27 +181,16 @@ static int _scpsys_bus_protect_enable(const struct sc= psys_bus_prot_data *bpd, st return 0; } =20 -static int scpsys_bus_protect_enable(struct scpsys_domain *pd) -{ - int ret; - - ret =3D _scpsys_bus_protect_enable(pd->data->bp_infracfg, pd->infracfg); - if (ret) - return ret; - - return _scpsys_bus_protect_enable(pd->data->bp_smi, pd->smi); -} - -static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *= bpd, - struct regmap *regmap) +static int scpsys_bus_protect_disable(struct scpsys_domain *pd) { - int i, ret; + for (int i =3D SPM_MAX_BUS_PROT_DATA - 1; i >=3D 0; i--) { + const struct scpsys_bus_prot_data *bpd =3D &pd->data->bp_cfg[i]; + int ret; =20 - for (i =3D SPM_MAX_BUS_PROT_DATA - 1; i >=3D 0; i--) { - if (!bpd[i].bus_prot_set_clr_mask) + if (!bpd->bus_prot_set_clr_mask) continue; =20 - ret =3D scpsys_bus_protect_clear(&bpd[i], regmap); + ret =3D scpsys_bus_protect_clear(pd, bpd); if (ret) return ret; } @@ -197,17 +198,6 @@ static int _scpsys_bus_protect_disable(const struct sc= psys_bus_prot_data *bpd, return 0; } =20 -static int scpsys_bus_protect_disable(struct scpsys_domain *pd) -{ - int ret; - - ret =3D _scpsys_bus_protect_disable(pd->data->bp_smi, pd->smi); - if (ret) - return ret; - - return _scpsys_bus_protect_disable(pd->data->bp_infracfg, pd->infracfg); -} - static int scpsys_regulator_enable(struct regulator *supply) { return supply ? regulator_enable(supply) : 0; diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/m= tk-pm-domains.h index 4b6ae56e7c95..356788263db2 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -45,6 +45,8 @@ enum scpsys_bus_prot_flags { BUS_PROT_REG_UPDATE =3D BIT(1), BUS_PROT_IGNORE_CLR_ACK =3D BIT(2), + BUS_PROT_COMPONENT_INFRA =3D BIT(3), + BUS_PROT_COMPONENT_SMI =3D BIT(4), }; =20 #define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \ @@ -56,17 +58,30 @@ enum scpsys_bus_prot_flags { .flags =3D _flags \ } =20 -#define BUS_PROT_WR(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _mask, _sta, 0) +#define BUS_PROT_INFRA_WR(_mask, _set, _clr, _sta) \ + _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_COMPONENT_INFRA) =20 -#define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_IGNORE_CLR_ACK) +#define BUS_PROT_INFRA_WR_IGN(_mask, _set, _clr, _sta) \ + _BUS_PROT(_mask, _set, _clr, _mask, _sta, \ + BUS_PROT_COMPONENT_INFRA | BUS_PROT_IGNORE_CLR_ACK) =20 -#define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_REG_UPDATE) +#define BUS_PROT_INFRA_UPDATE(_mask, _set, _clr, _sta) \ + _BUS_PROT(_mask, _set, _clr, _mask, _sta, \ + BUS_PROT_COMPONENT_INFRA | BUS_PROT_REG_UPDATE) =20 -#define BUS_PROT_UPDATE_TOPAXI(_mask) \ - BUS_PROT_UPDATE(_mask, \ +#define BUS_PROT_SMI_WR(_mask, _set, _clr, _sta) \ + _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_COMPONENT_SMI) + +#define BUS_PROT_SMI_WR_IGN(_mask, _set, _clr, _sta) \ + _BUS_PROT(_mask, _set, _clr, _mask, _sta, \ + BUS_PROT_COMPONENT_SMI | BUS_PROT_IGNORE_CLR_ACK) + +#define BUS_PROT_SMI_UPDATE(_mask, _set, _clr, _sta) \ + _BUS_PROT(_mask, _set, _clr, _mask, _sta, \ + BUS_PROT_COMPONENT_SMI | BUS_PROT_REG_UPDATE) + +#define BUS_PROT_INFRA_UPDATE_TOPAXI(_mask) \ + BUS_PROT_INFRA_UPDATE(_mask, \ INFRA_TOPAXI_PROTECTEN, \ INFRA_TOPAXI_PROTECTEN, \ INFRA_TOPAXI_PROTECTSTA1) @@ -90,8 +105,7 @@ struct scpsys_bus_prot_data { * @ext_buck_iso_offs: The offset for external buck isolation * @ext_buck_iso_mask: The mask for external buck isolation * @caps: The flag for active wake-up action. - * @bp_infracfg: bus protection for infracfg subsystem - * @bp_smi: bus protection for smi subsystem + * @bp_cfg: bus protection configuration for any subsystem */ struct scpsys_domain_data { const char *name; @@ -102,8 +116,7 @@ struct scpsys_domain_data { int ext_buck_iso_offs; u32 ext_buck_iso_mask; u8 caps; - const struct scpsys_bus_prot_data bp_infracfg[SPM_MAX_BUS_PROT_DATA]; - const struct scpsys_bus_prot_data bp_smi[SPM_MAX_BUS_PROT_DATA]; + const struct scpsys_bus_prot_data bp_cfg[SPM_MAX_BUS_PROT_DATA]; int pwr_sta_offs; int pwr_sta2nd_offs; }; --=20 2.40.1 From nobody Thu Nov 14 05:48:50 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CF12EB64DB for ; Mon, 19 Jun 2023 08:55:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231294AbjFSIz6 (ORCPT ); Mon, 19 Jun 2023 04:55:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57798 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231407AbjFSIzD (ORCPT ); Mon, 19 Jun 2023 04:55:03 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB67110CE for ; Mon, 19 Jun 2023 01:54:19 -0700 (PDT) Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-988a076a7d3so143618466b.3 for ; Mon, 19 Jun 2023 01:54:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20221208.gappssmtp.com; s=20221208; t=1687164858; x=1689756858; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SPf+y2ctEZoMI72ckvhMmROgBE22+ZnhLuRaMNUscz8=; b=F64R/K5b0EadtnOiOYb2nUWFwjqy/DD2rMbote0vH67+ouDjC826VzJoxWZcGwsdnk 9muDCiKsoJbPer8L/kkf6N1BQZBkdBk3bvQimpZdfqUlsv6ajjnN+TkqeljkNVWhUYGQ OH0hhgNV1k04q8QJSk+XNGtE/YfK+AJXPrF0hUzL2CEZhYG4TYVhmq2daTJ1ywmtOy9Q nXLISjjAN9T4tkczbiXGulzCc+o+csIYSf24jd889J81rxdu5kGnPd7ST0lQvaHZAVJZ YpRa2A4UbS1YUmOWirRUwtskqEB65MjorIVlgWT2pu6JKSN5SEMGBPssR7doF3aXLkxC 83iA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687164858; x=1689756858; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SPf+y2ctEZoMI72ckvhMmROgBE22+ZnhLuRaMNUscz8=; b=QfH3q/rHjunel0FdIpsTZ3BXTvkKpLt5Qk8oOdhNxzB//A75SgjQd7JaBpAM5ZZVzq WGNOAhJHzc9FTMhm2TF/jZv2UlPT+FKHCbnVLz2KZ9G30YTC/nqA/N2fvGf2EWYN+EXY GfPQpc8fKpxa3YMjq/LRJp10MTpIaH2ESP0ZdnF4pDMwnjkkkY0ej0j452RapuG1ZvO3 tr33xUxix6YCt1kJHN2gIk2+OYa3be2a5uta0adV2DBGNHTlLpS/h3l6I7k44s11dQlU 40P4HIbWXOZ0iQf8Hc0vhYqf8iN3CMzvpOlgoYFywFtRvlIjJzVXvPOcH3K3n48+OPyw NjnQ== X-Gm-Message-State: AC+VfDyttvAk2OReJ7LIYb0qAB+eWuFCgcvEblt7SN6dvOuKTIBSxeRM NFlq+tLbrISJcqpL0G+H4Ml6iA== X-Google-Smtp-Source: ACHHUZ4xquicSAHJqPCvbaZI6t/3cxct9sf1uRZJnZNSgS5IGO+5UpgoU9/0zLRTgndvL4XX4DXcrg== X-Received: by 2002:a17:907:2d94:b0:96f:f046:9a92 with SMTP id gt20-20020a1709072d9400b0096ff0469a92mr9526606ejc.37.1687164858251; Mon, 19 Jun 2023 01:54:18 -0700 (PDT) Received: from blmsp.fritz.box ([2001:4090:a245:802c:bc2b:8db8:9210:41eb]) by smtp.gmail.com with ESMTPSA id h27-20020a17090619db00b00987a6e01e94sm2994339ejd.214.2023.06.19.01.54.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 01:54:17 -0700 (PDT) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger Cc: Chun-Jie Chen , AngeloGioacchino Del Regno , Tinghan Shen , Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Alexandre Bailon , Fabien Parent , Markus Schneider-Pargmann Subject: [PATCH v5 6/8] soc: mediatek: Add support for WAY_EN operations Date: Mon, 19 Jun 2023 10:53:42 +0200 Message-Id: <20230619085344.2885311-7-msp@baylibre.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230619085344.2885311-1-msp@baylibre.com> References: <20230619085344.2885311-1-msp@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Alexandre Bailon This updates the power domain to support WAY_EN operations. WAY_EN operations on mt8365 are using a different component to check for the acknowledgment, namely the infracfg-nao component. Also to enable a way it the bit needs to be cleared while disabling a way needs a bit to be set. To support these two operations two flags are added, BUS_PROT_INVERTED and BUS_PROT_STA_COMPONENT_INFRA_NAO. Additionally another regmap is created if the INFRA_NAO capability is set. This operation is required by the mt8365 for the MM power domain. Signed-off-by: Alexandre Bailon Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann --- drivers/soc/mediatek/mtk-pm-domains.c | 39 +++++++++++++++++++++++---- drivers/soc/mediatek/mtk-pm-domains.h | 7 +++-- 2 files changed, 39 insertions(+), 7 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index 3cdf62c0b6bd..4659f0a0aa08 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -44,6 +44,7 @@ struct scpsys_domain { struct clk_bulk_data *clks; int num_subsys_clks; struct clk_bulk_data *subsys_clks; + struct regmap *infracfg_nao; struct regmap *infracfg; struct regmap *smi; struct regulator *supply; @@ -127,13 +128,26 @@ static struct regmap *scpsys_bus_protect_get_regmap(s= truct scpsys_domain *pd, return pd->infracfg; } =20 +static struct regmap *scpsys_bus_protect_get_sta_regmap(struct scpsys_doma= in *pd, + const struct scpsys_bus_prot_data *bpd) +{ + if (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO) + return pd->infracfg_nao; + else + return scpsys_bus_protect_get_regmap(pd, bpd); +} + static int scpsys_bus_protect_clear(struct scpsys_domain *pd, const struct scpsys_bus_prot_data *bpd) { + struct regmap *sta_regmap =3D scpsys_bus_protect_get_sta_regmap(pd, bpd); struct regmap *regmap =3D scpsys_bus_protect_get_regmap(pd, bpd); + u32 expected_ack; u32 val; u32 sta_mask =3D bpd->bus_prot_sta_mask; =20 + expected_ack =3D (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO ? sta_mas= k : 0); + if (bpd->flags & BUS_PROT_REG_UPDATE) regmap_clear_bits(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask); else @@ -142,14 +156,15 @@ static int scpsys_bus_protect_clear(struct scpsys_dom= ain *pd, if (bpd->flags & BUS_PROT_IGNORE_CLR_ACK) return 0; =20 - return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta, - val, !(val & sta_mask), + return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta, + val, (val & sta_mask) =3D=3D expected_ack, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); } =20 static int scpsys_bus_protect_set(struct scpsys_domain *pd, const struct scpsys_bus_prot_data *bpd) { + struct regmap *sta_regmap =3D scpsys_bus_protect_get_sta_regmap(pd, bpd); struct regmap *regmap =3D scpsys_bus_protect_get_regmap(pd, bpd); u32 val; u32 sta_mask =3D bpd->bus_prot_sta_mask; @@ -159,7 +174,7 @@ static int scpsys_bus_protect_set(struct scpsys_domain = *pd, else regmap_write(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask); =20 - return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta, + return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta, val, (val & sta_mask) =3D=3D sta_mask, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); } @@ -173,7 +188,10 @@ static int scpsys_bus_protect_enable(struct scpsys_dom= ain *pd) if (!bpd->bus_prot_set_clr_mask) break; =20 - ret =3D scpsys_bus_protect_set(pd, bpd); + if (bpd->flags & BUS_PROT_INVERTED) + ret =3D scpsys_bus_protect_clear(pd, bpd); + else + ret =3D scpsys_bus_protect_set(pd, bpd); if (ret) return ret; } @@ -190,7 +208,10 @@ static int scpsys_bus_protect_disable(struct scpsys_do= main *pd) if (!bpd->bus_prot_set_clr_mask) continue; =20 - ret =3D scpsys_bus_protect_clear(pd, bpd); + if (bpd->flags & BUS_PROT_INVERTED) + ret =3D scpsys_bus_protect_set(pd, bpd); + else + ret =3D scpsys_bus_protect_clear(pd, bpd); if (ret) return ret; } @@ -377,6 +398,14 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys= *scpsys, struct device_no return ERR_CAST(pd->smi); } =20 + pd->infracfg_nao =3D syscon_regmap_lookup_by_phandle(node, "mediatek,infr= acfg-nao"); + if (IS_ERR(pd->infracfg_nao)) { + if (MTK_SCPD_CAPS(pd, MTK_SCPD_HAS_INFRA_NAO)) + return ERR_CAST(pd->infracfg_nao); + + pd->infracfg_nao =3D NULL; + } + num_clks =3D of_clk_get_parent_count(node); if (num_clks > 0) { /* Calculate number of subsys_clks */ diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/m= tk-pm-domains.h index 356788263db2..562d4e92ce16 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -11,6 +11,7 @@ /* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */ #define MTK_SCPD_ALWAYS_ON BIT(5) #define MTK_SCPD_EXT_BUCK_ISO BIT(6) +#define MTK_SCPD_HAS_INFRA_NAO BIT(7) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) =20 #define SPM_VDE_PWR_CON 0x0210 @@ -45,8 +46,10 @@ enum scpsys_bus_prot_flags { BUS_PROT_REG_UPDATE =3D BIT(1), BUS_PROT_IGNORE_CLR_ACK =3D BIT(2), - BUS_PROT_COMPONENT_INFRA =3D BIT(3), - BUS_PROT_COMPONENT_SMI =3D BIT(4), + BUS_PROT_INVERTED =3D BIT(3), + BUS_PROT_COMPONENT_INFRA =3D BIT(4), + BUS_PROT_COMPONENT_SMI =3D BIT(5), + BUS_PROT_STA_COMPONENT_INFRA_NAO =3D BIT(6), }; =20 #define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \ --=20 2.40.1 From nobody Thu Nov 14 05:48:50 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F142EEB64D9 for ; Mon, 19 Jun 2023 08:55:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231233AbjFSIzg (ORCPT ); Mon, 19 Jun 2023 04:55:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231420AbjFSIzF (ORCPT ); Mon, 19 Jun 2023 04:55:05 -0400 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C071710D8 for ; Mon, 19 Jun 2023 01:54:20 -0700 (PDT) Received: by mail-ej1-x62a.google.com with SMTP id a640c23a62f3a-98377c5d53eso455742066b.0 for ; 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charset="utf-8" From: Alexandre Bailon This adds support for MTK_SCPD_STRICT_BUS_PROTECTION capability. It is a strict bus protection policy that requires the bus protection to be disabled before accessing the bus. This is required by the mt8365, for the MM power domain. Signed-off-by: Alexandre Bailon Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann --- drivers/soc/mediatek/mtk-pm-domains.c | 27 +++++++++++++++++++++++---- drivers/soc/mediatek/mtk-pm-domains.h | 1 + 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index 4659f0a0aa08..5c458aa2ddbe 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -262,9 +262,17 @@ static int scpsys_power_on(struct generic_pm_domain *g= enpd) regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); =20 - ret =3D clk_bulk_prepare_enable(pd->num_subsys_clks, pd->subsys_clks); - if (ret) - goto err_pwr_ack; + /* + * In few Mediatek platforms(e.g. MT6779), the bus protect policy is + * stricter, which leads to bus protect release must be prior to bus + * access. + */ + if (!MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUS_PROTECTION)) { + ret =3D clk_bulk_prepare_enable(pd->num_subsys_clks, + pd->subsys_clks); + if (ret) + goto err_pwr_ack; + } =20 ret =3D scpsys_sram_enable(pd); if (ret < 0) @@ -274,12 +282,23 @@ static int scpsys_power_on(struct generic_pm_domain *= genpd) if (ret < 0) goto err_disable_sram; =20 + if (MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUS_PROTECTION)) { + ret =3D clk_bulk_prepare_enable(pd->num_subsys_clks, + pd->subsys_clks); + if (ret) + goto err_enable_bus_protect; + } + return 0; =20 +err_enable_bus_protect: + scpsys_bus_protect_enable(pd); err_disable_sram: scpsys_sram_disable(pd); err_disable_subsys_clks: - clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks); + if (!MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUS_PROTECTION)) + clk_bulk_disable_unprepare(pd->num_subsys_clks, + pd->subsys_clks); err_pwr_ack: clk_bulk_disable_unprepare(pd->num_clks, pd->clks); err_reg: diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/m= tk-pm-domains.h index 562d4e92ce16..116c7875f74c 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -12,6 +12,7 @@ #define MTK_SCPD_ALWAYS_ON BIT(5) #define MTK_SCPD_EXT_BUCK_ISO BIT(6) #define MTK_SCPD_HAS_INFRA_NAO BIT(7) +#define MTK_SCPD_STRICT_BUS_PROTECTION BIT(8) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) =20 #define SPM_VDE_PWR_CON 0x0210 --=20 2.40.1 From nobody Thu Nov 14 05:48:50 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AE57EB64DA for ; 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charset="utf-8" From: Fabien Parent Add the needed board data to support MT8365 SoC. Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann --- drivers/soc/mediatek/mt8365-pm-domains.h | 197 +++++++++++++++++++++++ drivers/soc/mediatek/mtk-pm-domains.c | 5 + include/linux/soc/mediatek/infracfg.h | 41 +++++ 3 files changed, 243 insertions(+) create mode 100644 drivers/soc/mediatek/mt8365-pm-domains.h diff --git a/drivers/soc/mediatek/mt8365-pm-domains.h b/drivers/soc/mediate= k/mt8365-pm-domains.h new file mode 100644 index 000000000000..02f789e1c65a --- /dev/null +++ b/drivers/soc/mediatek/mt8365-pm-domains.h @@ -0,0 +1,197 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8365_PM_DOMAINS_H +#define __SOC_MEDIATEK_MT8365_PM_DOMAINS_H + +#include "mtk-pm-domains.h" +#include + +/* + * MT8365 power domain support + */ + +#define MT8365_BUS_PROT_INFRA_WR_TOPAXI(_mask) \ + BUS_PROT_INFRA_WR(_mask, \ + MT8365_INFRA_TOPAXI_PROTECTEN_SET, \ + MT8365_INFRA_TOPAXI_PROTECTEN_CLR, \ + MT8365_INFRA_TOPAXI_PROTECTEN_STA1) + +#define MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(_mask) \ + BUS_PROT_INFRA_WR(_mask, \ + MT8365_INFRA_TOPAXI_PROTECTEN_1_SET, \ + MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR, \ + MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1) + +#define MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(port) \ + BUS_PROT_SMI_WR(BIT(port), \ + MT8365_SMI_COMMON_CLAMP_EN_SET, \ + MT8365_SMI_COMMON_CLAMP_EN_CLR, \ + MT8365_SMI_COMMON_CLAMP_EN) + +#define MT8365_BUS_PROT_WAY_EN(_set_mask, _set, _sta_mask, _sta) \ + _BUS_PROT(_set_mask, _set, _set, _sta_mask, _sta, \ + BUS_PROT_COMPONENT_INFRA | \ + BUS_PROT_STA_COMPONENT_INFRA_NAO | \ + BUS_PROT_INVERTED | \ + BUS_PROT_REG_UPDATE) + +static const struct scpsys_domain_data scpsys_domain_data_mt8365[] =3D { + [MT8365_POWER_DOMAIN_MM] =3D { + .name =3D "mm", + .sta_mask =3D PWR_STATUS_DISP, + .ctl_offs =3D 0x30c, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .bp_cfg =3D { + MT8365_BUS_PROT_INFRA_WR_TOPAXI_1( + MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_0 | + MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_1), + MT8365_BUS_PROT_INFRA_WR_TOPAXI( + MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 | + MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1 | + MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0 | + MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1), + MT8365_BUS_PROT_WAY_EN( + MT8365_INFRA_TOPAXI_SI0_WAY_EN_MMAPB_S, + MT8365_INFRA_TOPAXI_SI0_CTL, + MT8365_INFRA_NAO_TOPAXI_SI0_CTRL_UPDATED, + MT8365_INFRA_NAO_TOPAXI_SI0_STA), + MT8365_BUS_PROT_WAY_EN( + MT8365_INFRA_TOPAXI_SI2_WAY_EN_PERI_M1, + MT8365_INFRA_TOPAXI_SI2_CTL, + MT8365_INFRA_NAO_TOPAXI_SI2_CTRL_UPDATED, + MT8365_INFRA_NAO_TOPAXI_SI2_STA), + MT8365_BUS_PROT_INFRA_WR_TOPAXI( + MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S), + }, + .caps =3D MTK_SCPD_STRICT_BUS_PROTECTION | MTK_SCPD_HAS_INFRA_NAO, + }, + [MT8365_POWER_DOMAIN_VENC] =3D { + .name =3D "venc", + .sta_mask =3D PWR_STATUS_VENC, + .ctl_offs =3D 0x0304, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .bp_cfg =3D { + MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(1), + }, + }, + [MT8365_POWER_DOMAIN_AUDIO] =3D { + .name =3D "audio", + .sta_mask =3D PWR_STATUS_AUDIO, + .ctl_offs =3D 0x0314, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(12, 8), + .sram_pdn_ack_bits =3D GENMASK(17, 13), + .bp_cfg =3D { + MT8365_BUS_PROT_INFRA_WR_TOPAXI_1( + MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_MP1_L2C_AFIFO | + MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_AUDIO_M), + }, + .caps =3D MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8365_POWER_DOMAIN_CONN] =3D { + .name =3D "conn", + .sta_mask =3D PWR_STATUS_CONN, + .ctl_offs =3D 0x032c, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D 0, + .sram_pdn_ack_bits =3D 0, + .bp_cfg =3D { + MT8365_BUS_PROT_INFRA_WR_TOPAXI( + MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB), + MT8365_BUS_PROT_INFRA_WR_TOPAXI_1( + MT8365_INFRA_TOPAXI_PROTECTEN_1_CONN2INFRA_AXI_GALS_MST), + MT8365_BUS_PROT_INFRA_WR_TOPAXI( + MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB), + MT8365_BUS_PROT_INFRA_WR_TOPAXI_1( + MT8365_INFRA_TOPAXI_PROTECTEN_1_INFRA2CONN_AHB_GALS_SLV), + }, + .caps =3D MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8365_POWER_DOMAIN_MFG] =3D { + .name =3D "mfg", + .sta_mask =3D PWR_STATUS_MFG, + .ctl_offs =3D 0x0338, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(9, 8), + .sram_pdn_ack_bits =3D GENMASK(13, 12), + .bp_cfg =3D { + MT8365_BUS_PROT_INFRA_WR_TOPAXI(BIT(25)), + MT8365_BUS_PROT_INFRA_WR_TOPAXI( + MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0 | + MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG), + }, + }, + [MT8365_POWER_DOMAIN_CAM] =3D { + .name =3D "cam", + .sta_mask =3D BIT(25), + .ctl_offs =3D 0x0344, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(9, 8), + .sram_pdn_ack_bits =3D GENMASK(13, 12), + .bp_cfg =3D { + MT8365_BUS_PROT_INFRA_WR_TOPAXI_1( + MT8365_INFRA_TOPAXI_PROTECTEN_1_CAM2MM_AXI_GALS_MST), + MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(2), + }, + }, + [MT8365_POWER_DOMAIN_VDEC] =3D { + .name =3D "vdec", + .sta_mask =3D BIT(31), + .ctl_offs =3D 0x0370, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .bp_cfg =3D { + MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(3), + }, + }, + [MT8365_POWER_DOMAIN_APU] =3D { + .name =3D "apu", + .sta_mask =3D BIT(16), + .ctl_offs =3D 0x0378, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(14, 8), + .sram_pdn_ack_bits =3D GENMASK(21, 15), + .bp_cfg =3D { + MT8365_BUS_PROT_INFRA_WR_TOPAXI_1( + MT8365_INFRA_TOPAXI_PROTECTEN_1_APU2AP | + MT8365_INFRA_TOPAXI_PROTECTEN_1_APU_CBIP_GALS_MST), + MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(4), + }, + }, + [MT8365_POWER_DOMAIN_DSP] =3D { + .name =3D "dsp", + .sta_mask =3D BIT(17), + .ctl_offs =3D 0x037C, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(11, 8), + .sram_pdn_ack_bits =3D GENMASK(15, 12), + .bp_cfg =3D { + MT8365_BUS_PROT_INFRA_WR_TOPAXI_1( + MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_INFRA_GALS_ADB | + MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_M | + MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_S), + }, + .caps =3D MTK_SCPD_ACTIVE_WAKEUP, + }, +}; + +static const struct scpsys_soc_data mt8365_scpsys_data =3D { + .domains_data =3D scpsys_domain_data_mt8365, + .num_domains =3D ARRAY_SIZE(scpsys_domain_data_mt8365), +}; + +#endif /* __SOC_MEDIATEK_MT8365_PM_DOMAINS_H */ diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index 5c458aa2ddbe..576d90c3f049 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -24,6 +24,7 @@ #include "mt8188-pm-domains.h" #include "mt8192-pm-domains.h" #include "mt8195-pm-domains.h" +#include "mt8365-pm-domains.h" =20 #define MTK_POLL_DELAY_US 10 #define MTK_POLL_TIMEOUT USEC_PER_SEC @@ -652,6 +653,10 @@ static const struct of_device_id scpsys_of_match[] =3D= { .compatible =3D "mediatek,mt8195-power-controller", .data =3D &mt8195_scpsys_data, }, + { + .compatible =3D "mediatek,mt8365-power-controller", + .data =3D &mt8365_scpsys_data, + }, { } }; =20 diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/medi= atek/infracfg.h index 07f67b3d8e97..f853397697b5 100644 --- a/include/linux/soc/mediatek/infracfg.h +++ b/include/linux/soc/mediatek/infracfg.h @@ -2,6 +2,47 @@ #ifndef __SOC_MEDIATEK_INFRACFG_H #define __SOC_MEDIATEK_INFRACFG_H =20 +#define MT8365_INFRA_TOPAXI_PROTECTEN_STA1 0x228 +#define MT8365_INFRA_TOPAXI_PROTECTEN_SET 0x2a0 +#define MT8365_INFRA_TOPAXI_PROTECTEN_CLR 0x2a4 +# define MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 BIT(1) +# define MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1 BIT(2) +# define MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S BIT(6) +# define MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0 BIT(10) +# define MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1 BIT(11) +# define MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB BIT(13) +# define MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB BIT(14) +# define MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0 BIT(21) +# define MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG BIT(22) +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1 0x258 +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_SET 0x2a8 +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR 0x2ac +# define MT8365_INFRA_TOPAXI_PROTECTEN_1_APU2AP BIT(2) +# define MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_0 BIT(16) +# define MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_1 BIT(17) +# define MT8365_INFRA_TOPAXI_PROTECTEN_1_CONN2INFRA_AXI_GALS_MST BIT(18) +# define MT8365_INFRA_TOPAXI_PROTECTEN_1_CAM2MM_AXI_GALS_MST BIT(19) +# define MT8365_INFRA_TOPAXI_PROTECTEN_1_APU_CBIP_GALS_MST BIT(20) +# define MT8365_INFRA_TOPAXI_PROTECTEN_1_INFRA2CONN_AHB_GALS_SLV BIT(21) +# define MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_INFRA_GALS_ADB BIT(24) +# define MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_MP1_L2C_AFIFO BIT(27) +# define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_AUDIO_M BIT(28) +# define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_M BIT(30) +# define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_S BIT(31) + +#define MT8365_INFRA_NAO_TOPAXI_SI0_STA 0x0 +# define MT8365_INFRA_NAO_TOPAXI_SI0_CTRL_UPDATED BIT(24) +#define MT8365_INFRA_NAO_TOPAXI_SI2_STA 0x28 +# define MT8365_INFRA_NAO_TOPAXI_SI2_CTRL_UPDATED BIT(14) +#define MT8365_INFRA_TOPAXI_SI0_CTL 0x200 +# define MT8365_INFRA_TOPAXI_SI0_WAY_EN_MMAPB_S BIT(6) +#define MT8365_INFRA_TOPAXI_SI2_CTL 0x234 +# define MT8365_INFRA_TOPAXI_SI2_WAY_EN_PERI_M1 BIT(5) + +#define MT8365_SMI_COMMON_CLAMP_EN 0x3c0 +#define MT8365_SMI_COMMON_CLAMP_EN_SET 0x3c4 +#define MT8365_SMI_COMMON_CLAMP_EN_CLR 0x3c8 + #define MT8195_TOP_AXI_PROT_EN_STA1 0x228 #define MT8195_TOP_AXI_PROT_EN_1_STA1 0x258 #define MT8195_TOP_AXI_PROT_EN_SET 0x2a0 --=20 2.40.1