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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On the SM8550 SoC, some nodes requires a specific bit mark instead of a bandwidth when voting. Add an enable_mask variable to be used to vote when a node is enabled in an aggregate loop. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- drivers/interconnect/qcom/bcm-voter.c | 5 +++++ drivers/interconnect/qcom/icc-rpmh.h | 2 ++ 2 files changed, 7 insertions(+) diff --git a/drivers/interconnect/qcom/bcm-voter.c b/drivers/interconnect/q= com/bcm-voter.c index 8f385f9c2dd3..d5f2a6b5376b 100644 --- a/drivers/interconnect/qcom/bcm-voter.c +++ b/drivers/interconnect/qcom/bcm-voter.c @@ -83,6 +83,11 @@ static void bcm_aggregate(struct qcom_icc_bcm *bcm) =20 temp =3D agg_peak[bucket] * bcm->vote_scale; bcm->vote_y[bucket] =3D bcm_div(temp, bcm->aux_data.unit); + + if (bcm->enable_mask && (bcm->vote_x[bucket] || bcm->vote_y[bucket])) { + bcm->vote_x[bucket] =3D 0; + bcm->vote_y[bucket] =3D bcm->enable_mask; + } } =20 if (bcm->keepalive && bcm->vote_x[QCOM_ICC_BUCKET_AMC] =3D=3D 0 && diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qc= om/icc-rpmh.h index 04391c1ba465..7843d8864d6b 100644 --- a/drivers/interconnect/qcom/icc-rpmh.h +++ b/drivers/interconnect/qcom/icc-rpmh.h @@ -81,6 +81,7 @@ struct qcom_icc_node { * @vote_x: aggregated threshold values, represents sum_bw when @type is b= w bcm * @vote_y: aggregated threshold values, represents peak_bw when @type is = bw bcm * @vote_scale: scaling factor for vote_x and vote_y + * @enable_mask: optional mask to send as vote instead of vote_x/vote_y * @dirty: flag used to indicate whether the bcm needs to be committed * @keepalive: flag used to indicate whether a keepalive is required * @aux_data: auxiliary data used when calculating threshold values and @@ -97,6 +98,7 @@ struct qcom_icc_bcm { u64 vote_x[QCOM_ICC_NUM_BUCKETS]; u64 vote_y[QCOM_ICC_NUM_BUCKETS]; u64 vote_scale; + u32 enable_mask; bool dirty; bool keepalive; struct bcm_db aux_data; --=20 2.34.1 From nobody Mon Feb 9 16:26:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 399D2EB64D9 for ; Mon, 19 Jun 2023 08:26:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229549AbjFSI0v (ORCPT ); Mon, 19 Jun 2023 04:26:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230295AbjFSIYv (ORCPT ); Mon, 19 Jun 2023 04:24:51 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 430FEE64 for ; Mon, 19 Jun 2023 01:24:47 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-307d58b3efbso2261789f8f.0 for ; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Set the proper enable_mask to needs requiring such value to be used instead of a bandwidth when voting. The masks were copied from the downstream implementation at [1]. [1] https://git.codelinaro.org/clo/la/kernel/msm-5.15/-/blob/kernel.lnx.5.1= 5.r1-rel/drivers/interconnect/qcom/kalama.c Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- drivers/interconnect/qcom/sm8550.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/interconnect/qcom/sm8550.c b/drivers/interconnect/qcom= /sm8550.c index d823ba988ef6..0864ed285375 100644 --- a/drivers/interconnect/qcom/sm8550.c +++ b/drivers/interconnect/qcom/sm8550.c @@ -1473,6 +1473,7 @@ static struct qcom_icc_node qns_mem_noc_sf_cam_ife_2 = =3D { =20 static struct qcom_icc_bcm bcm_acv =3D { .name =3D "ACV", + .enable_mask =3D 0x8, .num_nodes =3D 1, .nodes =3D { &ebi }, }; @@ -1485,6 +1486,7 @@ static struct qcom_icc_bcm bcm_ce0 =3D { =20 static struct qcom_icc_bcm bcm_cn0 =3D { .name =3D "CN0", + .enable_mask =3D 0x1, .keepalive =3D true, .num_nodes =3D 54, .nodes =3D { &qsm_cfg, &qhs_ahb2phy0, @@ -1524,6 +1526,7 @@ static struct qcom_icc_bcm bcm_cn1 =3D { =20 static struct qcom_icc_bcm bcm_co0 =3D { .name =3D "CO0", + .enable_mask =3D 0x1, .num_nodes =3D 2, .nodes =3D { &qxm_nsp, &qns_nsp_gemnoc }, }; @@ -1549,6 +1552,7 @@ static struct qcom_icc_bcm bcm_mm0 =3D { =20 static struct qcom_icc_bcm bcm_mm1 =3D { .name =3D "MM1", + .enable_mask =3D 0x1, .num_nodes =3D 8, .nodes =3D { &qnm_camnoc_hf, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_vapss_hcp, @@ -1589,6 +1593,7 @@ static struct qcom_icc_bcm bcm_sh0 =3D { =20 static struct qcom_icc_bcm bcm_sh1 =3D { .name =3D "SH1", + .enable_mask =3D 0x1, .num_nodes =3D 13, .nodes =3D { &alm_gpu_tcu, &alm_sys_tcu, &chm_apps, &qnm_gpu, @@ -1608,6 +1613,7 @@ static struct qcom_icc_bcm bcm_sn0 =3D { =20 static struct qcom_icc_bcm bcm_sn1 =3D { .name =3D "SN1", + .enable_mask =3D 0x1, .num_nodes =3D 3, .nodes =3D { &qhm_gic, &xm_gic, &qns_gemnoc_gc }, @@ -1633,6 +1639,7 @@ static struct qcom_icc_bcm bcm_sn7 =3D { =20 static struct qcom_icc_bcm bcm_acv_disp =3D { .name =3D "ACV", + .enable_mask =3D 0x1, .num_nodes =3D 1, .nodes =3D { &ebi_disp }, }; @@ -1657,12 +1664,14 @@ static struct qcom_icc_bcm bcm_sh0_disp =3D { =20 static struct qcom_icc_bcm bcm_sh1_disp =3D { .name =3D "SH1", + .enable_mask =3D 0x1, .num_nodes =3D 2, .nodes =3D { &qnm_mnoc_hf_disp, &qnm_pcie_disp }, }; =20 static struct qcom_icc_bcm bcm_acv_cam_ife_0 =3D { .name =3D "ACV", + .enable_mask =3D 0x0, .num_nodes =3D 1, .nodes =3D { &ebi_cam_ife_0 }, }; @@ -1681,6 +1690,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_0 =3D { =20 static struct qcom_icc_bcm bcm_mm1_cam_ife_0 =3D { .name =3D "MM1", + .enable_mask =3D 0x1, .num_nodes =3D 4, .nodes =3D { &qnm_camnoc_hf_cam_ife_0, &qnm_camnoc_icp_cam_ife_0, &qnm_camnoc_sf_cam_ife_0, &qns_mem_noc_sf_cam_ife_0 }, @@ -1694,6 +1704,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_0 =3D { =20 static struct qcom_icc_bcm bcm_sh1_cam_ife_0 =3D { .name =3D "SH1", + .enable_mask =3D 0x1, .num_nodes =3D 3, .nodes =3D { &qnm_mnoc_hf_cam_ife_0, &qnm_mnoc_sf_cam_ife_0, &qnm_pcie_cam_ife_0 }, @@ -1701,6 +1712,7 @@ static struct qcom_icc_bcm bcm_sh1_cam_ife_0 =3D { =20 static struct qcom_icc_bcm bcm_acv_cam_ife_1 =3D { .name =3D "ACV", + .enable_mask =3D 0x0, .num_nodes =3D 1, .nodes =3D { &ebi_cam_ife_1 }, }; @@ -1719,6 +1731,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_1 =3D { =20 static struct qcom_icc_bcm bcm_mm1_cam_ife_1 =3D { .name =3D "MM1", + .enable_mask =3D 0x1, .num_nodes =3D 4, .nodes =3D { &qnm_camnoc_hf_cam_ife_1, &qnm_camnoc_icp_cam_ife_1, &qnm_camnoc_sf_cam_ife_1, &qns_mem_noc_sf_cam_ife_1 }, @@ -1732,6 +1745,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_1 =3D { =20 static struct qcom_icc_bcm bcm_sh1_cam_ife_1 =3D { .name =3D "SH1", + .enable_mask =3D 0x1, .num_nodes =3D 3, .nodes =3D { &qnm_mnoc_hf_cam_ife_1, &qnm_mnoc_sf_cam_ife_1, &qnm_pcie_cam_ife_1 }, @@ -1739,6 +1753,7 @@ static struct qcom_icc_bcm bcm_sh1_cam_ife_1 =3D { =20 static struct qcom_icc_bcm bcm_acv_cam_ife_2 =3D { .name =3D "ACV", + .enable_mask =3D 0x0, .num_nodes =3D 1, .nodes =3D { &ebi_cam_ife_2 }, }; @@ -1757,6 +1772,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_2 =3D { =20 static struct qcom_icc_bcm bcm_mm1_cam_ife_2 =3D { .name =3D "MM1", + .enable_mask =3D 0x1, .num_nodes =3D 4, .nodes =3D { &qnm_camnoc_hf_cam_ife_2, &qnm_camnoc_icp_cam_ife_2, &qnm_camnoc_sf_cam_ife_2, &qns_mem_noc_sf_cam_ife_2 }, @@ -1770,6 +1786,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_2 =3D { =20 static struct qcom_icc_bcm bcm_sh1_cam_ife_2 =3D { .name =3D "SH1", + .enable_mask =3D 0x1, .num_nodes =3D 3, .nodes =3D { &qnm_mnoc_hf_cam_ife_2, &qnm_mnoc_sf_cam_ife_2, &qnm_pcie_cam_ife_2 }, --=20 2.34.1