From nobody Sun Feb 8 18:15:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 665DEEB64D7 for ; Sun, 18 Jun 2023 13:24:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229802AbjFRNYE (ORCPT ); Sun, 18 Jun 2023 09:24:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229509AbjFRNX6 (ORCPT ); Sun, 18 Jun 2023 09:23:58 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 52F651728; Sun, 18 Jun 2023 06:23:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1687094612; x=1718630612; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=rCzFHJ7T9piwXY/XOwXix/8/izDJuLEne8+2d/T2SUE=; b=VFQSWdIkcOOosdYv1bbkRnzkWGIO02cHLvGChBhMo9WBEkiEve5efrX5 VfUW6Q4srhD1dih+5bCpcidaiWoOBrdd1uryG8yeRKx+gtEeUF79zY+S6 OthFiayBFxsxjnj7DOzS4sGJBjWDULdt/v8zt0gcyIjeuLAstnvKk10lq yC+nCjX+xzX6UwAmTemhgnyS6cEJWcC8FMuefUzT9DmDMYxtRDnawtpo3 keoQcMm2PGWUkqK6bDcZB4AKQXpaIpkXVdJTTzBlR8C0uJzJYppCupg+L lY4WbgYs3vCFsERrIKuJ9dVkRtJ/OXqoddFEJYH1eDZnO3VSXzbFomcZB Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10745"; a="356967092" X-IronPort-AV: E=Sophos;i="6.00,252,1681196400"; d="scan'208";a="356967092" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2023 06:23:31 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10745"; a="747146851" X-IronPort-AV: E=Sophos;i="6.00,252,1681196400"; d="scan'208";a="747146851" Received: from unknown (HELO localhost.localdomain) ([10.226.216.116]) by orsmga001.jf.intel.com with ESMTP; 18 Jun 2023 06:23:27 -0700 From: niravkumar.l.rabara@intel.com To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Niravkumar L Rabara , Andrew Lunn , Dinh Nguyen , Michael Turquette , Stephen Boyd , Philipp Zabel , Wen Ping , Richard Cochran , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, netdev@vger.kernel.org, Adrian Ng Ho Yin Subject: [PATCH 4/4] arm64: dts: agilex5: Add initial support for Intel's Agilex5 SoCFPGA Date: Sun, 18 Jun 2023 21:22:35 +0800 Message-Id: <20230618132235.728641-5-niravkumar.l.rabara@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230618132235.728641-1-niravkumar.l.rabara@intel.com> References: <20230618132235.728641-1-niravkumar.l.rabara@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Niravkumar L Rabara Add the initial device tree files for Intel's Agilex5 SoCFPGA platform. Signed-off-by: Adrian Ng Ho Yin Signed-off-by: Niravkumar L Rabara --- arch/arm64/boot/dts/intel/Makefile | 3 + .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 641 ++++++++++++++++++ .../boot/dts/intel/socfpga_agilex5_socdk.dts | 184 +++++ .../dts/intel/socfpga_agilex5_socdk_nand.dts | 131 ++++ .../dts/intel/socfpga_agilex5_socdk_swvp.dts | 248 +++++++ 5 files changed, 1207 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_swvp.dts diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel= /Makefile index c2a723838344..bb74a7e30e58 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -2,5 +2,8 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) +=3D socfpga_agilex_n6000.dtb \ socfpga_agilex_socdk.dtb \ socfpga_agilex_socdk_nand.dtb \ + socfpga_agilex5_socdk.dtb \ + socfpga_agilex5_socdk_nand.dtb \ + socfpga_agilex5_socdk_swvp.dtb \ socfpga_n5x_socdk.dtb dtb-$(CONFIG_ARCH_KEEMBAY) +=3D keembay-evm.dtb diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/bo= ot/dts/intel/socfpga_agilex5.dtsi new file mode 100644 index 000000000000..9454d88d6457 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -0,0 +1,641 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023, Intel Corporation + */ + +/dts-v1/; +#include +#include +#include +#include +#include + +/ { + compatible =3D "intel,socfpga-agilex"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + service_reserved: svcbuffer@0 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0x80000000 0x0 0x2000000>; + alignment =3D <0x1000>; + no-map; + }; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a55"; + device_type =3D "cpu"; + enable-method =3D "psci"; + reg =3D <0x0>; + }; + + cpu1: cpu@1 { + compatible =3D "arm,cortex-a55"; + device_type =3D "cpu"; + enable-method =3D "psci"; + reg =3D <0x100>; + }; + + cpu2: cpu@2 { + compatible =3D "arm,cortex-a76"; + device_type =3D "cpu"; + enable-method =3D "psci"; + reg =3D <0x200>; + }; + + cpu3: cpu@3 { + compatible =3D "arm,cortex-a76"; + device_type =3D "cpu"; + enable-method =3D "psci"; + reg =3D <0x300>; + }; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + intc: interrupt-controller@1d000000 { + compatible =3D "arm,gic-v3", "arm,cortex-a15-gic"; + #interrupt-cells =3D <3>; + #address-cells =3D <2>; + #size-cells =3D<2>; + interrupt-controller; + #redistributor-regions =3D <1>; + label =3D "GIC"; + status =3D "okay"; + ranges; + redistributor-stride =3D <0x0 0x20000>; + reg =3D <0x0 0x1d000000 0 0x10000>, + <0x0 0x1d060000 0 0x100000>; + + its: msi-controller@1d040000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x1d040000 0x0 0x20000>; + label =3D "ITS"; + msi-controller; + status =3D "okay"; + }; + }; + + /* Clock tree 5 main sources*/ + clocks { + cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + }; + + cb_intosc_ls_clk: cb-intosc-ls-clk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + }; + + f2s_free_clk: f2s-free-clk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + }; + + osc1: osc1 { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + }; + + qspi_clk: qspi-clk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <200000000>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&intc>; + interrupts =3D , + , + , + ; + }; + + usbphy0: usbphy { + #phy-cells =3D <0>; + compatible =3D "usb-nop-xceiv"; + }; + + soc { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "simple-bus"; + device_type =3D "soc"; + interrupt-parent =3D <&intc>; + ranges =3D <0 0 0 0xffffffff>; + + clkmgr: clock-controller@10d10000 { + compatible =3D "intel,agilex5-clkmgr"; + reg =3D <0x10d10000 0x1000>; + #clock-cells =3D <1>; + }; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt =3D <31>; + snps,rd_osr_lmt =3D <31>; + snps,blen =3D <0 0 0 32 16 8 4>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <8>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x1>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x2>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x3>; + }; + queue4 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x4>; + }; + queue5 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x5>; + }; + queue6 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x6>; + }; + queue7 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x7>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <8>; + snps,tx-sched-wrr; + queue0 { + snps,weight =3D <0x09>; + snps,dcb-algorithm; + }; + queue1 { + snps,weight =3D <0x0A>; + snps,dcb-algorithm; + }; + queue2 { + snps,weight =3D <0x0B>; + snps,dcb-algorithm; + }; + queue3 { + snps,weight =3D <0x0C>; + snps,dcb-algorithm; + }; + queue4 { + snps,weight =3D <0x0D>; + snps,dcb-algorithm; + }; + queue5 { + snps,weight =3D <0x0E>; + snps,dcb-algorithm; + }; + queue6 { + snps,weight =3D <0x0F>; + snps,dcb-algorithm; + }; + queue7 { + snps,weight =3D <0x10>; + snps,dcb-algorithm; + }; + }; + + gmac0: ethernet@10810000 { + compatible =3D "altr,socfpga-stmmac-a10-s10", + "snps,dwxgmac-2.10", + "snps,dwxgmac"; + reg =3D <0x10810000 0x3500>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "macirq", + "macirq_tx0", + "macirq_tx1", + "macirq_tx2", + "macirq_tx3", + "macirq_tx4", + "macirq_tx5", + "macirq_tx6", + "macirq_tx7", + "macirq_rx0", + "macirq_rx1", + "macirq_rx2", + "macirq_rx3", + "macirq_rx4", + "macirq_rx5", + "macirq_rx6", + "macirq_rx7"; + mac-address =3D [00 00 00 00 00 00]; + resets =3D <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; + reset-names =3D "stmmaceth", "stmmaceth-ocp"; + tx-fifo-depth =3D <32768>; + rx-fifo-depth =3D <16384>; + snps,multicast-filter-bins =3D <64>; + snps,perfect-filter-entries =3D <64>; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,mtl-rx-config =3D <&mtl_rx_setup>; + snps,mtl-tx-config =3D <&mtl_tx_setup>; + snps,pbl =3D <32>; + snps,pblx8; + snps,multi-irq-en; + snps,tso; + altr,sysmgr-syscon =3D <&sysmgr 0x44 0>; + altr,smtg-hub; + snps,rx-vlan-offload; + clocks =3D <&clkmgr AGILEX5_EMAC0_CLK>, <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names =3D "stmmaceth", "ptp_ref"; + status =3D "disabled"; + }; + + i2c0: i2c@10c02800 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,designware-i2c"; + reg =3D <0x10c02800 0x100>; + interrupts =3D ; + resets =3D <&rst I2C0_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + status =3D "disabled"; + }; + + i2c1: i2c@10c02900 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,designware-i2c"; + reg =3D <0x10c02900 0x100>; + interrupts =3D ; + resets =3D <&rst I2C1_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + status =3D "disabled"; + }; + + i2c2: i2c@10c02a00 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,designware-i2c"; + reg =3D <0x10c02a00 0x100>; + interrupts =3D ; + resets =3D <&rst I2C2_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + status =3D "disabled"; + }; + + i2c3: i2c@10c02b00 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,designware-i2c"; + reg =3D <0x10c02b00 0x100>; + interrupts =3D ; + resets =3D <&rst I2C3_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + status =3D "disabled"; + }; + + i2c4: i2c@10c02c00 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,designware-i2c"; + reg =3D <0x10c02c00 0x100>; + interrupts =3D ; + resets =3D <&rst I2C4_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + status =3D "disabled"; + }; + + i3c0: i3c@10da0000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dw-i3c-master-1.00a"; + reg =3D <0x10da0000 0x1000>; + interrupts =3D ; + resets =3D <&rst I3C0_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_MP_CLK>; + status =3D "disabled"; + }; + + i3c1: i3c@10da1000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dw-i3c-master-1.00a"; + reg =3D <0x10da1000 0x1000>; + interrupts =3D ; + resets =3D <&rst I3C1_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_MP_CLK>; + status =3D "disabled"; + }; + + gpio1: gpio@10C03300 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0x10C03300 0x100>; + resets =3D <&rst GPIO1_RESET>; + status =3D "disabled"; + + portb: gpio-controller@0 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <24>; + reg =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D ; + }; + }; + + mmc: mmc0@10808000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "cdns,sd4hc"; + reg =3D <0x10808000 0x1000>; + interrupts =3D ; + fifo-depth =3D <0x800>; + resets =3D <&rst SDMMC_RESET>; + reset-names =3D "reset"; + clocks =3D <&clkmgr AGILEX5_L4_MP_CLK>, <&clkmgr AGILEX5_SDMCLK>; + clock-names =3D "biu", "ciu"; + /*iommus =3D <&smmu 5>;*/ + status =3D "disabled"; + }; + + nand: nand-controller@10b80000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "cdns,hp-nfc"; + reg =3D <0x10b80000 0x10000>, + <0x10840000 0x1000>; + reg-names =3D "reg", "sdma"; + interrupts =3D ; + clocks =3D <&clkmgr AGILEX5_NAND_NF_CLK>; + clock-names =3D "nf_clk"; + cdns,board-delay-ps =3D <4830>; + status =3D "disabled"; + }; + + ocram: sram@00000000 { + compatible =3D "mmio-sram"; + reg =3D <0x00000000 0x40000>; + }; + + dmac0: dma-controller@10DB0000 { + compatible =3D "snps,axi-dma-1.01a"; + reg =3D <0x10DB0000 0x500>; + clocks =3D <&clkmgr AGILEX5_L4_MAIN_CLK>, + <&clkmgr AGILEX5_L4_MP_CLK>; + clock-names =3D "core-clk", "cfgr-clk"; + interrupt-parent =3D <&intc>; + interrupts =3D ; + #dma-cells =3D <1>; + dma-channels =3D <4>; + snps,dma-masters =3D <1>; + snps,data-width =3D <2>; + snps,block-size =3D <32767 32767 32767 32767>; + snps,priority =3D <0 1 2 3>; + snps,axi-max-burst-len =3D <8>; + status =3D "okay"; + }; + + dmac1: dma-controller@10DC0000 { + compatible =3D "snps,axi-dma-1.01a"; + reg =3D <0x10DC0000 0x500>; + clocks =3D <&clkmgr AGILEX5_L4_MAIN_CLK>, + <&clkmgr AGILEX5_L4_MP_CLK>; + clock-names =3D "core-clk", "cfgr-clk"; + interrupt-parent =3D <&intc>; + interrupts =3D ; + #dma-cells =3D <1>; + dma-channels =3D <4>; + snps,dma-masters =3D <1>; + snps,data-width =3D <2>; + snps,block-size =3D <32767 32767 32767 32767>; + snps,priority =3D <0 1 2 3>; + snps,axi-max-burst-len =3D <8>; + status =3D "okay"; + }; + + rst: rstmgr@10d11000 { + #reset-cells =3D <1>; + compatible =3D "altr,stratix10-rst-mgr"; + reg =3D <0x10d11000 0x100>; + }; + + spi0: spi@10da4000 { + compatible =3D "snps,dw-apb-ssi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x10da4000 0x1000>; + interrupts =3D ; + resets =3D <&rst SPIM0_RESET>; + reset-names =3D "spi"; + reg-io-width =3D <4>; + num-cs =3D <4>; + clocks =3D <&clkmgr AGILEX5_L4_MAIN_CLK>; + dmas =3D <&dmac0 2>, <&dmac0 3>; + dma-names =3D"tx", "rx"; + + status =3D "disabled"; + + flash: m25p128@0 { + status =3D "okay"; + compatible =3D "st,m25p80"; + spi-max-frequency =3D <25000000>; + m25p,fast-read; + reg =3D <0>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "spi_flash_part0"; + reg =3D <0x0 0x100000>; + }; + }; + + }; + + spi1: spi@10da5000 { + compatible =3D "snps,dw-apb-ssi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x10da5000 0x1000>; + interrupts =3D ; + resets =3D <&rst SPIM1_RESET>; + reset-names =3D "spi"; + reg-io-width =3D <4>; + num-cs =3D <4>; + clocks =3D <&clkmgr AGILEX5_L4_MAIN_CLK>; + status =3D "disabled"; + }; + + sysmgr: sysmgr@10d12000 { + compatible =3D "altr,sys-mgr-s10","altr,sys-mgr"; + reg =3D <0x10d12000 0x500>; + }; + + timer0: timer0@10c03000 { + compatible =3D "snps,dw-apb-timer"; + interrupts =3D ; + reg =3D <0x10c03000 0x100>; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names =3D "timer"; + }; + + timer1: timer1@10c03100 { + compatible =3D "snps,dw-apb-timer"; + interrupts =3D ; + reg =3D <0x10c03100 0x100>; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names =3D "timer"; + }; + + timer2: timer2@10d00000 { + compatible =3D "snps,dw-apb-timer"; + interrupts =3D ; + reg =3D <0x10d00000 0x100>; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names =3D "timer"; + }; + + timer3: timer3@10d00100 { + compatible =3D "snps,dw-apb-timer"; + interrupts =3D ; + reg =3D <0x10d00100 0x100>; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names =3D "timer"; + }; + + uart0: serial@10c02000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x10c02000 0x100>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + resets =3D <&rst UART0_RESET>; + status =3D "disabled"; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + }; + + uart1: serial@10c02100 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x10c02100 0x100>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + resets =3D <&rst UART1_RESET>; + status =3D "disabled"; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + }; + + usb0: usb@10b00000 { + compatible =3D "snps,dwc2"; + reg =3D <0x10b00000 0x40000>; + interrupts =3D ; + phys =3D <&usbphy0>; + phy-names =3D "usb2-phy"; + resets =3D <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; + reset-names =3D "dwc2", "dwc2-ecc"; + clocks =3D <&clkmgr AGILEX5_USB2OTG_HCLK>; + clock-names =3D "otg"; + status =3D "disabled"; + }; + + watchdog0: watchdog@10d00200 { + compatible =3D "snps,dw-wdt"; + reg =3D <0x10d00200 0x100>; + interrupts =3D ; + resets =3D <&rst WATCHDOG0_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status =3D "disabled"; + }; + + watchdog1: watchdog@10d00300 { + compatible =3D "snps,dw-wdt"; + reg =3D <0x10d00300 0x100>; + interrupts =3D ; + resets =3D <&rst WATCHDOG1_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status =3D "disabled"; + }; + + watchdog2: watchdog@10d00400 { + compatible =3D "snps,dw-wdt"; + reg =3D <0x10d00400 0x100>; + interrupts =3D ; + resets =3D <&rst WATCHDOG2_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status =3D "disabled"; + }; + + watchdog3: watchdog@10d00500 { + compatible =3D "snps,dw-wdt"; + reg =3D <0x10d00500 0x100>; + interrupts =3D ; + resets =3D <&rst WATCHDOG3_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status =3D "disabled"; + }; + watchdog4: watchdog@10d00600 { + compatible =3D "snps,dw-wdt"; + reg =3D <0x10d00600 0x100>; + interrupts =3D ; + resets =3D <&rst WATCHDOG4_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status =3D "disabled"; + }; + + qspi: spi@108d2000 { + compatible =3D "intel,socfpga-qspi", "cdns,qspi-nor"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x108d2000 0x100>, + <0x10900000 0x100000>; + interrupts =3D ; + cdns,fifo-depth =3D <128>; + cdns,fifo-width =3D <4>; + cdns,trigger-address =3D <0x00000000>; + clocks =3D <&qspi_clk>; + status =3D "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm= 64/boot/dts/intel/socfpga_agilex5_socdk.dts new file mode 100644 index 000000000000..c29a6f8af1e6 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023, Intel Corporation + */ +#include "socfpga_agilex5.dtsi" + +/ { + model =3D "SoCFPGA Agilex5 SoCDK"; + compatible =3D "intel,socfpga-agilex5-socdk", "intel,socfpga-agilex"; + + aliases { + serial0 =3D &uart0; + ethernet0 =3D &gmac0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + bootargs =3D "console=3Duart8250,mmio32,0x10c02000,115200n8 \ + root=3D/dev/ram0 rw initrd=3D0x10000000 init=3D/sbin/init \ + ramdisk_size=3D10000000 earlycon=3Duart8250,mmio32,0x10c02000,115200n8 \ + panic=3D-1 nosmp rootfstype=3Dext3"; + }; + + leds { + compatible =3D "gpio-leds"; + hps0 { + label =3D "hps_led0"; + gpios =3D <&portb 20 GPIO_ACTIVE_HIGH>; + }; + + hps1 { + label =3D "hps_led1"; + gpios =3D <&portb 19 GPIO_ACTIVE_HIGH>; + }; + + hps2 { + label =3D "hps_led2"; + gpios =3D <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + + memory { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x0 0x80000000>; + #address-cells =3D <0x2>; + #size-cells =3D <0x2>; + u-boot,dm-pre-reloc; + }; +}; + +&gpio1 { + status =3D "okay"; +}; + +&gmac0 { + status =3D "okay"; + phy-mode =3D "rgmii"; + phy-handle =3D <&phy0>; + + max-frame-size =3D <9000>; + + mdio0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg =3D <0>; + }; + }; +}; + +&mmc { + status =3D "okay"; + bus-width =3D <4>; + sd-uhs-sdr50; + sdhci-caps =3D <0x00000000 0x0000c800>; + sdhci-caps-mask =3D <0x00002000 0x0000ff00>; + no-sdio; + cdns,phy-use-ext-lpbk-dqs =3D <1>; + cdns,phy-use-lpbk-dqs =3D <1>; + cdns,phy-use-phony-dqs =3D <1>; + cdns,phy-use-phony-dqs-cmd =3D <1>; + cdns,phy-io-mask-always-on =3D <0>; + cdns,phy-io-mask-end =3D <5>; + cdns,phy-io-mask-start =3D <0>; + cdns,phy-data-select-oe-end =3D <1>; + cdns,phy-sync-method =3D <1>; + cdns,phy-sw-half-cycle-shift =3D <0>; + cdns,phy-rd-del-sel =3D <52>; + cdns,phy-underrun-suppress =3D <1>; + cdns,phy-gate-cfg-always-on =3D <1>; + cdns,phy-param-dll-bypass-mode =3D <1>; + cdns,phy-param-phase-detect-sel =3D <2>; + cdns,phy-param-dll-start-point =3D <254>; + cdns,phy-read-dqs-cmd-delay =3D <0>; + cdns,phy-clk-wrdqs-delay =3D <0>; + cdns,phy-clk-wr-delay =3D <0>; + cdns,phy-read-dqs-delay =3D <0>; + cdns,phy-phony-dqs-timing =3D <0>; + cdns,hrs09-rddata-en =3D <1>; + cdns,hrs09-rdcmd-en =3D <1>; + cdns,hrs09-extended-wr-mode =3D <1>; + cdns,hrs09-extended-rd-mode =3D <1>; + cdns,hrs10-hcsdclkadj =3D <3>; + cdns,hrs16-wrdata1-sdclk-dly =3D <0>; + cdns,hrs16-wrdata0-sdclk-dly =3D <0>; + cdns,hrs16-wrcmd1-sdclk-dly =3D <0>; + cdns,hrs16-wrcmd0-sdclk-dly =3D <0>; + cdns,hrs16-wrdata1-dly =3D <0>; + cdns,hrs16-wrdata0-dly =3D <0>; + cdns,hrs16-wrcmd1-dly =3D <0>; + cdns,hrs16-wrcmd0-dly =3D <0>; + cdns,hrs07-rw-compensate =3D <10>; + cdns,hrs07-idelay-val =3D <0>; +}; + +&osc1 { + clock-frequency =3D <25000000>; +}; + +&uart0 { + status =3D "okay"; +}; + +&usb0 { + status =3D "okay"; + disable-over-current; +}; + +&watchdog0 { + status =3D "okay"; +}; + +&watchdog1 { + status =3D "okay"; +}; + +&watchdog2 { + status =3D "okay"; +}; + +&watchdog3 { + status =3D "okay"; +}; + +&watchdog4 { + status =3D "okay"; +}; + +&qspi { + status =3D "okay"; + flash@0 { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "micron,mt25qu02g", "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <100000000>; + + m25p,fast-read; + cdns,page-size =3D <256>; + cdns,block-size =3D <16>; + cdns,read-delay =3D <2>; + cdns,tshsl-ns =3D <50>; + cdns,tsd2d-ns =3D <50>; + cdns,tchsh-ns =3D <4>; + cdns,tslch-ns =3D <4>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + qspi_boot: partition@0 { + label =3D "Boot and fpga data"; + reg =3D <0x0 0x03FE0000>; + }; + + qspi_rootfs: partition@3FE0000 { + label =3D "Root Filesystem - JFFS2"; + reg =3D <0x03FE0000 0x0C020000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts b/arc= h/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts new file mode 100644 index 000000000000..0403f3859b4e --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023, Intel Corporation + */ +#include "socfpga_agilex5.dtsi" + +/ { + model =3D "SoCFPGA Agilex5 SoCDK"; + compatible =3D "intel,socfpga-agilex5-socdk", "intel,socfpga-agilex"; + + aliases { + serial0 =3D &uart0; + ethernet0 =3D &gmac0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + leds { + compatible =3D "gpio-leds"; + hps0 { + label =3D "hps_led0"; + gpios =3D <&portb 20 GPIO_ACTIVE_HIGH>; + }; + + hps1 { + label =3D "hps_led1"; + gpios =3D <&portb 19 GPIO_ACTIVE_HIGH>; + }; + + hps2 { + label =3D "hps_led2"; + gpios =3D <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + + memory { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x0 0x80000000>; + #address-cells =3D <0x2>; + #size-cells =3D <0x2>; + u-boot,dm-pre-reloc; + }; +}; + +&gpio1 { + status =3D "okay"; +}; + +&gmac0 { + status =3D "okay"; + phy-mode =3D "rgmii"; + phy-handle =3D <&phy0>; + + max-frame-size =3D <9000>; + + mdio0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg =3D <0>; + }; + }; +}; + +&osc1 { + clock-frequency =3D <25000000>; +}; + +&uart0 { + status =3D "okay"; +}; + +&watchdog0 { + status =3D "okay"; +}; + +&watchdog1 { + status =3D "okay"; +}; + +&watchdog2 { + status =3D "okay"; +}; + +&watchdog3 { + status =3D "okay"; +}; + +&watchdog4 { + status =3D "okay"; +}; + +&nand { + status =3D "okay"; + + flash@0 { + #address-cells =3D <1>; + #size-cells =3D <1>; + reg =3D <0>; + nand-bus-width =3D <16>; + + partition@0 { + label =3D "u-boot"; + reg =3D <0 0x200000>; + }; + partition@200000 { + label =3D "env"; + reg =3D <0x200000 0x40000>; + }; + partition@240000 { + label =3D "dtb"; + reg =3D <0x240000 0x40000>; + }; + partition@280000 { + label =3D "kernel"; + reg =3D <0x280000 0x2000000>; + }; + partition@2280000 { + label =3D "misc"; + reg =3D <0x2280000 0x2000000>; + }; + partition@4280000 { + label =3D "rootfs"; + reg =3D <0x4280000 0x3d80000>; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_swvp.dts b/arc= h/arm64/boot/dts/intel/socfpga_agilex5_socdk_swvp.dts new file mode 100644 index 000000000000..26a9347a23cc --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_swvp.dts @@ -0,0 +1,248 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023, Intel Corporation + */ +#include "socfpga_agilex5.dtsi" + +/ { + model =3D "SoCFPGA Agilex5 SoCDK"; + compatible =3D "intel,socfpga-agilex5-socdk", "intel,socfpga-agilex"; + + aliases { + serial0 =3D &uart0; + ethernet0 =3D &gmac0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + bootargs =3D "console=3Duart8250,mmio32,0x10c02000,115200n8 \ + root=3D/dev/ram0 rw initrd=3D0x10000000 init=3D/sbin/init \ + ramdisk_size=3D10000000 earlycon=3Duart8250,mmio32,0x10c02000,115200n8 \ + panic=3D-1 nosmp rootfstype=3Dext3"; + }; + + leds { + compatible =3D "gpio-leds"; + hps0 { + label =3D "hps_led0"; + gpios =3D <&portb 20 GPIO_ACTIVE_HIGH>; + }; + + hps1 { + label =3D "hps_led1"; + gpios =3D <&portb 19 GPIO_ACTIVE_HIGH>; + }; + + hps2 { + label =3D "hps_led2"; + gpios =3D <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + + memory { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x0 0x80000000>; + #address-cells =3D <0x2>; + #size-cells =3D <0x2>; + u-boot,dm-pre-reloc; + }; +}; + +&gpio1 { + status =3D "okay"; +}; + +&gmac0 { + status =3D "okay"; + phy-mode =3D "rgmii"; + phy-handle =3D <&phy0>; + + max-frame-size =3D <9000>; + + mdio0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg =3D <0>; + }; + }; +}; + +&mmc { + status =3D "okay"; + bus-width =3D <4>; + sd-uhs-sdr50; + sdhci-caps =3D <0x00000000 0x0000c800>; + sdhci-caps-mask =3D <0x00002000 0x0000ff00>; + no-sdio; + cdns,phy-use-ext-lpbk-dqs =3D <1>; + cdns,phy-use-lpbk-dqs =3D <1>; + cdns,phy-use-phony-dqs =3D <1>; + cdns,phy-use-phony-dqs-cmd =3D <1>; + cdns,phy-io-mask-always-on =3D <0>; + cdns,phy-io-mask-end =3D <5>; + cdns,phy-io-mask-start =3D <0>; + cdns,phy-data-select-oe-end =3D <1>; + cdns,phy-sync-method =3D <1>; + cdns,phy-sw-half-cycle-shift =3D <0>; + cdns,phy-rd-del-sel =3D <52>; + cdns,phy-underrun-suppress =3D <1>; + cdns,phy-gate-cfg-always-on =3D <1>; + cdns,phy-param-dll-bypass-mode =3D <1>; + cdns,phy-param-phase-detect-sel =3D <2>; + cdns,phy-param-dll-start-point =3D <254>; + cdns,phy-read-dqs-cmd-delay =3D <0>; + cdns,phy-clk-wrdqs-delay =3D <0>; + cdns,phy-clk-wr-delay =3D <0>; + cdns,phy-read-dqs-delay =3D <0>; + cdns,phy-phony-dqs-timing =3D <0>; + cdns,hrs09-rddata-en =3D <1>; + cdns,hrs09-rdcmd-en =3D <1>; + cdns,hrs09-extended-wr-mode =3D <1>; + cdns,hrs09-extended-rd-mode =3D <1>; + cdns,hrs10-hcsdclkadj =3D <3>; + cdns,hrs16-wrdata1-sdclk-dly =3D <0>; + cdns,hrs16-wrdata0-sdclk-dly =3D <0>; + cdns,hrs16-wrcmd1-sdclk-dly =3D <0>; + cdns,hrs16-wrcmd0-sdclk-dly =3D <0>; + cdns,hrs16-wrdata1-dly =3D <0>; + cdns,hrs16-wrdata0-dly =3D <0>; + cdns,hrs16-wrcmd1-dly =3D <0>; + cdns,hrs16-wrcmd0-dly =3D <0>; + cdns,hrs07-rw-compensate =3D <10>; + cdns,hrs07-idelay-val =3D <0>; +}; + +&i2c0 { + status =3D "okay"; +}; + +&i2c1 { + status =3D "okay"; +}; + +&i2c2 { + status =3D "okay"; +}; + +&i2c3 { + status =3D "okay"; +}; + +&i2c4 { + status =3D "okay"; +}; + +&i3c0 { + status =3D "okay"; +}; + +&i3c1 { + status =3D "okay"; +}; + +&osc1 { + clock-frequency =3D <25000000>; +}; + +&uart0 { + status =3D "okay"; +}; + +&usb0 { + status =3D "okay"; + disable-over-current; +}; + +&watchdog0 { + status =3D "okay"; +}; + +&watchdog1 { + status =3D "okay"; +}; + +&watchdog2 { + status =3D "okay"; +}; + +&watchdog3 { + status =3D "okay"; +}; + +&watchdog4 { + status =3D "okay"; +}; + +&qspi { + status =3D "okay"; + flash@0 { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "micron,mt25qu02g", "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <100000000>; + + m25p,fast-read; + cdns,page-size =3D <256>; + cdns,block-size =3D <16>; + cdns,read-delay =3D <2>; + cdns,tshsl-ns =3D <50>; + cdns,tsd2d-ns =3D <50>; + cdns,tchsh-ns =3D <4>; + cdns,tslch-ns =3D <4>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + qspi_boot: partition@0 { + label =3D "Boot and fpga data"; + reg =3D <0x0 0x03FE0000>; + }; + + qspi_rootfs: partition@3FE0000 { + label =3D "Root Filesystem - JFFS2"; + reg =3D <0x03FE0000 0x0C020000>; + }; + }; + }; +}; + +&nand { + status =3D "okay"; + + flash@0 { + #address-cells =3D <1>; + #size-cells =3D <1>; + reg =3D <0>; + nand-bus-width =3D <16>; + + partition@0 { + label =3D "u-boot"; + reg =3D <0 0x200000>; + }; + partition@200000 { + label =3D "env"; + reg =3D <0x200000 0x40000>; + }; + partition@240000 { + label =3D "dtb"; + reg =3D <0x240000 0x40000>; + }; + partition@280000 { + label =3D "kernel"; + reg =3D <0x280000 0x2000000>; + }; + partition@2280000 { + label =3D "misc"; + reg =3D <0x2280000 0x2000000>; + }; + partition@4280000 { + label =3D "rootfs"; + reg =3D <0x4280000 0x3d80000>; + }; + }; +}; --=20 2.25.1