From nobody Sun Feb 8 04:11:31 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D712CEB64D7 for ; Sun, 18 Jun 2023 13:23:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229716AbjFRNX1 (ORCPT ); Sun, 18 Jun 2023 09:23:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229614AbjFRNXY (ORCPT ); Sun, 18 Jun 2023 09:23:24 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 82E2F1BF; Sun, 18 Jun 2023 06:23:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1687094594; x=1718630594; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=LfyquutmidP2HJP0MsNOnHSnrpomrzgZpCbNNI6rJfE=; b=keViApPzZAEQ+PgFh1Ey9q2vrs4BT+Tm0XKeNqr2eKJRKtkFIorq5IZT Zb/ALF/YkBGu1BYixywGydhaFPC8NLbTz36GY0svfWF/F+ymVnn2raVLX uMXg45qq5N+XHtJ3vMrHES2To0bBWtsikQUr9X7ApSwzI4nlYkrMcpArx t5Cz4REuGISryvO1+p/0mgVqGpA214xGwaKSeIQppnXOucR9sk+QKCpBA 8zMxGLgsKUSdfu4scYOjyeJGmylWG7usxCKNg3EcSBJvPSXRqkIzndL0h vRsAIhpAJiPXeKJUEHypofv8VIv/xZjlRO8pM5+RXf47p72hpcd8faVzd Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10745"; a="356967043" X-IronPort-AV: E=Sophos;i="6.00,252,1681196400"; d="scan'208";a="356967043" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2023 06:23:14 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10745"; a="747146765" X-IronPort-AV: E=Sophos;i="6.00,252,1681196400"; d="scan'208";a="747146765" Received: from unknown (HELO localhost.localdomain) ([10.226.216.116]) by orsmga001.jf.intel.com with ESMTP; 18 Jun 2023 06:23:09 -0700 From: niravkumar.l.rabara@intel.com To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Niravkumar L Rabara , Andrew Lunn , Dinh Nguyen , Michael Turquette , Stephen Boyd , Philipp Zabel , Wen Ping , Richard Cochran , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, netdev@vger.kernel.org, Adrian Ng Ho Yin Subject: [PATCH 1/4] dt-bindings: intel: Add Intel Agilex5 compatible Date: Sun, 18 Jun 2023 21:22:32 +0800 Message-Id: <20230618132235.728641-2-niravkumar.l.rabara@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230618132235.728641-1-niravkumar.l.rabara@intel.com> References: <20230618132235.728641-1-niravkumar.l.rabara@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Niravkumar L Rabara Add new compatible for Intel Agilex5 based boards. Signed-off-by: Niravkumar L Rabara --- Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Doc= umentation/devicetree/bindings/arm/intel,socfpga.yaml index 4b4dcf551eb6..28849c720314 100644 --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml @@ -20,6 +20,7 @@ properties: - intel,n5x-socdk - intel,socfpga-agilex-n6000 - intel,socfpga-agilex-socdk + - intel,socfpga-agilex5-socdk - const: intel,socfpga-agilex =20 additionalProperties: true --=20 2.25.1 From nobody Sun Feb 8 04:11:31 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D54D4EB64DB for ; Sun, 18 Jun 2023 13:23:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229720AbjFRNXi (ORCPT ); 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X-IronPort-AV: E=McAfee;i="6600,9927,10745"; a="356967059" X-IronPort-AV: E=Sophos;i="6.00,252,1681196400"; d="scan'208";a="356967059" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2023 06:23:19 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10745"; a="747146795" X-IronPort-AV: E=Sophos;i="6.00,252,1681196400"; d="scan'208";a="747146795" Received: from unknown (HELO localhost.localdomain) ([10.226.216.116]) by orsmga001.jf.intel.com with ESMTP; 18 Jun 2023 06:23:15 -0700 From: niravkumar.l.rabara@intel.com To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Niravkumar L Rabara , Andrew Lunn , Dinh Nguyen , Michael Turquette , Stephen Boyd , Philipp Zabel , Wen Ping , Richard Cochran , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, netdev@vger.kernel.org, Adrian Ng Ho Yin Subject: [PATCH 2/4] dt-bindings: clock: Add Intel Agilex5 clocks and resets Date: Sun, 18 Jun 2023 21:22:33 +0800 Message-Id: <20230618132235.728641-3-niravkumar.l.rabara@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230618132235.728641-1-niravkumar.l.rabara@intel.com> References: <20230618132235.728641-1-niravkumar.l.rabara@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Niravkumar L Rabara Add clock and reset ID definitions for Intel Agilex5 SoCFPGA Co-developed-by: Teh Wen Ping Signed-off-by: Teh Wen Ping Signed-off-by: Niravkumar L Rabara --- .../bindings/clock/intel,agilex5.yaml | 42 ++++++++ include/dt-bindings/clock/agilex5-clock.h | 100 ++++++++++++++++++ .../dt-bindings/reset/altr,rst-mgr-agilex5.h | 79 ++++++++++++++ 3 files changed, 221 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex5.y= aml create mode 100644 include/dt-bindings/clock/agilex5-clock.h create mode 100644 include/dt-bindings/reset/altr,rst-mgr-agilex5.h diff --git a/Documentation/devicetree/bindings/clock/intel,agilex5.yaml b/D= ocumentation/devicetree/bindings/clock/intel,agilex5.yaml new file mode 100644 index 000000000000..e408c52deefa --- /dev/null +++ b/Documentation/devicetree/bindings/clock/intel,agilex5.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/intel,agilex5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel SoCFPGA Agilex5 platform clock controller binding + +maintainers: + - Teh Wen Ping + - Niravkumar L Rabara + +description: + The Intel Agilex5 Clock controller is an integrated clock controller, wh= ich + generates and supplies to all modules. + +properties: + compatible: + const: intel,agilex5-clkmgr + + '#clock-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + # Clock controller node: + - | + clkmgr: clock-controller@10d10000 { + compatible =3D "intel,agilex5-clkmgr"; + reg =3D <0x10d10000 0x1000>; + #clock-cells =3D <1>; + }; +... diff --git a/include/dt-bindings/clock/agilex5-clock.h b/include/dt-binding= s/clock/agilex5-clock.h new file mode 100644 index 000000000000..4505b352cd83 --- /dev/null +++ b/include/dt-bindings/clock/agilex5-clock.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (C) 2022, Intel Corporation + */ + +#ifndef __AGILEX5_CLOCK_H +#define __AGILEX5_CLOCK_H + +/* fixed rate clocks */ +#define AGILEX5_OSC1 0 +#define AGILEX5_CB_INTOSC_HS_DIV2_CLK 1 +#define AGILEX5_CB_INTOSC_LS_CLK 2 +#define AGILEX5_F2S_FREE_CLK 3 + +/* PLL clocks */ +#define AGILEX5_MAIN_PLL_CLK 4 +#define AGILEX5_MAIN_PLL_C0_CLK 5 +#define AGILEX5_MAIN_PLL_C1_CLK 6 +#define AGILEX5_MAIN_PLL_C2_CLK 7 +#define AGILEX5_MAIN_PLL_C3_CLK 8 +#define AGILEX5_PERIPH_PLL_CLK 9 +#define AGILEX5_PERIPH_PLL_C0_CLK 10 +#define AGILEX5_PERIPH_PLL_C1_CLK 11 +#define AGILEX5_PERIPH_PLL_C2_CLK 12 +#define AGILEX5_PERIPH_PLL_C3_CLK 13 +#define AGILEX5_CORE0_FREE_CLK 14 +#define AGILEX5_CORE1_FREE_CLK 15 +#define AGILEX5_CORE2_FREE_CLK 16 +#define AGILEX5_CORE3_FREE_CLK 17 +#define AGILEX5_DSU_FREE_CLK 18 +#define AGILEX5_BOOT_CLK 19 + +/* fixed factor clocks */ +#define AGILEX5_L3_MAIN_FREE_CLK 20 +#define AGILEX5_NOC_FREE_CLK 21 +#define AGILEX5_S2F_USR0_CLK 22 +#define AGILEX5_NOC_CLK 23 +#define AGILEX5_EMAC_A_FREE_CLK 24 +#define AGILEX5_EMAC_B_FREE_CLK 25 +#define AGILEX5_EMAC_PTP_FREE_CLK 26 +#define AGILEX5_GPIO_DB_FREE_CLK 27 +#define AGILEX5_S2F_USER0_FREE_CLK 28 +#define AGILEX5_S2F_USER1_FREE_CLK 29 +#define AGILEX5_PSI_REF_FREE_CLK 30 +#define AGILEX5_USB31_FREE_CLK 31 + +/* Gate clocks */ +#define AGILEX5_CORE0_CLK 32 +#define AGILEX5_CORE1_CLK 33 +#define AGILEX5_CORE2_CLK 34 +#define AGILEX5_CORE3_CLK 35 +#define AGILEX5_MPU_CLK 36 +#define AGILEX5_MPU_PERIPH_CLK 37 +#define AGILEX5_MPU_CCU_CLK 38 +#define AGILEX5_L4_MAIN_CLK 39 +#define AGILEX5_L4_MP_CLK 40 +#define AGILEX5_L4_SYS_FREE_CLK 41 +#define AGILEX5_L4_SP_CLK 42 +#define AGILEX5_CS_AT_CLK 43 +#define AGILEX5_CS_TRACE_CLK 44 +#define AGILEX5_CS_PDBG_CLK 45 +#define AGILEX5_EMAC1_CLK 47 +#define AGILEX5_EMAC2_CLK 48 +#define AGILEX5_EMAC_PTP_CLK 49 +#define AGILEX5_GPIO_DB_CLK 50 +#define AGILEX5_S2F_USER0_CLK 51 +#define AGILEX5_S2F_USER1_CLK 52 +#define AGILEX5_PSI_REF_CLK 53 +#define AGILEX5_USB31_SUSPEND_CLK 54 +#define AGILEX5_EMAC0_CLK 46 +#define AGILEX5_USB31_BUS_CLK_EARLY 55 +#define AGILEX5_USB2OTG_HCLK 56 +#define AGILEX5_SPIM_0_CLK 57 +#define AGILEX5_SPIM_1_CLK 58 +#define AGILEX5_SPIS_0_CLK 59 +#define AGILEX5_SPIS_1_CLK 60 +#define AGILEX5_DMA_CORE_CLK 61 +#define AGILEX5_DMA_HS_CLK 62 +#define AGILEX5_I3C_0_CORE_CLK 63 +#define AGILEX5_I3C_1_CORE_CLK 64 +#define AGILEX5_I2C_0_PCLK 65 +#define AGILEX5_I2C_1_PCLK 66 +#define AGILEX5_I2C_EMAC0_PCLK 67 +#define AGILEX5_I2C_EMAC1_PCLK 68 +#define AGILEX5_I2C_EMAC2_PCLK 69 +#define AGILEX5_UART_0_PCLK 70 +#define AGILEX5_UART_1_PCLK 71 +#define AGILEX5_SPTIMER_0_PCLK 72 +#define AGILEX5_SPTIMER_1_PCLK 73 +#define AGILEX5_DFI_CLK 74 +#define AGILEX5_NAND_NF_CLK 75 +#define AGILEX5_NAND_BCH_CLK 76 +#define AGILEX5_SDMMC_SDPHY_REG_CLK 77 +#define AGILEX5_SDMCLK 78 +#define AGILEX5_SOFTPHY_REG_PCLK 79 +#define AGILEX5_SOFTPHY_PHY_CLK 80 +#define AGILEX5_SOFTPHY_CTRL_CLK 81 +#define AGILEX5_NUM_CLKS 82 + +#endif /* __AGILEX5_CLOCK_H */ diff --git a/include/dt-bindings/reset/altr,rst-mgr-agilex5.h b/include/dt-= bindings/reset/altr,rst-mgr-agilex5.h new file mode 100644 index 000000000000..81e5e8c89893 --- /dev/null +++ b/include/dt-bindings/reset/altr,rst-mgr-agilex5.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (C) 2023 Intel Corporation. All rights reserved + * + */ + +#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_AGILEX5_H +#define _DT_BINDINGS_RESET_ALTR_RST_MGR_AGILEX5_H + +/* PER0MODRST */ +#define EMAC0_RESET 32 +#define EMAC1_RESET 33 +#define EMAC2_RESET 34 +#define USB0_RESET 35 +#define USB1_RESET 36 +#define NAND_RESET 37 +#define SOFT_PHY_RESET 38 +#define SDMMC_RESET 39 +#define EMAC0_OCP_RESET 40 +#define EMAC1_OCP_RESET 41 +#define EMAC2_OCP_RESET 42 +#define USB0_OCP_RESET 43 +#define USB1_OCP_RESET 44 +#define NAND_OCP_RESET 45 +/* 46 is empty */ +#define SDMMC_OCP_RESET 47 +#define DMA_RESET 48 +#define SPIM0_RESET 49 +#define SPIM1_RESET 50 +#define SPIS0_RESET 51 +#define SPIS1_RESET 52 +#define DMA_OCP_RESET 53 +#define EMAC_PTP_RESET 54 +/* 55 is empty*/ +#define DMAIF0_RESET 56 +#define DMAIF1_RESET 57 +#define DMAIF2_RESET 58 +#define DMAIF3_RESET 59 +#define DMAIF4_RESET 60 +#define DMAIF5_RESET 61 +#define DMAIF6_RESET 62 +#define DMAIF7_RESET 63 + +/* PER1MODRST */ +#define WATCHDOG0_RESET 64 +#define WATCHDOG1_RESET 65 +#define WATCHDOG2_RESET 66 +#define WATCHDOG3_RESET 67 +#define L4SYSTIMER0_RESET 68 +#define L4SYSTIMER1_RESET 69 +#define SPTIMER0_RESET 70 +#define SPTIMER1_RESET 71 +#define I2C0_RESET 72 +#define I2C1_RESET 73 +#define I2C2_RESET 74 +#define I2C3_RESET 75 +#define I2C4_RESET 76 +#define I3C0_RESET 77 +#define I3C1_RESET 78 +/* 79 is empty */ +#define UART0_RESET 80 +#define UART1_RESET 81 +/* 82-87 is empty */ +#define GPIO0_RESET 88 +#define GPIO1_RESET 89 +#define WATCHDOG4_RESET 90 + +/* BRGMODRST */ +#define SOC2FPGA_RESET 96 +#define LWHPS2FPGA_RESET 97 +#define FPGA2SOC_RESET 98 +#define F2SSDRAM0_RESET 99 +/* 100-101 is empty */ +#define MPFE_RESET 102 + +/* DBGMODRST */ +#define DBG_RESET 128 + +#endif --=20 2.25.1 From nobody Sun Feb 8 04:11:31 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE295EB64DB for ; Sun, 18 Jun 2023 13:24:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229729AbjFRNYA (ORCPT ); Sun, 18 Jun 2023 09:24:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40496 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229743AbjFRNXs (ORCPT ); Sun, 18 Jun 2023 09:23:48 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7DEC81707; Sun, 18 Jun 2023 06:23:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1687094606; x=1718630606; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=EztM/IITrGnmWIEpYsLp2Lhfj42tfhV8RF4RYXaJeFM=; b=lNEBuzJMp8iEQj1xWVssmkCzuZVn0dnapXAqTMBP8XGIU2eAd+9+OJHQ gghY0q+0Cl7rP8BwfmYDRNBdrF2REBvmRp/uvI2sQ2ZIw4w3DK0AG1C2D L3Zo8e7qUgL8tTKov6VszeuNagohIk9NdjQXueRkh+PyPiDvslVSPp2+/ IgDSHm1iCQ4r6pnV6hUXlaNy2fyXgdH2cG01Rm4VPg2MjYn4H5hViynDr k+jkDF+iC3wRDoMqI5JPx0hGZqCYLMvF5957PiL0vHNuchkFYR+3Xiwu0 qe4E6PD5fnVtbzaYmZ9JrRRUFIOkbagZ11M6JL5igKKKKHerBnjBv1+85 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10745"; a="356967078" X-IronPort-AV: E=Sophos;i="6.00,252,1681196400"; d="scan'208";a="356967078" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2023 06:23:25 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10745"; a="747146839" X-IronPort-AV: E=Sophos;i="6.00,252,1681196400"; d="scan'208";a="747146839" Received: from unknown (HELO localhost.localdomain) ([10.226.216.116]) by orsmga001.jf.intel.com with ESMTP; 18 Jun 2023 06:23:20 -0700 From: niravkumar.l.rabara@intel.com To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Niravkumar L Rabara , Andrew Lunn , Dinh Nguyen , Michael Turquette , Stephen Boyd , Philipp Zabel , Wen Ping , Richard Cochran , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, netdev@vger.kernel.org, Adrian Ng Ho Yin Subject: [PATCH 3/4] clk: socfpga: agilex5: Add clock driver for Agilex5 platform Date: Sun, 18 Jun 2023 21:22:34 +0800 Message-Id: <20230618132235.728641-4-niravkumar.l.rabara@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230618132235.728641-1-niravkumar.l.rabara@intel.com> References: <20230618132235.728641-1-niravkumar.l.rabara@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Niravkumar L Rabara The clock manager driver for Agilex5 is very similar to the Agilex platform. This patch makes the necessary changes for the driver to differentiate between the Agilex and the Agilex5 platforms. Signed-off-by: Teh Wen Ping Signed-off-by: Niravkumar L Rabara --- drivers/clk/socfpga/Kconfig | 4 +- drivers/clk/socfpga/Makefile | 2 +- drivers/clk/socfpga/clk-agilex5.c | 843 ++++++++++++++++++++++++++++ drivers/clk/socfpga/clk-pll-s10.c | 48 ++ drivers/clk/socfpga/stratix10-clk.h | 2 + 5 files changed, 896 insertions(+), 3 deletions(-) create mode 100644 drivers/clk/socfpga/clk-agilex5.c diff --git a/drivers/clk/socfpga/Kconfig b/drivers/clk/socfpga/Kconfig index 0cf16b894efb..e82c0cda3245 100644 --- a/drivers/clk/socfpga/Kconfig +++ b/drivers/clk/socfpga/Kconfig @@ -4,7 +4,7 @@ config CLK_INTEL_SOCFPGA default ARCH_INTEL_SOCFPGA help Support for the clock controllers present on Intel SoCFPGA and eASIC - devices like Aria, Cyclone, Stratix 10, Agilex and N5X eASIC. + devices like Aria, Cyclone, Stratix 10, Agilex, N5X eASIC and Agilex5. =20 if CLK_INTEL_SOCFPGA =20 @@ -13,7 +13,7 @@ config CLK_INTEL_SOCFPGA32 default ARM && ARCH_INTEL_SOCFPGA =20 config CLK_INTEL_SOCFPGA64 - bool "Intel Stratix / Agilex / N5X clock controller support" if COMPILE_T= EST && (!ARM64 || !ARCH_INTEL_SOCFPGA) + bool "Intel Stratix / Agilex / N5X clock / Agilex5 controller support" if= COMPILE_TEST && (!ARM64 || !ARCH_INTEL_SOCFPGA) default ARM64 && ARCH_INTEL_SOCFPGA =20 endif # CLK_INTEL_SOCFPGA diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile index e8dfce339c91..a1ea2b988eaf 100644 --- a/drivers/clk/socfpga/Makefile +++ b/drivers/clk/socfpga/Makefile @@ -3,4 +3,4 @@ obj-$(CONFIG_CLK_INTEL_SOCFPGA32) +=3D clk.o clk-gate.o clk= -pll.o clk-periph.o \ clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o obj-$(CONFIG_CLK_INTEL_SOCFPGA64) +=3D clk-s10.o \ clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o \ - clk-agilex.o + clk-agilex.o clk-agilex5.o diff --git a/drivers/clk/socfpga/clk-agilex5.c b/drivers/clk/socfpga/clk-ag= ilex5.c new file mode 100644 index 000000000000..2d597176a98d --- /dev/null +++ b/drivers/clk/socfpga/clk-agilex5.c @@ -0,0 +1,843 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022, Intel Corporation + */ +#include +#include +#include +#include +#include + +#include + +#include "stratix10-clk.h" + +static const struct clk_parent_data pll_mux[] =3D { + { + .fw_name =3D "osc1", + .name =3D "osc1", + }, + { + .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", + }, + { + .fw_name =3D "f2s-free-clk", + .name =3D "f2s-free-clk", + }, +}; + +static const struct clk_parent_data boot_mux[] =3D { + { + .fw_name =3D "osc1", + .name =3D "osc1", + }, + { + .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", + }, +}; + +static const struct clk_parent_data core0_free_mux[] =3D { + { + .fw_name =3D "main_pll_c1", + .name =3D "main_pll_c1", + }, + { + .fw_name =3D "peri_pll_c0", + .name =3D "peri_pll_c0", + }, + { + .fw_name =3D "osc1", + .name =3D "osc1", + }, + { + .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", + }, + { + .fw_name =3D "f2s-free-clk", + .name =3D "f2s-free-clk", + }, +}; + +static const struct clk_parent_data core1_free_mux[] =3D { + { + .fw_name =3D "main_pll_c1", + .name =3D "main_pll_c1", + }, + { + .fw_name =3D "peri_pll_c0", + .name =3D "peri_pll_c0", + }, + { + .fw_name =3D "osc1", + .name =3D "osc1", + }, + { + .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", + }, + { + .fw_name =3D "f2s-free-clk", + .name =3D "f2s-free-clk", + }, +}; + +static const struct clk_parent_data core2_free_mux[] =3D { + { + .fw_name =3D "main_pll_c0", + .name =3D "main_pll_c0", + }, + { + .fw_name =3D "osc1", + .name =3D "osc1", + }, + { + .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", + }, + { + .fw_name =3D "f2s-free-clk", + .name =3D "f2s-free-clk", + }, +}; + +static const struct clk_parent_data core3_free_mux[] =3D { + { + .fw_name =3D "main_pll_c0", + .name =3D "main_pll_c0", + }, + { + .fw_name =3D "osc1", + .name =3D "osc1", + }, + { + .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", + }, + { + .fw_name =3D "f2s-free-clk", + .name =3D "f2s-free-clk", + }, +}; + +static const struct clk_parent_data dsu_free_mux[] =3D { + { + .fw_name =3D "main_pll_c2", + .name =3D "main_pll_c2", + }, + { + .fw_name =3D "peri_pll_c0", + .name =3D "peri_pll_c0", + }, + { + .fw_name =3D "osc1", + .name =3D "osc1", + }, + { + .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", + }, + { + .fw_name =3D "f2s-free-clk", + .name =3D "f2s-free-clk", + }, +}; + +static const struct clk_parent_data noc_free_mux[] =3D { + { + .fw_name =3D "main_pll_c3", + .name =3D "main_pll_c3", + }, + { + .fw_name =3D "peri_pll_c1", + .name =3D "peri_pll_c1", + }, + { + .fw_name =3D "osc1", + .name =3D "osc1", + }, + { + .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", + }, + { + .fw_name =3D "f2s-free-clk", + .name =3D "f2s-free-clk", + }, +}; + +static const struct clk_parent_data emaca_free_mux[] =3D { + { + .fw_name =3D "main_pll_c1", + .name =3D "main_pll_c1", + }, + { + .fw_name =3D "peri_pll_c3", + .name =3D "peri_pll_c3", + }, + { + .fw_name =3D "osc1", + .name =3D "osc1", + }, + { + .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", + }, + { + .fw_name =3D "f2s-free-clk", + .name =3D "f2s-free-clk", + }, +}; + +static const struct clk_parent_data emacb_free_mux[] =3D { + { + .fw_name =3D "main_pll_c1", + .name =3D "main_pll_c1", + }, + { + .fw_name =3D "peri_pll_c3", + .name =3D "peri_pll_c3", + }, + { + .fw_name =3D "osc1", + .name =3D "osc1", + }, + { + .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", + }, + { + .fw_name =3D "f2s-free-clk", + .name =3D "f2s-free-clk", + }, +}; + +static const struct clk_parent_data emac_ptp_free_mux[] =3D { + { + .fw_name =3D "main_pll_c1", + .name =3D "main_pll_c1", + }, + { + .fw_name =3D "peri_pll_c3", + .name =3D "peri_pll_c3", + }, + { + .fw_name =3D "osc1", + .name =3D "osc1", + }, + { + .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", + }, + { + .fw_name =3D "f2s-free-clk", + .name =3D "f2s-free-clk", + }, +}; + +static const struct clk_parent_data gpio_db_free_mux[] =3D { + { + .fw_name =3D "main_pll_c3", + .name =3D "main_pll_c3", + }, + { + .fw_name =3D "peri_pll_c1", + .name =3D "peri_pll_c1", + }, + { + .fw_name =3D "osc1", + .name =3D "osc1", + }, + { + .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", + }, + { + .fw_name =3D "f2s-free-clk", + .name =3D "f2s-free-clk", + }, +}; + +static const struct clk_parent_data psi_ref_free_mux[] =3D { + { + .fw_name =3D "main_pll_c1", + .name =3D "main_pll_c1", + }, + { + .fw_name =3D "peri_pll_c3", + .name =3D "peri_pll_c3", + }, + { + .fw_name =3D "osc1", + .name =3D "osc1", + }, + { + .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", + }, + { + .fw_name =3D "f2s-free-clk", + .name =3D "f2s-free-clk", + }, +}; + +static const struct clk_parent_data usb31_free_mux[] =3D { + { + .fw_name =3D "main_pll_c3", + .name =3D "main_pll_c3", + }, + { + .fw_name =3D "peri_pll_c2", + .name =3D "peri_pll_c2", + }, + { + .fw_name =3D "osc1", + .name =3D "osc1", + }, + { + .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", + }, + { + .fw_name =3D "f2s-free-clk", + .name =3D "f2s-free-clk", + }, +}; + +static const struct clk_parent_data s2f_usr0_free_mux[] =3D { + { + .fw_name =3D "main_pll_c1", + .name =3D "main_pll_c1", + }, + { + .fw_name =3D "peri_pll_c3", + .name =3D "peri_pll_c3", + }, + { + .fw_name =3D "osc1", + .name =3D "osc1", + }, + { + .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", + }, + { + .fw_name =3D "f2s-free-clk", + .name =3D "f2s-free-clk", + }, +}; + +static const struct clk_parent_data s2f_usr1_free_mux[] =3D { + { + .fw_name =3D "main_pll_c1", + .name =3D "main_pll_c1", + }, + { + .fw_name =3D "peri_pll_c3", + .name =3D "peri_pll_c3", + }, + { + .fw_name =3D "osc1", + .name =3D "osc1", + }, + { + .fw_name =3D "cb-intosc-hs-div2-clk", + .name =3D "cb-intosc-hs-div2-clk", + }, + { + .fw_name =3D "f2s-free-clk", + .name =3D "f2s-free-clk", + }, +}; + +static const struct clk_parent_data core0_mux[] =3D { + { + .fw_name =3D "core0_free_clk", + .name =3D "core0_free_clk", + }, + { + .fw_name =3D "boot_clk", + .name =3D "boot_clk", + }, +}; + +static const struct clk_parent_data core1_mux[] =3D { + { + .fw_name =3D "core1_free_clk", + .name =3D "core1_free_clk", + }, + { + .fw_name =3D "boot_clk", + .name =3D "boot_clk", + }, +}; + +static const struct clk_parent_data core2_mux[] =3D { + { + .fw_name =3D "core2_free_clk", + .name =3D "core2_free_clk", + }, + { + .fw_name =3D "boot_clk", + .name =3D "boot_clk", + }, +}; + +static const struct clk_parent_data core3_mux[] =3D { + { + .fw_name =3D "core3_free_clk", + .name =3D "core3_free_clk", + }, + { + .fw_name =3D "boot_clk", + .name =3D "boot_clk", + }, +}; + +static const struct clk_parent_data dsu_mux[] =3D { + { + .fw_name =3D "dsu_free_clk", + .name =3D "dsu_free_clk", + }, + { + .fw_name =3D "boot_clk", + .name =3D "boot_clk", + }, +}; + +static const struct clk_parent_data emac_mux[] =3D { + { + .fw_name =3D "emaca_free_clk", + .name =3D "emaca_free_clk", + }, + { + .fw_name =3D "emacb_free_clk", + .name =3D "emacb_free_clk", + }, + { + .fw_name =3D "boot_clk", + .name =3D "boot_clk", + }, +}; + +static const struct clk_parent_data noc_mux[] =3D { + { + .fw_name =3D "noc_free_clk", + .name =3D "noc_free_clk", + }, + { + .fw_name =3D "boot_clk", + .name =3D "boot_clk", + }, +}; + +static const struct clk_parent_data s2f_user0_mux[] =3D { + { + .fw_name =3D "s2f_user0_free_clk", + .name =3D "s2f_user0_free_clk", + }, + { + .fw_name =3D "boot_clk", + .name =3D "boot_clk", + }, +}; + +static const struct clk_parent_data s2f_user1_mux[] =3D { + { + .fw_name =3D "s2f_user1_free_clk", + .name =3D "s2f_user1_free_clk", + }, + { + .fw_name =3D "boot_clk", + .name =3D "boot_clk", + }, +}; + +static const struct clk_parent_data psi_mux[] =3D { + { + .fw_name =3D "psi_ref_free_clk", + .name =3D "psi_ref_free_clk", + }, + { + .fw_name =3D "boot_clk", + .name =3D "boot_clk", + }, +}; + +static const struct clk_parent_data gpio_db_mux[] =3D { + { + .fw_name =3D "gpio_db_free_clk", + .name =3D "gpio_db_free_clk", + }, + { + .fw_name =3D "boot_clk", + .name =3D "boot_clk", + }, +}; + +static const struct clk_parent_data emac_ptp_mux[] =3D { + { + .fw_name =3D "emac_ptp_free_clk", + .name =3D "emac_ptp_free_clk", + }, + { + .fw_name =3D "boot_clk", + .name =3D "boot_clk", + }, +}; + +static const struct clk_parent_data usb31_mux[] =3D { + { + .fw_name =3D "usb31_free_clk", + .name =3D "usb31_free_clk", + }, + { + .fw_name =3D "boot_clk", + .name =3D "boot_clk", + }, +}; + +/* + * TODO - Clocks in AO (always on) controller + * 2 main PLLs only + */ +static const struct stratix10_pll_clock agilex5_pll_clks[] =3D { + { AGILEX5_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0, + 0x0 }, + { AGILEX5_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux), 0, + 0x48 }, + { AGILEX5_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux), 0, + 0x9C }, +}; + +static const struct stratix10_perip_c_clock agilex5_main_perip_c_clks[] = =3D { + { AGILEX5_MAIN_PLL_C0_CLK, "main_pll_c0", "main_pll", NULL, 1, 0, + 0x5C }, + { AGILEX5_MAIN_PLL_C1_CLK, "main_pll_c1", "main_pll", NULL, 1, 0, + 0x60 }, + { AGILEX5_MAIN_PLL_C2_CLK, "main_pll_c2", "main_pll", NULL, 1, 0, + 0x64 }, + { AGILEX5_MAIN_PLL_C3_CLK, "main_pll_c3", "main_pll", NULL, 1, 0, + 0x68 }, + { AGILEX5_PERIPH_PLL_C0_CLK, "peri_pll_c0", "periph_pll", NULL, 1, 0, + 0xB0 }, + { AGILEX5_PERIPH_PLL_C1_CLK, "peri_pll_c1", "periph_pll", NULL, 1, 0, + 0xB4 }, + { AGILEX5_PERIPH_PLL_C2_CLK, "peri_pll_c2", "periph_pll", NULL, 1, 0, + 0xB8 }, + { AGILEX5_PERIPH_PLL_C3_CLK, "peri_pll_c3", "periph_pll", NULL, 1, 0, + 0xBC }, +}; + +/* Non-SW clock-gated enabled clocks */ +static const struct stratix10_perip_cnt_clock agilex5_main_perip_cnt_clks[= ] =3D { + { AGILEX5_CORE0_FREE_CLK, "core0_free_clk", NULL, core0_free_mux, + ARRAY_SIZE(core0_free_mux), 0, 0x0104, 0, 0, 0}, + { AGILEX5_CORE1_FREE_CLK, "core1_free_clk", NULL, core1_free_mux, + ARRAY_SIZE(core1_free_mux), 0, 0x0104, 0, 0, 0}, + { AGILEX5_CORE2_FREE_CLK, "core2_free_clk", NULL, core2_free_mux, + ARRAY_SIZE(core2_free_mux), 0, 0x010C, 0, 0, 0}, + { AGILEX5_CORE3_FREE_CLK, "core3_free_clk", NULL, core3_free_mux, + ARRAY_SIZE(core3_free_mux), 0, 0x0110, 0, 0, 0}, + { AGILEX5_DSU_FREE_CLK, "dsu_free_clk", NULL, dsu_free_mux, + ARRAY_SIZE(dsu_free_mux), 0, 0x0100, 0, 0, 0}, + { AGILEX5_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, + ARRAY_SIZE(noc_free_mux), 0, 0x40, 0, 0, 0 }, + { AGILEX5_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, + ARRAY_SIZE(emaca_free_mux), 0, 0xD4, 0, 0x88, 0 }, + { AGILEX5_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, + ARRAY_SIZE(emacb_free_mux), 0, 0xD8, 0, 0x88, 1 }, + { AGILEX5_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL, + emac_ptp_free_mux, ARRAY_SIZE(emac_ptp_free_mux), 0, 0xDC, 0, 0x88, + 2 }, + { AGILEX5_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux, + ARRAY_SIZE(gpio_db_free_mux), 0, 0xE0, 0, 0x88, 3 }, + { AGILEX5_S2F_USER0_FREE_CLK, "s2f_user0_free_clk", NULL, + s2f_usr0_free_mux, ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0x30, + 2 }, + { AGILEX5_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, + s2f_usr1_free_mux, ARRAY_SIZE(s2f_usr1_free_mux), 0, 0xEC, 0, 0x88, + 5 }, + { AGILEX5_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux, + ARRAY_SIZE(psi_ref_free_mux), 0, 0xF0, 0, 0x88, 6 }, + { AGILEX5_USB31_FREE_CLK, "usb31_free_clk", NULL, usb31_free_mux, + ARRAY_SIZE(usb31_free_mux), 0, 0xF8, 0, 0x88, 7}, +}; + +/* SW Clock gate enabled clocks */ +static const struct stratix10_gate_clock agilex5_gate_clks[] =3D { + /* Main PLL0 Begin */ + /* MPU clocks */ + { AGILEX5_CORE0_CLK, "core0_clk", NULL, core0_mux, + ARRAY_SIZE(core0_mux), 0, 0x24, 8, 0, 0, 0, 0x30, 5, 0 }, + { AGILEX5_CORE1_CLK, "core1_clk", NULL, core1_mux, + ARRAY_SIZE(core1_mux), 0, 0x24, 9, 0, 0, 0, 0x30, 5, 0 }, + { AGILEX5_CORE2_CLK, "core2_clk", NULL, core2_mux, + ARRAY_SIZE(core2_mux), 0, 0x24, 10, 0, 0, 0, 0x30, 6, 0 }, + { AGILEX5_CORE3_CLK, "core3_clk", NULL, core3_mux, + ARRAY_SIZE(core3_mux), 0, 0x24, 11, 0, 0, 0, 0x30, 7, 0 }, + { AGILEX5_MPU_CLK, "dsu_clk", NULL, dsu_mux, ARRAY_SIZE(dsu_mux), 0, 0, + 0, 0, 0, 0, 0x34, 4, 0 }, + { AGILEX5_MPU_PERIPH_CLK, "mpu_periph_clk", NULL, dsu_mux, + ARRAY_SIZE(dsu_mux), 0, 0, 0, 0x44, 20, 2, 0x34, 4, 0 }, + { AGILEX5_MPU_CCU_CLK, "mpu_ccu_clk", NULL, dsu_mux, + ARRAY_SIZE(dsu_mux), 0, 0, 0, 0x44, 18, 2, 0x34, 4, 0 }, + + /* l4 main clk has no divider now */ + { AGILEX5_L4_MAIN_CLK, "l4_main_clk", NULL, noc_mux, + ARRAY_SIZE(noc_mux), 0, 0x24, 1, 0, 0, 0, 0, 0, 0 }, + { AGILEX5_L4_MP_CLK, "l4_mp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, + 0x24, 2, 0x44, 4, 2, 0x30, 1, 0 }, + { AGILEX5_L4_SYS_FREE_CLK, "l4_sys_free_clk", NULL, noc_mux, + ARRAY_SIZE(noc_mux), 0, 0, 0, 0x44, 2, 2, 0x30, 1, 0 }, + { AGILEX5_L4_SP_CLK, "l4_sp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), + CLK_IS_CRITICAL, 0x24, 3, 0x44, 6, 2, 0x30, 1, 0 }, + + /* Core sight clocks*/ + { AGILEX5_CS_AT_CLK, "cs_at_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, + 0x24, 4, 0x44, 24, 2, 0x30, 1, 0 }, + { AGILEX5_CS_TRACE_CLK, "cs_trace_clk", NULL, noc_mux, + ARRAY_SIZE(noc_mux), 0, 0x24, 4, 0x44, 26, 2, 0x30, 1, 0 }, + { AGILEX5_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x24, 4, + 0x44, 28, 1, 0, 0, 0 }, + /* Main PLL0 End */ + + /* Main Peripheral PLL1 Begin */ + { AGILEX5_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), + 0, 0x7C, 0, 0, 0, 0, 0x94, 26, 0 }, + { AGILEX5_EMAC1_CLK, "emac1_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), + 0, 0x7C, 1, 0, 0, 0, 0x94, 27, 0 }, + { AGILEX5_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), + 0, 0x7C, 2, 0, 0, 0, 0x94, 28, 0 }, + { AGILEX5_EMAC_PTP_CLK, "emac_ptp_clk", NULL, emac_ptp_mux, + ARRAY_SIZE(emac_ptp_mux), 0, 0x7C, 3, 0, 0, 0, 0x88, 2, 0 }, + { AGILEX5_GPIO_DB_CLK, "gpio_db_clk", NULL, gpio_db_mux, + ARRAY_SIZE(gpio_db_mux), 0, 0x7C, 4, 0x98, 0, 16, 0x88, 3, 0 }, + /* Main Peripheral PLL1 End */ + + /* Peripheral clocks */ + { AGILEX5_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_user0_mux, + ARRAY_SIZE(s2f_user0_mux), 0, 0x24, 6, 0, 0, 0, 0x30, 2, 0 }, + { AGILEX5_S2F_USER1_CLK, "s2f_user1_clk", NULL, s2f_user1_mux, + ARRAY_SIZE(s2f_user1_mux), 0, 0x7C, 6, 0, 0, 0, 0x88, 5, 0 }, + { AGILEX5_PSI_REF_CLK, "psi_ref_clk", NULL, psi_mux, + ARRAY_SIZE(psi_mux), 0, 0x7C, 7, 0, 0, 0, 0x88, 6, 0 }, + { AGILEX5_USB31_SUSPEND_CLK, "usb31_suspend_clk", NULL, usb31_mux, + ARRAY_SIZE(usb31_mux), 0, 0x7C, 25, 0, 0, 0, 0x88, 7, 0 }, + { AGILEX5_USB31_BUS_CLK_EARLY, "usb31_bus_clk_early", "l4_main_clk", + NULL, 1, 0, 0x7C, 25, 0, 0, 0, 0, 0, 0 }, + { AGILEX5_USB2OTG_HCLK, "usb2otg_hclk", "l4_mp_clk", NULL, 1, 0, 0x7C, + 8, 0, 0, 0, 0, 0, 0 }, + { AGILEX5_SPIM_0_CLK, "spim_0_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, 9, + 0, 0, 0, 0, 0, 0 }, + { AGILEX5_SPIM_1_CLK, "spim_1_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, 11, + 0, 0, 0, 0, 0, 0 }, + { AGILEX5_SPIS_0_CLK, "spis_0_clk", "l4_sp_clk", NULL, 1, 0, 0x7C, 12, + 0, 0, 0, 0, 0, 0 }, + { AGILEX5_SPIS_1_CLK, "spis_1_clk", "l4_sp_clk", NULL, 1, 0, 0x7C, 13, + 0, 0, 0, 0, 0, 0 }, + { AGILEX5_DMA_CORE_CLK, "dma_core_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, + 14, 0, 0, 0, 0, 0, 0 }, + { AGILEX5_DMA_HS_CLK, "dma_hs_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, 14, + 0, 0, 0, 0, 0, 0 }, + { AGILEX5_I3C_0_CORE_CLK, "i3c_0_core_clk", "l4_mp_clk", NULL, 1, 0, + 0x7C, 18, 0, 0, 0, 0, 0, 0 }, + { AGILEX5_I3C_1_CORE_CLK, "i3c_1_core_clk", "l4_mp_clk", NULL, 1, 0, + 0x7C, 19, 0, 0, 0, 0, 0, 0 }, + { AGILEX5_I2C_0_PCLK, "i2c_0_pclk", "l4_sp_clk", NULL, 1, 0, 0x7C, 15, + 0, 0, 0, 0, 0, 0 }, + { AGILEX5_I2C_1_PCLK, "i2c_1_pclk", "l4_sp_clk", NULL, 1, 0, 0x7C, 16, + 0, 0, 0, 0, 0, 0 }, + { AGILEX5_I2C_EMAC0_PCLK, "i2c_emac0_pclk", "l4_sp_clk", NULL, 1, 0, + 0x7C, 17, 0, 0, 0, 0, 0, 0 }, + { AGILEX5_I2C_EMAC1_PCLK, "i2c_emac1_pclk", "l4_sp_clk", NULL, 1, 0, + 0x7C, 22, 0, 0, 0, 0, 0, 0 }, + { AGILEX5_I2C_EMAC2_PCLK, "i2c_emac2_pclk", "l4_sp_clk", NULL, 1, 0, + 0x7C, 27, 0, 0, 0, 0, 0, 0 }, + { AGILEX5_UART_0_PCLK, "uart_0_pclk", "l4_sp_clk", NULL, 1, 0, 0x7C, 20, + 0, 0, 0, 0, 0, 0 }, + { AGILEX5_UART_1_PCLK, "uart_1_pclk", "l4_sp_clk", NULL, 1, 0, 0x7C, 21, + 0, 0, 0, 0, 0, 0 }, + { AGILEX5_SPTIMER_0_PCLK, "sptimer_0_pclk", "l4_sp_clk", NULL, 1, 0, + 0x7C, 23, 0, 0, 0, 0, 0, 0 }, + { AGILEX5_SPTIMER_1_PCLK, "sptimer_1_pclk", "l4_sp_clk", NULL, 1, 0, + 0x7C, 24, 0, 0, 0, 0, 0, 0 }, + + /*NAND, SD/MMC and SoftPHY overall clocking*/ + { AGILEX5_DFI_CLK, "dfi_clk", "l4_mp_clk", NULL, 1, 0, 0, 0, 0x44, 16, + 2, 0, 0, 0 }, + { AGILEX5_NAND_NF_CLK, "nand_nf_clk", "dfi_clk", NULL, 1, 0, 0x7C, 10, + 0, 0, 0, 0, 0, 0 }, + { AGILEX5_NAND_BCH_CLK, "nand_bch_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, + 10, 0, 0, 0, 0, 0, 0 }, + { AGILEX5_SDMMC_SDPHY_REG_CLK, "sdmmc_sdphy_reg_clk", "l4_mp_clk", NULL, + 1, 0, 0x7C, 5, 0, 0, 0, 0, 0, 0 }, + { AGILEX5_SDMCLK, "sdmclk", "dfi_clk", NULL, 1, 0, 0x7C, 5, 0, 0, 0, 0, + 0, 0 }, + { AGILEX5_SOFTPHY_REG_PCLK, "softphy_reg_pclk", "l4_mp_clk", NULL, 1, 0, + 0x7C, 26, 0, 0, 0, 0, 0, 0 }, + { AGILEX5_SOFTPHY_PHY_CLK, "softphy_phy_clk", "l4_mp_clk", NULL, 1, 0, + 0x7C, 26, 0x44, 16, 2, 0, 0, 0 }, + { AGILEX5_SOFTPHY_CTRL_CLK, "softphy_ctrl_clk", "dfi_clk", NULL, 1, 0, + 0x7C, 26, 0, 0, 0, 0, 0, 0 }, +}; + +static int +agilex5_clk_register_c_perip(const struct stratix10_perip_c_clock *clks, + int nums, struct stratix10_clock_data *data) +{ + struct clk_hw *hw_clk; + void __iomem *base =3D data->base; + int i; + + for (i =3D 0; i < nums; i++) { + hw_clk =3D s10_register_periph(&clks[i], base); + if (IS_ERR(hw_clk)) { + pr_err("%s: failed to register clock %s\n", __func__, + clks[i].name); + continue; + } + data->clk_data.hws[clks[i].id] =3D hw_clk; + } + return 0; +} + +static int +agilex5_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clk= s, + int nums, struct stratix10_clock_data *data) +{ + struct clk_hw *hw_clk; + void __iomem *base =3D data->base; + int i; + + for (i =3D 0; i < nums; i++) { + hw_clk =3D s10_register_cnt_periph(&clks[i], base); + if (IS_ERR(hw_clk)) { + pr_err("%s: failed to register clock %s\n", __func__, + clks[i].name); + continue; + } + data->clk_data.hws[clks[i].id] =3D hw_clk; + } + + return 0; +} + +static int agilex5_clk_register_gate(const struct stratix10_gate_clock *cl= ks, + int nums, + struct stratix10_clock_data *data) +{ + struct clk_hw *hw_clk; + void __iomem *base =3D data->base; + int i; + + for (i =3D 0; i < nums; i++) { + hw_clk =3D agilex_register_gate(&clks[i], base); + if (IS_ERR(hw_clk)) { + pr_err("%s: failed to register clock %s\n", __func__, + clks[i].name); + continue; + } + data->clk_data.hws[clks[i].id] =3D hw_clk; + } + + return 0; +} + +static int agilex5_clk_register_pll(const struct stratix10_pll_clock *clks, + int nums, struct stratix10_clock_data *data) +{ + struct clk_hw *hw_clk; + void __iomem *base =3D data->base; + int i; + + for (i =3D 0; i < nums; i++) { + hw_clk =3D agilex5_register_pll(&clks[i], base); + if (IS_ERR(hw_clk)) { + pr_err("%s: failed to register clock %s\n", __func__, + clks[i].name); + continue; + } + data->clk_data.hws[clks[i].id] =3D hw_clk; + } + + return 0; +} + +static int agilex5_clkmgr_init(struct platform_device *pdev) +{ + struct device_node *np =3D pdev->dev.of_node; + struct device *dev =3D &pdev->dev; + struct stratix10_clock_data *clk_data; + struct resource *res; + void __iomem *base; + int i, num_clks; + + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + base =3D devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + num_clks =3D AGILEX5_NUM_CLKS; + + clk_data =3D devm_kzalloc(dev, + struct_size(clk_data, clk_data.hws, num_clks), + GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + for (i =3D 0; i < num_clks; i++) + clk_data->clk_data.hws[i] =3D ERR_PTR(-ENOENT); + + clk_data->base =3D base; + clk_data->clk_data.num =3D num_clks; + + agilex5_clk_register_pll(agilex5_pll_clks, ARRAY_SIZE(agilex5_pll_clks), + clk_data); + + agilex5_clk_register_c_perip(agilex5_main_perip_c_clks, + ARRAY_SIZE(agilex5_main_perip_c_clks), + clk_data); + + agilex5_clk_register_cnt_perip(agilex5_main_perip_cnt_clks, + ARRAY_SIZE(agilex5_main_perip_cnt_clks), + clk_data); + + agilex5_clk_register_gate(agilex5_gate_clks, + ARRAY_SIZE(agilex5_gate_clks), clk_data); + + of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data); + return 0; +} + +static int agilex5_clkmgr_probe(struct platform_device *pdev) +{ + int (*probe_func)(struct platform_device *init_func); + + probe_func =3D of_device_get_match_data(&pdev->dev); + if (!probe_func) + return -ENODEV; + return probe_func(pdev); +} + +static const struct of_device_id agilex5_clkmgr_match_table[] =3D { + { .compatible =3D "intel,agilex5-clkmgr", .data =3D agilex5_clkmgr_init }, + {} +}; + +static struct platform_driver agilex5_clkmgr_driver =3D { + .probe =3D agilex5_clkmgr_probe, + .driver =3D { + .name =3D "agilex5-clkmgr", + .suppress_bind_attrs =3D true, + .of_match_table =3D agilex5_clkmgr_match_table, + }, +}; + +static int __init agilex5_clk_init(void) +{ + return platform_driver_register(&agilex5_clkmgr_driver); +} +core_initcall(agilex5_clk_init); diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pl= l-s10.c index 1d82737befd3..e3367d34bc55 100644 --- a/drivers/clk/socfpga/clk-pll-s10.c +++ b/drivers/clk/socfpga/clk-pll-s10.c @@ -175,6 +175,14 @@ static const struct clk_ops agilex_clk_pll_ops =3D { .prepare =3D clk_pll_prepare, }; =20 +/* TODO need to fix, Agilex5 SM requires change */ +static const struct clk_ops agilex5_clk_pll_ops =3D { + /* TODO This may require a custom Agilex5 implementation */ + .recalc_rate =3D agilex_clk_pll_recalc_rate, + .get_parent =3D clk_pll_get_parent, + .prepare =3D clk_pll_prepare, +}; + static const struct clk_ops clk_pll_ops =3D { .recalc_rate =3D clk_pll_recalc_rate, .get_parent =3D clk_pll_get_parent, @@ -304,3 +312,43 @@ struct clk_hw *n5x_register_pll(const struct stratix10= _pll_clock *clks, } return hw_clk; } + +struct clk_hw *agilex5_register_pll(const struct stratix10_pll_clock *clks, + void __iomem *reg) +{ + struct clk_hw *hw_clk; + struct socfpga_pll *pll_clk; + struct clk_init_data init; + const char *name =3D clks->name; + int ret; + + pll_clk =3D kzalloc(sizeof(*pll_clk), GFP_KERNEL); + if (WARN_ON(!pll_clk)) + return NULL; + + pll_clk->hw.reg =3D reg + clks->offset; + + if (streq(name, SOCFPGA_BOOT_CLK)) + init.ops =3D &clk_boot_ops; + else + init.ops =3D &agilex5_clk_pll_ops; + + init.name =3D name; + init.flags =3D clks->flags; + + init.num_parents =3D clks->num_parents; + init.parent_names =3D NULL; + init.parent_data =3D clks->parent_data; + pll_clk->hw.hw.init =3D &init; + + pll_clk->hw.bit_idx =3D SOCFPGA_PLL_POWER; + hw_clk =3D &pll_clk->hw.hw; + + ret =3D clk_hw_register(NULL, hw_clk); + if (ret) { + kfree(pll_clk); + return ERR_PTR(ret); + } + return hw_clk; +} + diff --git a/drivers/clk/socfpga/stratix10-clk.h b/drivers/clk/socfpga/stra= tix10-clk.h index 75234e0783e1..468e0f0ab4ab 100644 --- a/drivers/clk/socfpga/stratix10-clk.h +++ b/drivers/clk/socfpga/stratix10-clk.h @@ -77,6 +77,8 @@ struct clk_hw *agilex_register_pll(const struct stratix10= _pll_clock *clks, void __iomem *reg); struct clk_hw *n5x_register_pll(const struct stratix10_pll_clock *clks, void __iomem *reg); +struct clk_hw *agilex5_register_pll(const struct stratix10_pll_clock *clks, + void __iomem *reg); struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *c= lks, void __iomem *reg); struct clk_hw *n5x_register_periph(const struct n5x_perip_c_clock *clks, --=20 2.25.1 From nobody Sun Feb 8 04:11:31 2026 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From: niravkumar.l.rabara@intel.com To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Niravkumar L Rabara , Andrew Lunn , Dinh Nguyen , Michael Turquette , Stephen Boyd , Philipp Zabel , Wen Ping , Richard Cochran , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, netdev@vger.kernel.org, Adrian Ng Ho Yin Subject: [PATCH 4/4] arm64: dts: agilex5: Add initial support for Intel's Agilex5 SoCFPGA Date: Sun, 18 Jun 2023 21:22:35 +0800 Message-Id: <20230618132235.728641-5-niravkumar.l.rabara@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230618132235.728641-1-niravkumar.l.rabara@intel.com> References: <20230618132235.728641-1-niravkumar.l.rabara@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Niravkumar L Rabara Add the initial device tree files for Intel's Agilex5 SoCFPGA platform. Signed-off-by: Adrian Ng Ho Yin Signed-off-by: Niravkumar L Rabara --- arch/arm64/boot/dts/intel/Makefile | 3 + .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 641 ++++++++++++++++++ .../boot/dts/intel/socfpga_agilex5_socdk.dts | 184 +++++ .../dts/intel/socfpga_agilex5_socdk_nand.dts | 131 ++++ .../dts/intel/socfpga_agilex5_socdk_swvp.dts | 248 +++++++ 5 files changed, 1207 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_swvp.dts diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel= /Makefile index c2a723838344..bb74a7e30e58 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -2,5 +2,8 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) +=3D socfpga_agilex_n6000.dtb \ socfpga_agilex_socdk.dtb \ socfpga_agilex_socdk_nand.dtb \ + socfpga_agilex5_socdk.dtb \ + socfpga_agilex5_socdk_nand.dtb \ + socfpga_agilex5_socdk_swvp.dtb \ socfpga_n5x_socdk.dtb dtb-$(CONFIG_ARCH_KEEMBAY) +=3D keembay-evm.dtb diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/bo= ot/dts/intel/socfpga_agilex5.dtsi new file mode 100644 index 000000000000..9454d88d6457 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -0,0 +1,641 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023, Intel Corporation + */ + +/dts-v1/; +#include +#include +#include +#include +#include + +/ { + compatible =3D "intel,socfpga-agilex"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + service_reserved: svcbuffer@0 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0x80000000 0x0 0x2000000>; + alignment =3D <0x1000>; + no-map; + }; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a55"; + device_type =3D "cpu"; + enable-method =3D "psci"; + reg =3D <0x0>; + }; + + cpu1: cpu@1 { + compatible =3D "arm,cortex-a55"; + device_type =3D "cpu"; + enable-method =3D "psci"; + reg =3D <0x100>; + }; + + cpu2: cpu@2 { + compatible =3D "arm,cortex-a76"; + device_type =3D "cpu"; + enable-method =3D "psci"; + reg =3D <0x200>; + }; + + cpu3: cpu@3 { + compatible =3D "arm,cortex-a76"; + device_type =3D "cpu"; + enable-method =3D "psci"; + reg =3D <0x300>; + }; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + intc: interrupt-controller@1d000000 { + compatible =3D "arm,gic-v3", "arm,cortex-a15-gic"; + #interrupt-cells =3D <3>; + #address-cells =3D <2>; + #size-cells =3D<2>; + interrupt-controller; + #redistributor-regions =3D <1>; + label =3D "GIC"; + status =3D "okay"; + ranges; + redistributor-stride =3D <0x0 0x20000>; + reg =3D <0x0 0x1d000000 0 0x10000>, + <0x0 0x1d060000 0 0x100000>; + + its: msi-controller@1d040000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x1d040000 0x0 0x20000>; + label =3D "ITS"; + msi-controller; + status =3D "okay"; + }; + }; + + /* Clock tree 5 main sources*/ + clocks { + cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + }; + + cb_intosc_ls_clk: cb-intosc-ls-clk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + }; + + f2s_free_clk: f2s-free-clk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + }; + + osc1: osc1 { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + }; + + qspi_clk: qspi-clk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <200000000>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&intc>; + interrupts =3D , + , + , + ; + }; + + usbphy0: usbphy { + #phy-cells =3D <0>; + compatible =3D "usb-nop-xceiv"; + }; + + soc { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "simple-bus"; + device_type =3D "soc"; + interrupt-parent =3D <&intc>; + ranges =3D <0 0 0 0xffffffff>; + + clkmgr: clock-controller@10d10000 { + compatible =3D "intel,agilex5-clkmgr"; + reg =3D <0x10d10000 0x1000>; + #clock-cells =3D <1>; + }; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt =3D <31>; + snps,rd_osr_lmt =3D <31>; + snps,blen =3D <0 0 0 32 16 8 4>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <8>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x1>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x2>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x3>; + }; + queue4 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x4>; + }; + queue5 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x5>; + }; + queue6 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x6>; + }; + queue7 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x7>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <8>; + snps,tx-sched-wrr; + queue0 { + snps,weight =3D <0x09>; + snps,dcb-algorithm; + }; + queue1 { + snps,weight =3D <0x0A>; + snps,dcb-algorithm; + }; + queue2 { + snps,weight =3D <0x0B>; + snps,dcb-algorithm; + }; + queue3 { + snps,weight =3D <0x0C>; + snps,dcb-algorithm; + }; + queue4 { + snps,weight =3D <0x0D>; + snps,dcb-algorithm; + }; + queue5 { + snps,weight =3D <0x0E>; + snps,dcb-algorithm; + }; + queue6 { + snps,weight =3D <0x0F>; + snps,dcb-algorithm; + }; + queue7 { + snps,weight =3D <0x10>; + snps,dcb-algorithm; + }; + }; + + gmac0: ethernet@10810000 { + compatible =3D "altr,socfpga-stmmac-a10-s10", + "snps,dwxgmac-2.10", + "snps,dwxgmac"; + reg =3D <0x10810000 0x3500>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "macirq", + "macirq_tx0", + "macirq_tx1", + "macirq_tx2", + "macirq_tx3", + "macirq_tx4", + "macirq_tx5", + "macirq_tx6", + "macirq_tx7", + "macirq_rx0", + "macirq_rx1", + "macirq_rx2", + "macirq_rx3", + "macirq_rx4", + "macirq_rx5", + "macirq_rx6", + "macirq_rx7"; + mac-address =3D [00 00 00 00 00 00]; + resets =3D <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; + reset-names =3D "stmmaceth", "stmmaceth-ocp"; + tx-fifo-depth =3D <32768>; + rx-fifo-depth =3D <16384>; + snps,multicast-filter-bins =3D <64>; + snps,perfect-filter-entries =3D <64>; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,mtl-rx-config =3D <&mtl_rx_setup>; + snps,mtl-tx-config =3D <&mtl_tx_setup>; + snps,pbl =3D <32>; + snps,pblx8; + snps,multi-irq-en; + snps,tso; + altr,sysmgr-syscon =3D <&sysmgr 0x44 0>; + altr,smtg-hub; + snps,rx-vlan-offload; + clocks =3D <&clkmgr AGILEX5_EMAC0_CLK>, <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names =3D "stmmaceth", "ptp_ref"; + status =3D "disabled"; + }; + + i2c0: i2c@10c02800 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,designware-i2c"; + reg =3D <0x10c02800 0x100>; + interrupts =3D ; + resets =3D <&rst I2C0_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + status =3D "disabled"; + }; + + i2c1: i2c@10c02900 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,designware-i2c"; + reg =3D <0x10c02900 0x100>; + interrupts =3D ; + resets =3D <&rst I2C1_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + status =3D "disabled"; + }; + + i2c2: i2c@10c02a00 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,designware-i2c"; + reg =3D <0x10c02a00 0x100>; + interrupts =3D ; + resets =3D <&rst I2C2_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + status =3D "disabled"; + }; + + i2c3: i2c@10c02b00 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,designware-i2c"; + reg =3D <0x10c02b00 0x100>; + interrupts =3D ; + resets =3D <&rst I2C3_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + status =3D "disabled"; + }; + + i2c4: i2c@10c02c00 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,designware-i2c"; + reg =3D <0x10c02c00 0x100>; + interrupts =3D ; + resets =3D <&rst I2C4_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + status =3D "disabled"; + }; + + i3c0: i3c@10da0000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dw-i3c-master-1.00a"; + reg =3D <0x10da0000 0x1000>; + interrupts =3D ; + resets =3D <&rst I3C0_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_MP_CLK>; + status =3D "disabled"; + }; + + i3c1: i3c@10da1000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dw-i3c-master-1.00a"; + reg =3D <0x10da1000 0x1000>; + interrupts =3D ; + resets =3D <&rst I3C1_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_MP_CLK>; + status =3D "disabled"; + }; + + gpio1: gpio@10C03300 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0x10C03300 0x100>; + resets =3D <&rst GPIO1_RESET>; + status =3D "disabled"; + + portb: gpio-controller@0 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <24>; + reg =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D ; + }; + }; + + mmc: mmc0@10808000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "cdns,sd4hc"; + reg =3D <0x10808000 0x1000>; + interrupts =3D ; + fifo-depth =3D <0x800>; + resets =3D <&rst SDMMC_RESET>; + reset-names =3D "reset"; + clocks =3D <&clkmgr AGILEX5_L4_MP_CLK>, <&clkmgr AGILEX5_SDMCLK>; + clock-names =3D "biu", "ciu"; + /*iommus =3D <&smmu 5>;*/ + status =3D "disabled"; + }; + + nand: nand-controller@10b80000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "cdns,hp-nfc"; + reg =3D <0x10b80000 0x10000>, + <0x10840000 0x1000>; + reg-names =3D "reg", "sdma"; + interrupts =3D ; + clocks =3D <&clkmgr AGILEX5_NAND_NF_CLK>; + clock-names =3D "nf_clk"; + cdns,board-delay-ps =3D <4830>; + status =3D "disabled"; + }; + + ocram: sram@00000000 { + compatible =3D "mmio-sram"; + reg =3D <0x00000000 0x40000>; + }; + + dmac0: dma-controller@10DB0000 { + compatible =3D "snps,axi-dma-1.01a"; + reg =3D <0x10DB0000 0x500>; + clocks =3D <&clkmgr AGILEX5_L4_MAIN_CLK>, + <&clkmgr AGILEX5_L4_MP_CLK>; + clock-names =3D "core-clk", "cfgr-clk"; + interrupt-parent =3D <&intc>; + interrupts =3D ; + #dma-cells =3D <1>; + dma-channels =3D <4>; + snps,dma-masters =3D <1>; + snps,data-width =3D <2>; + snps,block-size =3D <32767 32767 32767 32767>; + snps,priority =3D <0 1 2 3>; + snps,axi-max-burst-len =3D <8>; + status =3D "okay"; + }; + + dmac1: dma-controller@10DC0000 { + compatible =3D "snps,axi-dma-1.01a"; + reg =3D <0x10DC0000 0x500>; + clocks =3D <&clkmgr AGILEX5_L4_MAIN_CLK>, + <&clkmgr AGILEX5_L4_MP_CLK>; + clock-names =3D "core-clk", "cfgr-clk"; + interrupt-parent =3D <&intc>; + interrupts =3D ; + #dma-cells =3D <1>; + dma-channels =3D <4>; + snps,dma-masters =3D <1>; + snps,data-width =3D <2>; + snps,block-size =3D <32767 32767 32767 32767>; + snps,priority =3D <0 1 2 3>; + snps,axi-max-burst-len =3D <8>; + status =3D "okay"; + }; + + rst: rstmgr@10d11000 { + #reset-cells =3D <1>; + compatible =3D "altr,stratix10-rst-mgr"; + reg =3D <0x10d11000 0x100>; + }; + + spi0: spi@10da4000 { + compatible =3D "snps,dw-apb-ssi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x10da4000 0x1000>; + interrupts =3D ; + resets =3D <&rst SPIM0_RESET>; + reset-names =3D "spi"; + reg-io-width =3D <4>; + num-cs =3D <4>; + clocks =3D <&clkmgr AGILEX5_L4_MAIN_CLK>; + dmas =3D <&dmac0 2>, <&dmac0 3>; + dma-names =3D"tx", "rx"; + + status =3D "disabled"; + + flash: m25p128@0 { + status =3D "okay"; + compatible =3D "st,m25p80"; + spi-max-frequency =3D <25000000>; + m25p,fast-read; + reg =3D <0>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "spi_flash_part0"; + reg =3D <0x0 0x100000>; + }; + }; + + }; + + spi1: spi@10da5000 { + compatible =3D "snps,dw-apb-ssi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x10da5000 0x1000>; + interrupts =3D ; + resets =3D <&rst SPIM1_RESET>; + reset-names =3D "spi"; + reg-io-width =3D <4>; + num-cs =3D <4>; + clocks =3D <&clkmgr AGILEX5_L4_MAIN_CLK>; + status =3D "disabled"; + }; + + sysmgr: sysmgr@10d12000 { + compatible =3D "altr,sys-mgr-s10","altr,sys-mgr"; + reg =3D <0x10d12000 0x500>; + }; + + timer0: timer0@10c03000 { + compatible =3D "snps,dw-apb-timer"; + interrupts =3D ; + reg =3D <0x10c03000 0x100>; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names =3D "timer"; + }; + + timer1: timer1@10c03100 { + compatible =3D "snps,dw-apb-timer"; + interrupts =3D ; + reg =3D <0x10c03100 0x100>; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names =3D "timer"; + }; + + timer2: timer2@10d00000 { + compatible =3D "snps,dw-apb-timer"; + interrupts =3D ; + reg =3D <0x10d00000 0x100>; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names =3D "timer"; + }; + + timer3: timer3@10d00100 { + compatible =3D "snps,dw-apb-timer"; + interrupts =3D ; + reg =3D <0x10d00100 0x100>; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names =3D "timer"; + }; + + uart0: serial@10c02000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x10c02000 0x100>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + resets =3D <&rst UART0_RESET>; + status =3D "disabled"; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + }; + + uart1: serial@10c02100 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x10c02100 0x100>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + resets =3D <&rst UART1_RESET>; + status =3D "disabled"; + clocks =3D <&clkmgr AGILEX5_L4_SP_CLK>; + }; + + usb0: usb@10b00000 { + compatible =3D "snps,dwc2"; + reg =3D <0x10b00000 0x40000>; + interrupts =3D ; + phys =3D <&usbphy0>; + phy-names =3D "usb2-phy"; + resets =3D <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; + reset-names =3D "dwc2", "dwc2-ecc"; + clocks =3D <&clkmgr AGILEX5_USB2OTG_HCLK>; + clock-names =3D "otg"; + status =3D "disabled"; + }; + + watchdog0: watchdog@10d00200 { + compatible =3D "snps,dw-wdt"; + reg =3D <0x10d00200 0x100>; + interrupts =3D ; + resets =3D <&rst WATCHDOG0_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status =3D "disabled"; + }; + + watchdog1: watchdog@10d00300 { + compatible =3D "snps,dw-wdt"; + reg =3D <0x10d00300 0x100>; + interrupts =3D ; + resets =3D <&rst WATCHDOG1_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status =3D "disabled"; + }; + + watchdog2: watchdog@10d00400 { + compatible =3D "snps,dw-wdt"; + reg =3D <0x10d00400 0x100>; + interrupts =3D ; + resets =3D <&rst WATCHDOG2_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status =3D "disabled"; + }; + + watchdog3: watchdog@10d00500 { + compatible =3D "snps,dw-wdt"; + reg =3D <0x10d00500 0x100>; + interrupts =3D ; + resets =3D <&rst WATCHDOG3_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status =3D "disabled"; + }; + watchdog4: watchdog@10d00600 { + compatible =3D "snps,dw-wdt"; + reg =3D <0x10d00600 0x100>; + interrupts =3D ; + resets =3D <&rst WATCHDOG4_RESET>; + clocks =3D <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status =3D "disabled"; + }; + + qspi: spi@108d2000 { + compatible =3D "intel,socfpga-qspi", "cdns,qspi-nor"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x108d2000 0x100>, + <0x10900000 0x100000>; + interrupts =3D ; + cdns,fifo-depth =3D <128>; + cdns,fifo-width =3D <4>; + cdns,trigger-address =3D <0x00000000>; + clocks =3D <&qspi_clk>; + status =3D "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm= 64/boot/dts/intel/socfpga_agilex5_socdk.dts new file mode 100644 index 000000000000..c29a6f8af1e6 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023, Intel Corporation + */ +#include "socfpga_agilex5.dtsi" + +/ { + model =3D "SoCFPGA Agilex5 SoCDK"; + compatible =3D "intel,socfpga-agilex5-socdk", "intel,socfpga-agilex"; + + aliases { + serial0 =3D &uart0; + ethernet0 =3D &gmac0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + bootargs =3D "console=3Duart8250,mmio32,0x10c02000,115200n8 \ + root=3D/dev/ram0 rw initrd=3D0x10000000 init=3D/sbin/init \ + ramdisk_size=3D10000000 earlycon=3Duart8250,mmio32,0x10c02000,115200n8 \ + panic=3D-1 nosmp rootfstype=3Dext3"; + }; + + leds { + compatible =3D "gpio-leds"; + hps0 { + label =3D "hps_led0"; + gpios =3D <&portb 20 GPIO_ACTIVE_HIGH>; + }; + + hps1 { + label =3D "hps_led1"; + gpios =3D <&portb 19 GPIO_ACTIVE_HIGH>; + }; + + hps2 { + label =3D "hps_led2"; + gpios =3D <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + + memory { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x0 0x80000000>; + #address-cells =3D <0x2>; + #size-cells =3D <0x2>; + u-boot,dm-pre-reloc; + }; +}; + +&gpio1 { + status =3D "okay"; +}; + +&gmac0 { + status =3D "okay"; + phy-mode =3D "rgmii"; + phy-handle =3D <&phy0>; + + max-frame-size =3D <9000>; + + mdio0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg =3D <0>; + }; + }; +}; + +&mmc { + status =3D "okay"; + bus-width =3D <4>; + sd-uhs-sdr50; + sdhci-caps =3D <0x00000000 0x0000c800>; + sdhci-caps-mask =3D <0x00002000 0x0000ff00>; + no-sdio; + cdns,phy-use-ext-lpbk-dqs =3D <1>; + cdns,phy-use-lpbk-dqs =3D <1>; + cdns,phy-use-phony-dqs =3D <1>; + cdns,phy-use-phony-dqs-cmd =3D <1>; + cdns,phy-io-mask-always-on =3D <0>; + cdns,phy-io-mask-end =3D <5>; + cdns,phy-io-mask-start =3D <0>; + cdns,phy-data-select-oe-end =3D <1>; + cdns,phy-sync-method =3D <1>; + cdns,phy-sw-half-cycle-shift =3D <0>; + cdns,phy-rd-del-sel =3D <52>; + cdns,phy-underrun-suppress =3D <1>; + cdns,phy-gate-cfg-always-on =3D <1>; + cdns,phy-param-dll-bypass-mode =3D <1>; + cdns,phy-param-phase-detect-sel =3D <2>; + cdns,phy-param-dll-start-point =3D <254>; + cdns,phy-read-dqs-cmd-delay =3D <0>; + cdns,phy-clk-wrdqs-delay =3D <0>; + cdns,phy-clk-wr-delay =3D <0>; + cdns,phy-read-dqs-delay =3D <0>; + cdns,phy-phony-dqs-timing =3D <0>; + cdns,hrs09-rddata-en =3D <1>; + cdns,hrs09-rdcmd-en =3D <1>; + cdns,hrs09-extended-wr-mode =3D <1>; + cdns,hrs09-extended-rd-mode =3D <1>; + cdns,hrs10-hcsdclkadj =3D <3>; + cdns,hrs16-wrdata1-sdclk-dly =3D <0>; + cdns,hrs16-wrdata0-sdclk-dly =3D <0>; + cdns,hrs16-wrcmd1-sdclk-dly =3D <0>; + cdns,hrs16-wrcmd0-sdclk-dly =3D <0>; + cdns,hrs16-wrdata1-dly =3D <0>; + cdns,hrs16-wrdata0-dly =3D <0>; + cdns,hrs16-wrcmd1-dly =3D <0>; + cdns,hrs16-wrcmd0-dly =3D <0>; + cdns,hrs07-rw-compensate =3D <10>; + cdns,hrs07-idelay-val =3D <0>; +}; + +&osc1 { + clock-frequency =3D <25000000>; +}; + +&uart0 { + status =3D "okay"; +}; + +&usb0 { + status =3D "okay"; + disable-over-current; +}; + +&watchdog0 { + status =3D "okay"; +}; + +&watchdog1 { + status =3D "okay"; +}; + +&watchdog2 { + status =3D "okay"; +}; + +&watchdog3 { + status =3D "okay"; +}; + +&watchdog4 { + status =3D "okay"; +}; + +&qspi { + status =3D "okay"; + flash@0 { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "micron,mt25qu02g", "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <100000000>; + + m25p,fast-read; + cdns,page-size =3D <256>; + cdns,block-size =3D <16>; + cdns,read-delay =3D <2>; + cdns,tshsl-ns =3D <50>; + cdns,tsd2d-ns =3D <50>; + cdns,tchsh-ns =3D <4>; + cdns,tslch-ns =3D <4>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + qspi_boot: partition@0 { + label =3D "Boot and fpga data"; + reg =3D <0x0 0x03FE0000>; + }; + + qspi_rootfs: partition@3FE0000 { + label =3D "Root Filesystem - JFFS2"; + reg =3D <0x03FE0000 0x0C020000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts b/arc= h/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts new file mode 100644 index 000000000000..0403f3859b4e --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023, Intel Corporation + */ +#include "socfpga_agilex5.dtsi" + +/ { + model =3D "SoCFPGA Agilex5 SoCDK"; + compatible =3D "intel,socfpga-agilex5-socdk", "intel,socfpga-agilex"; + + aliases { + serial0 =3D &uart0; + ethernet0 =3D &gmac0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + leds { + compatible =3D "gpio-leds"; + hps0 { + label =3D "hps_led0"; + gpios =3D <&portb 20 GPIO_ACTIVE_HIGH>; + }; + + hps1 { + label =3D "hps_led1"; + gpios =3D <&portb 19 GPIO_ACTIVE_HIGH>; + }; + + hps2 { + label =3D "hps_led2"; + gpios =3D <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + + memory { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x0 0x80000000>; + #address-cells =3D <0x2>; + #size-cells =3D <0x2>; + u-boot,dm-pre-reloc; + }; +}; + +&gpio1 { + status =3D "okay"; +}; + +&gmac0 { + status =3D "okay"; + phy-mode =3D "rgmii"; + phy-handle =3D <&phy0>; + + max-frame-size =3D <9000>; + + mdio0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg =3D <0>; + }; + }; +}; + +&osc1 { + clock-frequency =3D <25000000>; +}; + +&uart0 { + status =3D "okay"; +}; + +&watchdog0 { + status =3D "okay"; +}; + +&watchdog1 { + status =3D "okay"; +}; + +&watchdog2 { + status =3D "okay"; +}; + +&watchdog3 { + status =3D "okay"; +}; + +&watchdog4 { + status =3D "okay"; +}; + +&nand { + status =3D "okay"; + + flash@0 { + #address-cells =3D <1>; + #size-cells =3D <1>; + reg =3D <0>; + nand-bus-width =3D <16>; + + partition@0 { + label =3D "u-boot"; + reg =3D <0 0x200000>; + }; + partition@200000 { + label =3D "env"; + reg =3D <0x200000 0x40000>; + }; + partition@240000 { + label =3D "dtb"; + reg =3D <0x240000 0x40000>; + }; + partition@280000 { + label =3D "kernel"; + reg =3D <0x280000 0x2000000>; + }; + partition@2280000 { + label =3D "misc"; + reg =3D <0x2280000 0x2000000>; + }; + partition@4280000 { + label =3D "rootfs"; + reg =3D <0x4280000 0x3d80000>; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_swvp.dts b/arc= h/arm64/boot/dts/intel/socfpga_agilex5_socdk_swvp.dts new file mode 100644 index 000000000000..26a9347a23cc --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_swvp.dts @@ -0,0 +1,248 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023, Intel Corporation + */ +#include "socfpga_agilex5.dtsi" + +/ { + model =3D "SoCFPGA Agilex5 SoCDK"; + compatible =3D "intel,socfpga-agilex5-socdk", "intel,socfpga-agilex"; + + aliases { + serial0 =3D &uart0; + ethernet0 =3D &gmac0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + bootargs =3D "console=3Duart8250,mmio32,0x10c02000,115200n8 \ + root=3D/dev/ram0 rw initrd=3D0x10000000 init=3D/sbin/init \ + ramdisk_size=3D10000000 earlycon=3Duart8250,mmio32,0x10c02000,115200n8 \ + panic=3D-1 nosmp rootfstype=3Dext3"; + }; + + leds { + compatible =3D "gpio-leds"; + hps0 { + label =3D "hps_led0"; + gpios =3D <&portb 20 GPIO_ACTIVE_HIGH>; + }; + + hps1 { + label =3D "hps_led1"; + gpios =3D <&portb 19 GPIO_ACTIVE_HIGH>; + }; + + hps2 { + label =3D "hps_led2"; + gpios =3D <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + + memory { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x0 0x80000000>; + #address-cells =3D <0x2>; + #size-cells =3D <0x2>; + u-boot,dm-pre-reloc; + }; +}; + +&gpio1 { + status =3D "okay"; +}; + +&gmac0 { + status =3D "okay"; + phy-mode =3D "rgmii"; + phy-handle =3D <&phy0>; + + max-frame-size =3D <9000>; + + mdio0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg =3D <0>; + }; + }; +}; + +&mmc { + status =3D "okay"; + bus-width =3D <4>; + sd-uhs-sdr50; + sdhci-caps =3D <0x00000000 0x0000c800>; + sdhci-caps-mask =3D <0x00002000 0x0000ff00>; + no-sdio; + cdns,phy-use-ext-lpbk-dqs =3D <1>; + cdns,phy-use-lpbk-dqs =3D <1>; + cdns,phy-use-phony-dqs =3D <1>; + cdns,phy-use-phony-dqs-cmd =3D <1>; + cdns,phy-io-mask-always-on =3D <0>; + cdns,phy-io-mask-end =3D <5>; + cdns,phy-io-mask-start =3D <0>; + cdns,phy-data-select-oe-end =3D <1>; + cdns,phy-sync-method =3D <1>; + cdns,phy-sw-half-cycle-shift =3D <0>; + cdns,phy-rd-del-sel =3D <52>; + cdns,phy-underrun-suppress =3D <1>; + cdns,phy-gate-cfg-always-on =3D <1>; + cdns,phy-param-dll-bypass-mode =3D <1>; + cdns,phy-param-phase-detect-sel =3D <2>; + cdns,phy-param-dll-start-point =3D <254>; + cdns,phy-read-dqs-cmd-delay =3D <0>; + cdns,phy-clk-wrdqs-delay =3D <0>; + cdns,phy-clk-wr-delay =3D <0>; + cdns,phy-read-dqs-delay =3D <0>; + cdns,phy-phony-dqs-timing =3D <0>; + cdns,hrs09-rddata-en =3D <1>; + cdns,hrs09-rdcmd-en =3D <1>; + cdns,hrs09-extended-wr-mode =3D <1>; + cdns,hrs09-extended-rd-mode =3D <1>; + cdns,hrs10-hcsdclkadj =3D <3>; + cdns,hrs16-wrdata1-sdclk-dly =3D <0>; + cdns,hrs16-wrdata0-sdclk-dly =3D <0>; + cdns,hrs16-wrcmd1-sdclk-dly =3D <0>; + cdns,hrs16-wrcmd0-sdclk-dly =3D <0>; + cdns,hrs16-wrdata1-dly =3D <0>; + cdns,hrs16-wrdata0-dly =3D <0>; + cdns,hrs16-wrcmd1-dly =3D <0>; + cdns,hrs16-wrcmd0-dly =3D <0>; + cdns,hrs07-rw-compensate =3D <10>; + cdns,hrs07-idelay-val =3D <0>; +}; + +&i2c0 { + status =3D "okay"; +}; + +&i2c1 { + status =3D "okay"; +}; + +&i2c2 { + status =3D "okay"; +}; + +&i2c3 { + status =3D "okay"; +}; + +&i2c4 { + status =3D "okay"; +}; + +&i3c0 { + status =3D "okay"; +}; + +&i3c1 { + status =3D "okay"; +}; + +&osc1 { + clock-frequency =3D <25000000>; +}; + +&uart0 { + status =3D "okay"; +}; + +&usb0 { + status =3D "okay"; + disable-over-current; +}; + +&watchdog0 { + status =3D "okay"; +}; + +&watchdog1 { + status =3D "okay"; +}; + +&watchdog2 { + status =3D "okay"; +}; + +&watchdog3 { + status =3D "okay"; +}; + +&watchdog4 { + status =3D "okay"; +}; + +&qspi { + status =3D "okay"; + flash@0 { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "micron,mt25qu02g", "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <100000000>; + + m25p,fast-read; + cdns,page-size =3D <256>; + cdns,block-size =3D <16>; + cdns,read-delay =3D <2>; + cdns,tshsl-ns =3D <50>; + cdns,tsd2d-ns =3D <50>; + cdns,tchsh-ns =3D <4>; + cdns,tslch-ns =3D <4>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + qspi_boot: partition@0 { + label =3D "Boot and fpga data"; + reg =3D <0x0 0x03FE0000>; + }; + + qspi_rootfs: partition@3FE0000 { + label =3D "Root Filesystem - JFFS2"; + reg =3D <0x03FE0000 0x0C020000>; + }; + }; + }; +}; + +&nand { + status =3D "okay"; + + flash@0 { + #address-cells =3D <1>; + #size-cells =3D <1>; + reg =3D <0>; + nand-bus-width =3D <16>; + + partition@0 { + label =3D "u-boot"; + reg =3D <0 0x200000>; + }; + partition@200000 { + label =3D "env"; + reg =3D <0x200000 0x40000>; + }; + partition@240000 { + label =3D "dtb"; + reg =3D <0x240000 0x40000>; + }; + partition@280000 { + label =3D "kernel"; + reg =3D <0x280000 0x2000000>; + }; + partition@2280000 { + label =3D "misc"; + reg =3D <0x2280000 0x2000000>; + }; + partition@4280000 { + label =3D "rootfs"; + reg =3D <0x4280000 0x3d80000>; + }; + }; +}; --=20 2.25.1