From nobody Wed Dec 17 03:58:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70A6FEB64DC for ; Sat, 17 Jun 2023 16:27:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237563AbjFQQ1B (ORCPT ); Sat, 17 Jun 2023 12:27:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44168 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232184AbjFQQ05 (ORCPT ); Sat, 17 Jun 2023 12:26:57 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4998A139; Sat, 17 Jun 2023 09:26:57 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id DAC6260F51; Sat, 17 Jun 2023 16:26:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0F697C433CC; Sat, 17 Jun 2023 16:26:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1687019216; bh=SPJDcPMwrrlzSG74QPkv587ksGll4C/xWYjG7hI2xKQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=k2ykfh7EjPhM7ZUVmbO9bWK2evu+5Qawj1w4FOwYFihn5wmG7ZAaG4kg6i/BzWV4w 2Red1wsns7E8rxWYmH4Hwn8Fe6oG/C8nvnOhvHXUGD0XTuWmy5DQsaRg/WbCuuLyzm MGbOMUGeCzLkBL92xDgnXA1KQSOYyHCfbLtyIziOltVpXuQn+/cy9BUbBvbdvg/4gf zKicAu5dwCvNidcJmav3gnPnkZi9erhX40GyUB16+kiIUyMVWqOxAZu+XlV8+x++e9 QO6NgyNhwqhfpWfIFii4u7MorlqmVyH4iBJA4xxUDLyDUHlXuQCXcie8nir72i0EW8 hRopKsY56omzg== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano Cc: Guo Ren , Fu Wei , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley Subject: [PATCH v3 1/8] dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC Date: Sun, 18 Jun 2023 00:15:22 +0800 Message-Id: <20230617161529.2092-2-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230617161529.2092-1-jszhang@kernel.org> References: <20230617161529.2092-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add compatible string for T-HEAD TH1520 plic. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley Reviewed-by: Guo Ren --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,= plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/si= five,plic-1.0.0.yaml index f75736a061af..0fa9b862e4a5 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml @@ -65,6 +65,7 @@ properties: - items: - enum: - allwinner,sun20i-d1-plic + - thead,th1520-plic - const: thead,c900-plic - items: - const: sifive,plic-1.0.0 --=20 2.40.0 From nobody Wed Dec 17 03:58:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E4ACC001DD for ; Sat, 17 Jun 2023 16:27:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346166AbjFQQ1F (ORCPT ); Sat, 17 Jun 2023 12:27:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44210 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238423AbjFQQ1D (ORCPT ); Sat, 17 Jun 2023 12:27:03 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77E1F1724; Sat, 17 Jun 2023 09:27:01 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 1379F60F76; Sat, 17 Jun 2023 16:27:01 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 285D1C433C8; Sat, 17 Jun 2023 16:26:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1687019220; bh=nfDyGgMqm33myHuNfUx4jziWq1pWWDUYYnNP4dchYlI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=K0tit8FlvBgNCxLsvZuqNmqrvwKesXFZMHSlgwmFsmGn0CIkrJhOtZ7kDEaM7ktS8 X+JXUbiHFeQsp8XDtM4JEg4RHYUzVx7JuEUHYamsOgkhB87wGrXZHszOv896jkef5y 1vxbmr/fXwWffEflkV4glb6HRsNFNq0FpKISjD10N2BvFH6jUi6o/FNOYAZuLLGSir Rda56EcnXg+nX45s4OKpHtOf5tHhUMkcSdsv6oezjPfdyb/oMYrcv/zaqOilmwcox2 qFgqWjSlIRBydT5+BoVww9Sil5V+ZTOzpK4bEGTKnypTgIf7mDR7SyN6KboJeCEjG3 +TBXVAT8oDgow== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano Cc: Guo Ren , Fu Wei , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley Subject: [PATCH v3 2/8] dt-bindings: timer: Add T-HEAD TH1520 clint Date: Sun, 18 Jun 2023 00:15:23 +0800 Message-Id: <20230617161529.2092-3-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230617161529.2092-1-jszhang@kernel.org> References: <20230617161529.2092-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add compatible string for the T-HEAD TH1520 clint. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Do= cumentation/devicetree/bindings/timer/sifive,clint.yaml index 94bef9424df1..388d3385d7eb 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -37,6 +37,7 @@ properties: - items: - enum: - allwinner,sun20i-d1-clint + - thead,th1520-clint - const: thead,c900-clint - items: - const: sifive,clint0 --=20 2.40.0 From nobody Wed Dec 17 03:58:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1248EB64DB for ; Sat, 17 Jun 2023 16:27:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346228AbjFQQ1K (ORCPT ); Sat, 17 Jun 2023 12:27:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346231AbjFQQ1G (ORCPT ); Sat, 17 Jun 2023 12:27:06 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4198A10D8; Sat, 17 Jun 2023 09:27:05 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C815F60F78; Sat, 17 Jun 2023 16:27:04 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EB7D5C433C9; Sat, 17 Jun 2023 16:27:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1687019224; bh=ayCUu7VWTParlzqlhysZ/3yMoFf8bKiG9G6ke1+jMJ4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FGjV6yD0kJyidE+gMTGYZ+mL4zZN4FDEsOMBIjd+0+g/uh9zpjuCuMDgRObtvZ/zA /zW39lihE/LJ9ntaZXe4+AHtf9lT3ipqWNhRneZggwHAEbAzb/NVNh+G6nQxqh/nK5 daH2GtaeWlMFqEk39/a02/koOZXP9fsHME+23sNtiaqsahrroPkHTg5mEQHFAEeP/9 UvknHTBiGituPIzz9KA6rMSbI2ZmQi/wQb97k46URxMwOFyQubT7hkpzrstFtwsv8y bf8hA1Ff6ZdVMlEk/Jpd3amham+2N/S5f84etKZdVYsgc588eQ/rCIIqtcq4iWszje oqphKQy1i3tQg== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano Cc: Guo Ren , Fu Wei , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 3/8] dt-bindings: riscv: Add T-HEAD TH1520 board compatibles Date: Sun, 18 Jun 2023 00:15:24 +0800 Message-Id: <20230617161529.2092-4-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230617161529.2092-1-jszhang@kernel.org> References: <20230617161529.2092-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Several SoMs and boards are available that feature the T-HEAD TH1520 SoC. Document the compatible strings. Signed-off-by: Jisheng Zhang --- .../devicetree/bindings/riscv/thead.yaml | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/thead.yaml diff --git a/Documentation/devicetree/bindings/riscv/thead.yaml b/Documenta= tion/devicetree/bindings/riscv/thead.yaml new file mode 100644 index 000000000000..e62f6821372e --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/thead.yaml @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/thead.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD SoC-based boards + +maintainers: + - Jisheng Zhang + +description: + T-HEAD SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Sipeed Lichee Pi 4A board for the Sipeed Lichee Modul= e 4A + items: + - enum: + - sipeed,lichee-pi-4a + - const: sipeed,lichee-module-4a + - const: thead,th1520 + +additionalProperties: true + +... --=20 2.40.0 From nobody Wed Dec 17 03:58:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07AD3EB64DC for ; Sat, 17 Jun 2023 16:27:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346281AbjFQQ1R (ORCPT ); Sat, 17 Jun 2023 12:27:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44410 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345967AbjFQQ1L (ORCPT ); Sat, 17 Jun 2023 12:27:11 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6222D173B; Sat, 17 Jun 2023 09:27:09 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E9A5D60F71; Sat, 17 Jun 2023 16:27:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B1AE5C433CD; Sat, 17 Jun 2023 16:27:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1687019228; bh=9TcP0pheewMFNteE2MjQt4eyImwOKciOqR8+Aqc04aI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BPnAUsh93U3aeHBUKqzv4wIHLB3IOdV2/E6/coVGuZyPoQ34uckzFBlxTg2W2TApd ElOmw92e7gpvrpqZCj0LR+ePdZPnWiSteQwpULo5lNfTQOo09E1ViF2YbdCqlblh/w rzqy68lX5qbuPf2pI6lR8Y7gEFVwSOAqtFHoZ3wGgQ6jaHe+WzG98kZ4LEQE6z0fKW pnWBbX5XYpiKkX1QOk5psdB1DfcRGUF/Upf+63t+59b5/xuyi7BoIfzBeMFFpNvY2/ weom9JS1O9tQqeAkZv0pDRso9V9TXdymiQr0zAHnAzWjSoMzWxbbgCoVnYl+E2ywLP EphWZrBIzsKew== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano Cc: Guo Ren , Fu Wei , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley Subject: [PATCH v3 4/8] riscv: Add the T-HEAD SoC family Kconfig option Date: Sun, 18 Jun 2023 00:15:25 +0800 Message-Id: <20230617161529.2092-5-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230617161529.2092-1-jszhang@kernel.org> References: <20230617161529.2092-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The first SoC in the T-HEAD series is TH1520, containing quad T-HEAD C910 cores. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley --- arch/riscv/Kconfig.socs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 1cf69f958f10..ce10a38dff37 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -41,6 +41,12 @@ config ARCH_SUNXI This enables support for Allwinner sun20i platform hardware, including boards based on the D1 and D1s SoCs. =20 +config ARCH_THEAD + bool "T-HEAD RISC-V SoCs" + select ERRATA_THEAD + help + This enables support for the RISC-V based T-HEAD SoCs. + config ARCH_VIRT def_bool SOC_VIRT =20 --=20 2.40.0 From nobody Wed Dec 17 03:58:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC5A5EB64D9 for ; Sat, 17 Jun 2023 16:27:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229945AbjFQQ1X (ORCPT ); Sat, 17 Jun 2023 12:27:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44632 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346295AbjFQQ1T (ORCPT ); Sat, 17 Jun 2023 12:27:19 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 261E51FEC; Sat, 17 Jun 2023 09:27:13 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 76AF260BA8; Sat, 17 Jun 2023 16:27:12 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D1D5CC43142; Sat, 17 Jun 2023 16:27:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1687019231; bh=/rpzt+cUra4ehzWl29wluUAHECrIIYSnbeZnS5OIyCM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FJpZFN2jPlnVGf7NIimQwVFz179vyVzGudt8mvNWuUkWEpFNXQF0UVyNBwBp0Kv6B LUDpc+MF6M6AGfoWUivIcrctyPGr/LPM3mncyXYpQDpI/OroymaiJ2gOtutTB1uBP2 SNZZbBrsAZC8cz2m3WgjDBOlse0UnRM7iVlTVf9iH2bnz6jq691tPGqBknVBnGb0XS RL8vsIaZYoIufhpTBpfGG2vRgx5f1HuQdJgfPgOy2J+3XWVrBSP0VKwT9n9VIny/v9 EW90yIawXcL4NWPdqMg+ZK1UrNv9KJzhFxlk/dnembxvDVUzJRhEoih4Thkk7f0tZk nNJAlzIi/RnaQ== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano Cc: Guo Ren , Fu Wei , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 5/8] riscv: dts: add initial T-HEAD TH1520 SoC device tree Date: Sun, 18 Jun 2023 00:15:26 +0800 Message-Id: <20230617161529.2092-6-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230617161529.2092-1-jszhang@kernel.org> References: <20230617161529.2092-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add initial device tree for the TH1520 RISC-V SoC by T-HEAD. Signed-off-by: Jisheng Zhang --- arch/riscv/boot/dts/thead/th1520.dtsi | 422 ++++++++++++++++++++++++++ 1 file changed, 422 insertions(+) create mode 100644 arch/riscv/boot/dts/thead/th1520.dtsi diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi new file mode 100644 index 000000000000..56a73134b49e --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -0,0 +1,422 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + * Copyright (C) 2023 Jisheng Zhang + */ + +#include + +/ { + compatible =3D "thead,th1520"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus: cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <3000000>; + + c910_0: cpu@0 { + compatible =3D "thead,c910", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + reg =3D <0>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache>; + mmu-type =3D "riscv,sv39"; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + c910_1: cpu@1 { + compatible =3D "thead,c910", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + reg =3D <1>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache>; + mmu-type =3D "riscv,sv39"; + + cpu1_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + c910_2: cpu@2 { + compatible =3D "thead,c910", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + reg =3D <2>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache>; + mmu-type =3D "riscv,sv39"; + + cpu2_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + c910_3: cpu@3 { + compatible =3D "thead,c910", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + reg =3D <3>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache>; + mmu-type =3D "riscv,sv39"; + + cpu3_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + l2_cache: l2-cache { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + }; + + osc: oscillator { + compatible =3D "fixed-clock"; + clock-output-names =3D "osc_24m"; + #clock-cells =3D <0>; + }; + + osc_32k: 32k-oscillator { + compatible =3D "fixed-clock"; + clock-output-names =3D "osc_32k"; + #clock-cells =3D <0>; + }; + + apb_clk: apb-clk-clock { + compatible =3D "fixed-clock"; + clock-output-names =3D "apb_clk"; + #clock-cells =3D <0>; + }; + + uart_sclk: uart-sclk-clock { + compatible =3D "fixed-clock"; + clock-output-names =3D "uart_sclk"; + #clock-cells =3D <0>; + }; + + soc { + compatible =3D "simple-bus"; + interrupt-parent =3D <&plic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + plic: interrupt-controller@ffd8000000 { + compatible =3D "thead,th1520-plic", "thead,c900-plic"; + reg =3D <0xff 0xd8000000 0x0 0x01000000>; + interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>; + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <2>; + riscv,ndev =3D <240>; + }; + + clint: timer@ffdc000000 { + compatible =3D "thead,th1520-clint", "thead,c900-clint"; + reg =3D <0xff 0xdc000000 0x0 0x00010000>; + interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>; + }; + + uart0: serial@ffe7014000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0xff 0xe7014000 0x0 0x100>; + interrupts =3D <36 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&uart_sclk>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart1: serial@ffe7f00000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0xff 0xe7f00000 0x0 0x100>; + interrupts =3D <37 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&uart_sclk>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart3: serial@ffe7f04000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0xff 0xe7f04000 0x0 0x100>; + interrupts =3D <39 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&uart_sclk>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + gpio2: gpio@ffe7f34000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0xff 0xe7f34000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + portc: gpio-controller@0 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + ngpios =3D <32>; + reg =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D <58 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio3: gpio@ffe7f38000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0xff 0xe7f38000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + portd: gpio-controller@0 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + ngpios =3D <32>; + reg =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D <59 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio0: gpio@ffec005000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0xff 0xec005000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + porta: gpio-controller@0 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + ngpios =3D <32>; + reg =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D <56 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio1: gpio@ffec006000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0xff 0xec006000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + portb: gpio-controller@0 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + ngpios =3D <32>; + reg =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D <57 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + uart2: serial@ffec010000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0xff 0xec010000 0x0 0x4000>; + interrupts =3D <38 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&uart_sclk>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + dmac0: dma-controller@ffefc00000 { + compatible =3D "snps,axi-dma-1.01a"; + reg =3D <0xff 0xefc00000 0x0 0x1000>; + interrupts =3D <27 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&apb_clk>, <&apb_clk>; + clock-names =3D "core-clk", "cfgr-clk"; + #dma-cells =3D <1>; + dma-channels =3D <4>; + snps,block-size =3D <65536 65536 65536 65536>; + snps,priority =3D <0 1 2 3>; + snps,dma-masters =3D <1>; + snps,data-width =3D <4>; + snps,axi-max-burst-len =3D <16>; + status =3D "disabled"; + }; + + timer0: timer@ffefc32000 { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0xff 0xefc32000 0x0 0x14>; + clocks =3D <&apb_clk>; + clock-names =3D "timer"; + interrupts =3D <16 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + timer1: timer@ffefc32014 { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0xff 0xefc32014 0x0 0x14>; + clocks =3D <&apb_clk>; + clock-names =3D "timer"; + interrupts =3D <17 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + timer2: timer@ffefc32028 { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0xff 0xefc32028 0x0 0x14>; + clocks =3D <&apb_clk>; + clock-names =3D "timer"; + interrupts =3D <18 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + timer3: timer@ffefc3203c { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0xff 0xefc3203c 0x0 0x14>; + clocks =3D <&apb_clk>; + clock-names =3D "timer"; + interrupts =3D <19 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + uart4: serial@fff7f08000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0xff 0xf7f08000 0x0 0x4000>; + interrupts =3D <40 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&uart_sclk>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart5: serial@fff7f0c000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0xff 0xf7f0c000 0x0 0x4000>; + interrupts =3D <41 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&uart_sclk>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + timer4: timer@ffffc33000 { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0xff 0xffc33000 0x0 0x14>; + clocks =3D <&apb_clk>; + clock-names =3D "timer"; + interrupts =3D <20 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + timer5: timer@ffffc33014 { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0xff 0xffc33014 0x0 0x14>; + clocks =3D <&apb_clk>; + clock-names =3D "timer"; + interrupts =3D <21 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + timer6: timer@ffffc33028 { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0xff 0xffc33028 0x0 0x14>; + clocks =3D <&apb_clk>; + clock-names =3D "timer"; + interrupts =3D <22 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + timer7: timer@ffffc3303c { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0xff 0xffc3303c 0x0 0x14>; + clocks =3D <&apb_clk>; + clock-names =3D "timer"; + interrupts =3D <23 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + ao_gpio0: gpio@fffff41000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0xff 0xfff41000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + porte: gpio-controller@0 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + ngpios =3D <32>; + reg =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D <76 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + ao_gpio1: gpio@fffff52000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0xff 0xfff52000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + portf: gpio-controller@0 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + ngpios =3D <32>; + reg =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D <55 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; +}; --=20 2.40.0 From nobody Wed Dec 17 03:58:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13D85EB64DA for ; Sat, 17 Jun 2023 16:27:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346329AbjFQQ1g (ORCPT ); Sat, 17 Jun 2023 12:27:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44848 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346322AbjFQQ11 (ORCPT ); Sat, 17 Jun 2023 12:27:27 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E84C2700; Sat, 17 Jun 2023 09:27:17 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C70D160F71; Sat, 17 Jun 2023 16:27:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5DAF8C433C0; Sat, 17 Jun 2023 16:27:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1687019236; bh=SPhHXPcnyMrXjaiP7DOxwbB5VjmdUJq9U0kUEmDjQ0w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=psdbYLjaspvqgMtuNSkr/BszIFTR4pISYrWxkLOPmv8bPWSIkxY0AgQSBtF3YXC2Y +jGPnMEvDbvFIa/9sxjQT/UAYeFa+wwReHYVw57aqO+sjWmRwpM2ZDVjN97UZopvzS FIi+hi9aTmhcJp+AN75Xq9S1K2vYHuErHTI48uzdX8Ve6NAKmJLF+c2MBShRNbHHib zEy5tjmAC5C1IW29yYSdYBZnGWKzkPPBssM3UJOz3TVk6+/Z9+B4Mjv/u1AGI5NutE /643+We1nvOFlB0LnbYkOhVLfxUALGc+3HOqD3jTjwzjkHt+e6Q+TcOVjMkkRD5LzJ hkTog+p8XmsLQ== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano Cc: Guo Ren , Fu Wei , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 6/8] riscv: dts: thead: add sipeed Lichee Pi 4A board device tree Date: Sun, 18 Jun 2023 00:15:27 +0800 Message-Id: <20230617161529.2092-7-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230617161529.2092-1-jszhang@kernel.org> References: <20230617161529.2092-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core module which is powered by T-HEAD's TH1520 SoC. Add minimal device tree files for the core module and the development board. Support basic uart/gpio/dmac drivers, so supports booting to a basic shell. Signed-off-by: Jisheng Zhang --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/thead/Makefile | 2 + .../dts/thead/th1520-lichee-module-4a.dtsi | 38 +++++++++++++++++++ .../boot/dts/thead/th1520-lichee-pi-4a.dts | 32 ++++++++++++++++ 4 files changed, 73 insertions(+) create mode 100644 arch/riscv/boot/dts/thead/Makefile create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index f0d9f89054f8..1e884868ccba 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -2,6 +2,7 @@ subdir-y +=3D allwinner subdir-y +=3D sifive subdir-y +=3D starfive +subdir-y +=3D thead subdir-y +=3D canaan subdir-y +=3D microchip subdir-y +=3D renesas diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead= /Makefile new file mode 100644 index 000000000000..e311fc9a5939 --- /dev/null +++ b/arch/riscv/boot/dts/thead/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_THEAD) +=3D th1520-lichee-pi-4a.dtb diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/= riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi new file mode 100644 index 000000000000..4b0249ac710f --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Jisheng Zhang + */ + +/dts-v1/; + +#include "th1520.dtsi" + +/ { + model =3D "Sipeed Lichee Module 4A"; + compatible =3D "sipeed,lichee-module-4a", "thead,th1520"; + + memory@0 { + device_type =3D "memory"; + reg =3D <0x0 0x00000000 0x2 0x00000000>; + }; +}; + +&osc { + clock-frequency =3D <24000000>; +}; + +&osc_32k { + clock-frequency =3D <32768>; +}; + +&apb_clk { + clock-frequency =3D <62500000>; +}; + +&uart_sclk { + clock-frequency =3D <100000000>; +}; + +&dmac0 { + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv= /boot/dts/thead/th1520-lichee-pi-4a.dts new file mode 100644 index 000000000000..a1248b2ee3a3 --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Jisheng Zhang + */ + +#include "th1520-lichee-module-4a.dtsi" + +/ { + model =3D "Sipeed Lichee Pi 4A"; + compatible =3D "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,t= h1520"; + + aliases { + gpio0 =3D &gpio0; + gpio1 =3D &gpio1; + gpio2 =3D &gpio2; + gpio3 =3D &gpio3; + serial0 =3D &uart0; + serial1 =3D &uart1; + serial2 =3D &uart2; + serial3 =3D &uart3; + serial4 =3D &uart4; + serial5 =3D &uart5; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&uart0 { + status =3D "okay"; +}; --=20 2.40.0 From nobody Wed Dec 17 03:58:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB0FCEB64DB for ; Sat, 17 Jun 2023 16:27:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231200AbjFQQ1r (ORCPT ); Sat, 17 Jun 2023 12:27:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45074 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346322AbjFQQ1k (ORCPT ); Sat, 17 Jun 2023 12:27:40 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E366211D; Sat, 17 Jun 2023 09:27:22 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E7C9A61172; Sat, 17 Jun 2023 16:27:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id ADFA5C433C8; Sat, 17 Jun 2023 16:27:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1687019240; bh=tuyRjugUtNnv9NSvg0JKtT6JTySfG2QjgD5pYhGE3Oo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rLemWZcmp8D3z8QRkuuDf2liEEtC/neuEkSmoLSHnQgiOwulQ7eCL/KBpJl/rE7vD JsSZ7N3EO5eX40xP6q9hxFDd+WPWvBpQNSbyo1UlzK7m6yoyfDzOEug7yDnSj9Fvzt nKCg/BZZqu33EPlM0+umikiChGZTZREweHOfuARN/WVQ0TLKBBsX6Ceagyp7pAoTPd mOC5vFCkJXkH33fDdscyRniDJTOsqMdatDrVeOLEry1ZzoDRoLeO3oQ0yu9YySZAZF EKqUT7hzvN73HeXK1nCs/c8NEeZnncnkWCHCu/f8TxBQdKxKHIWISGi0u3n95wWZFw 3jJlEXSWOSoyQ== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano Cc: Guo Ren , Fu Wei , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley Subject: [PATCH v3 7/8] MAINTAINERS: add entry for T-HEAD RISC-V SoC Date: Sun, 18 Jun 2023 00:15:28 +0800 Message-Id: <20230617161529.2092-8-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230617161529.2092-1-jszhang@kernel.org> References: <20230617161529.2092-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, I would like to maintain the T-HEAD RISC-V SoC support. Signed-off-by: Jisheng Zhang Acked-by: Conor Dooley --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e0ad886d3163..68805b09654f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18162,6 +18162,14 @@ F: drivers/perf/riscv_pmu.c F: drivers/perf/riscv_pmu_legacy.c F: drivers/perf/riscv_pmu_sbi.c =20 +RISC-V THEAD SoC SUPPORT +M: Jisheng Zhang +M: Guo Ren +M: Fu Wei +L: linux-riscv@lists.infradead.org +S: Maintained +F: arch/riscv/boot/dts/thead/ + RNBD BLOCK DRIVERS M: Md. Haris Iqbal M: Jack Wang --=20 2.40.0 From nobody Wed Dec 17 03:58:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A8E8EB64DB for ; Sat, 17 Jun 2023 16:28:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233001AbjFQQ2C (ORCPT ); Sat, 17 Jun 2023 12:28:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232486AbjFQQ16 (ORCPT ); Sat, 17 Jun 2023 12:27:58 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9F9026AA; Sat, 17 Jun 2023 09:27:34 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 41F2960F76; Sat, 17 Jun 2023 16:27:25 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 334E4C433C0; Sat, 17 Jun 2023 16:27:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1687019244; bh=15h31Gq485ARLyon5H9bm78eqGG5GpNtnkp3TJY8+4s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bUcCSHlXWz8OFVrESwROBhwI5K2nR0kk3xQ1Y0ggV+4bN2ztD8fjNnx+lOC9QoLja 2EcFpI6AFbr8WK290wnO6rYD+tNSbFhScpf39CJQGF1J9X5ZScD/wVutAcsFtIq1bg GDIxqZ4cKpbgNQVFI0mkTXZUZKWi1gIO9Ih2YTI4IY+052KxIN5gr+6FJdz06DUkt7 o3oVmfhkIXPpBYp9jlc6PWHIGqZkx4Pu7dlrRg0lQxKEK094ViP98LUeeM888vAlnQ r0x3Gw/XwFtfMQs2YwjH6voAy9g/mTY999c+5mUScETLEt5jVm9c+uYQGr4uosMr9a WJSPTCjEMg4IQ== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano Cc: Guo Ren , Fu Wei , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley , Palmer Dabbelt Subject: [PATCH v3 8/8] riscv: defconfig: enable T-HEAD SoC Date: Sun, 18 Jun 2023 00:15:29 +0800 Message-Id: <20230617161529.2092-9-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230617161529.2092-1-jszhang@kernel.org> References: <20230617161529.2092-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable T-HEAD SoC config in defconfig to allow the default upstream kernel to boot on Sipeed Lichee Pi 4A board. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley Acked-by: Palmer Dabbelt Acked-by: Guo Ren --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index d98d6e90b2b8..109e4b5b003c 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -27,6 +27,7 @@ CONFIG_EXPERT=3Dy CONFIG_PROFILING=3Dy CONFIG_SOC_MICROCHIP_POLARFIRE=3Dy CONFIG_ARCH_RENESAS=3Dy +CONFIG_ARCH_THEAD=3Dy CONFIG_SOC_SIFIVE=3Dy CONFIG_SOC_STARFIVE=3Dy CONFIG_ARCH_SUNXI=3Dy --=20 2.40.0