From nobody Mon Feb 9 09:46:39 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C6C2EB64DD for ; Fri, 16 Jun 2023 10:58:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234884AbjFPK56 (ORCPT ); Fri, 16 Jun 2023 06:57:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345385AbjFPK5g (ORCPT ); Fri, 16 Jun 2023 06:57:36 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E4B135583; Fri, 16 Jun 2023 03:50:25 -0700 (PDT) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35G9l7bi011896; Fri, 16 Jun 2023 10:50:22 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=25RZna5ZNyxfew4SK+nqRn7dDf3Lqj2R+RQunJiq25k=; b=CiR3eWRppd1uAvrYFjHUdI+s2tsjJLM5eai0NlWgXLVa58OEYUBP1tpU8a8pwpU4/+c9 yHJiXCR1si1ND2vD6CVWgXJ+C3B+WCAduL0aRBi4BWYtko574u6WLnSm41nh2KnMHEbb aLmElNhqn03GGP1chkWua2yl2to6ILF4rxVQ3z3lXhBKyKycOuA6vcrw8QX5SB+zDfmH h9xLthHX8jh5F1kNMbEHhHbrtGgZlTWEBF8xQI6slxcrgJ8oxao7xWalRhZq9K0m9qRF iFaXGVGYhh7xS1nD3cy6V0QHOT3qpjciTz8JlXkbHHuBH2l2F3g/GVIUib1yvrg3Dv7L nw== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3r8n09g5qw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Jun 2023 10:50:22 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 35GAoLPI029367 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Jun 2023 10:50:21 GMT Received: from hu-imrashai-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 16 Jun 2023 03:50:16 -0700 From: Imran Shaik To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Melody Olvera , Taniya Das , Imran Shaik , , , , , Jagadeesh Kona , Satya Priya Kakitapalli , Ajit Pandey Subject: [PATCH 1/2] dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCs Date: Fri, 16 Jun 2023 16:19:40 +0530 Message-ID: <20230616104941.921555-2-quic_imrashai@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230616104941.921555-1-quic_imrashai@quicinc.com> References: <20230616104941.921555-1-quic_imrashai@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: sq9-U4597ZEAgl5wV9WvKQ91lPewt3Ti X-Proofpoint-ORIG-GUID: sq9-U4597ZEAgl5wV9WvKQ91lPewt3Ti X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-16_07,2023-06-16_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 mlxlogscore=999 spamscore=0 priorityscore=1501 malwarescore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306160097 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update the qcom GCC clock bindings and add v2 compatible string for QDU1000 and QRU1000 SoCs. Signed-off-by: Taniya Das Signed-off-by: Imran Shaik --- .../devicetree/bindings/clock/qcom,qdu1000-gcc.yaml | 6 +++++- include/dt-bindings/clock/qcom,qdu1000-gcc.h | 4 +++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml = b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml index 767a9d03aa32..030953d258c1 100644 --- a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml @@ -8,6 +8,8 @@ title: Qualcomm Global Clock & Reset Controller for QDU1000= and QRU1000 =20 maintainers: - Melody Olvera + - Taniya Das + - Imran Shaik =20 description: | Qualcomm global clock control module which supports the clocks, resets a= nd @@ -17,7 +19,9 @@ description: | =20 properties: compatible: - const: qcom,qdu1000-gcc + enum: + - qcom,qdu1000-gcc + - qcom,qdu1000-gcc-v2 =20 clocks: items: diff --git a/include/dt-bindings/clock/qcom,qdu1000-gcc.h b/include/dt-bind= ings/clock/qcom,qdu1000-gcc.h index ddbc6b825e80..2fd36cbfddbb 100644 --- a/include/dt-bindings/clock/qcom,qdu1000-gcc.h +++ b/include/dt-bindings/clock/qcom,qdu1000-gcc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ /* - * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights re= served. + * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights re= served. */ =20 #ifndef _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H @@ -138,6 +138,8 @@ #define GCC_AGGRE_NOC_ECPRI_GSI_CLK 128 #define GCC_PCIE_0_PIPE_CLK_SRC 129 #define GCC_PCIE_0_PHY_AUX_CLK_SRC 130 +#define GCC_GPLL1_OUT_EVEN 131 +#define GCC_DDRSS_ECPRI_GSI_CLK 132 =20 /* GCC resets */ #define GCC_ECPRI_CC_BCR 0 --=20 2.25.1 From nobody Mon Feb 9 09:46:39 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCDF9EB64D7 for ; Fri, 16 Jun 2023 10:58:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345385AbjFPK6D (ORCPT ); Fri, 16 Jun 2023 06:58:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53652 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345564AbjFPK5j (ORCPT ); Fri, 16 Jun 2023 06:57:39 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E7685592; Fri, 16 Jun 2023 03:50:31 -0700 (PDT) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35G9v443002190; Fri, 16 Jun 2023 10:50:27 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=X7K6Z30y2/dORtmqwSGrKhk/hqC1Y+VBb/4Mduq2opo=; b=AoqO4m3yvExf4519rmkBHnp26LsJdx0Jp2TXPy+6duzzV0rLqgcBbPJO5WPGquGB0yde UHV9Xleinj3vjlV9sw5ujN6CoR09mhRhbACRI2SG56AYbCKcRwdBiM8J5v+1vgeGa1N6 KDbWEdDdFr0TEEw04MGk92RryK4xN35tDWMbWQH8nFdr6DfE3vcn141sb1BRmnWsrPFh Y/ImGN+nRj5ZTNdC1IEdPPpjAHHj9LCv7FL2Owkp3qrFM/rrH7bThO5jjsvQQkadEnBD /ykh+0UL2jCYPyDTzM2nCauggx0tQOYpB9tYmhyW9w84QqF3T4MUL6zv15faM+ULOPnN Mw== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3r8n09g5r0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Jun 2023 10:50:27 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 35GAoQMH024458 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Jun 2023 10:50:26 GMT Received: from hu-imrashai-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 16 Jun 2023 03:50:21 -0700 From: Imran Shaik To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Melody Olvera , Taniya Das , Imran Shaik , , , , , Jagadeesh Kona , Satya Priya Kakitapalli , Ajit Pandey Subject: [PATCH 2/2] clk: qcom: gcc-qdu1000: Update GCC clocks and add support for GDSCs Date: Fri, 16 Jun 2023 16:19:41 +0530 Message-ID: <20230616104941.921555-3-quic_imrashai@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230616104941.921555-1-quic_imrashai@quicinc.com> References: <20230616104941.921555-1-quic_imrashai@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: FFUZMrSketR50FF6h5RlB0Wz67P4BI-S X-Proofpoint-ORIG-GUID: FFUZMrSketR50FF6h5RlB0Wz67P4BI-S X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-16_07,2023-06-16_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 mlxlogscore=999 spamscore=0 priorityscore=1501 malwarescore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306160097 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update the GCC clocks and add support for GDSCs for QDU1000 and QRU1000 SoCs. While at it, fix the PCIe pipe clock handling and add support for v2 variant. Signed-off-by: Taniya Das Signed-off-by: Imran Shaik --- drivers/clk/qcom/gcc-qdu1000.c | 162 ++++++++++++++++++++++----------- 1 file changed, 110 insertions(+), 52 deletions(-) diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index 5051769ad90c..5d8125c0eacc 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights re= served. */ =20 #include @@ -17,6 +17,7 @@ #include "clk-regmap-divider.h" #include "clk-regmap-mux.h" #include "clk-regmap-phy-mux.h" +#include "gdsc.h" #include "reset.h" =20 enum { @@ -370,16 +371,6 @@ static const struct clk_parent_data gcc_parent_data_6[= ] =3D { { .index =3D DT_TCXO_IDX }, }; =20 -static const struct parent_map gcc_parent_map_7[] =3D { - { P_PCIE_0_PIPE_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_7[] =3D { - { .index =3D DT_PCIE_0_PIPE_CLK_IDX }, - { .index =3D DT_TCXO_IDX }, -}; - static const struct parent_map gcc_parent_map_8[] =3D { { P_BI_TCXO, 0 }, { P_GCC_GPLL0_OUT_MAIN, 1 }, @@ -439,16 +430,15 @@ static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_s= rc =3D { }, }; =20 -static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src =3D { +static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src =3D { .reg =3D 0x9d064, - .shift =3D 0, - .width =3D 2, - .parent_map =3D gcc_parent_map_7, .clkr =3D { .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_pcie_0_pipe_clk_src", - .parent_data =3D gcc_parent_data_7, - .num_parents =3D ARRAY_SIZE(gcc_parent_data_7), + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_PCIE_0_PIPE_CLK_IDX, + }, + .num_parents =3D 1, .ops =3D &clk_regmap_phy_mux_ops, }, }, @@ -485,7 +475,7 @@ static struct clk_rcg2 gcc_aggre_noc_ecpri_dma_clk_src = =3D { .name =3D "gcc_aggre_noc_ecpri_dma_clk_src", .parent_data =3D gcc_parent_data_4, .num_parents =3D ARRAY_SIZE(gcc_parent_data_4), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }, }; =20 @@ -505,7 +495,7 @@ static struct clk_rcg2 gcc_aggre_noc_ecpri_gsi_clk_src = =3D { .name =3D "gcc_aggre_noc_ecpri_gsi_clk_src", .parent_data =3D gcc_parent_data_5, .num_parents =3D ARRAY_SIZE(gcc_parent_data_5), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }, }; =20 @@ -524,7 +514,7 @@ static struct clk_rcg2 gcc_gp1_clk_src =3D { .name =3D "gcc_gp1_clk_src", .parent_data =3D gcc_parent_data_1, .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }, }; =20 @@ -538,7 +528,7 @@ static struct clk_rcg2 gcc_gp2_clk_src =3D { .name =3D "gcc_gp2_clk_src", .parent_data =3D gcc_parent_data_1, .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }, }; =20 @@ -552,7 +542,7 @@ static struct clk_rcg2 gcc_gp3_clk_src =3D { .name =3D "gcc_gp3_clk_src", .parent_data =3D gcc_parent_data_1, .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }, }; =20 @@ -571,7 +561,7 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src =3D { .name =3D "gcc_pcie_0_aux_clk_src", .parent_data =3D gcc_parent_data_3, .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }, }; =20 @@ -591,7 +581,7 @@ static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src =3D= { .name =3D "gcc_pcie_0_phy_rchng_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }, }; =20 @@ -610,7 +600,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src =3D { .name =3D "gcc_pdm2_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }, }; =20 @@ -632,7 +622,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap0_s0_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src =3D { @@ -648,7 +638,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap0_s1_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src =3D { @@ -664,7 +654,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap0_s2_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src =3D { @@ -680,7 +670,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap0_s3_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src =3D { @@ -696,7 +686,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap0_s4_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src =3D { @@ -717,7 +707,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap0_s5_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src =3D { @@ -733,7 +723,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap0_s6_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src =3D { @@ -749,7 +739,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap0_s7_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src =3D { @@ -765,7 +755,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap1_s0_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src =3D { @@ -781,7 +771,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap1_s1_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src =3D { @@ -797,7 +787,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap1_s2_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src =3D { @@ -813,7 +803,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap1_s3_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src =3D { @@ -829,7 +819,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap1_s4_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src =3D { @@ -845,7 +835,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap1_s5_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src =3D { @@ -861,7 +851,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap1_s6_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src =3D { @@ -877,7 +867,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap1_s7_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src =3D { @@ -913,7 +903,7 @@ static struct clk_rcg2 gcc_sdcc5_apps_clk_src =3D { .name =3D "gcc_sdcc5_apps_clk_src", .parent_data =3D gcc_parent_data_8, .num_parents =3D ARRAY_SIZE(gcc_parent_data_8), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_floor_ops, }, }; =20 @@ -932,7 +922,7 @@ static struct clk_rcg2 gcc_sdcc5_ice_core_clk_src =3D { .name =3D "gcc_sdcc5_ice_core_clk_src", .parent_data =3D gcc_parent_data_2, .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_floor_ops, }, }; =20 @@ -946,7 +936,7 @@ static struct clk_rcg2 gcc_sm_bus_xo_clk_src =3D { .name =3D "gcc_sm_bus_xo_clk_src", .parent_data =3D gcc_parent_data_2, .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }, }; =20 @@ -965,7 +955,7 @@ static struct clk_rcg2 gcc_tsc_clk_src =3D { .name =3D "gcc_tsc_clk_src", .parent_data =3D gcc_parent_data_9, .num_parents =3D ARRAY_SIZE(gcc_parent_data_9), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }, }; =20 @@ -985,7 +975,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = =3D { .name =3D "gcc_usb30_prim_master_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }, }; =20 @@ -999,7 +989,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src= =3D { .name =3D "gcc_usb30_prim_mock_utmi_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }, }; =20 @@ -1013,7 +1003,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = =3D { .name =3D "gcc_usb3_prim_phy_aux_clk_src", .parent_data =3D gcc_parent_data_3, .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }, }; =20 @@ -1142,6 +1132,26 @@ static struct clk_branch gcc_ddrss_ecpri_dma_clk =3D= { }, }; =20 +static struct clk_branch gcc_ddrss_ecpri_gsi_clk =3D { + .halt_reg =3D 0x54298, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x54298, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x54298, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ddrss_ecpri_gsi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + static struct clk_branch gcc_ecpri_ahb_clk =3D { .halt_reg =3D 0x3a008, .halt_check =3D BRANCH_HALT_VOTED, @@ -1458,14 +1468,13 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk =3D= { =20 static struct clk_branch gcc_pcie_0_clkref_en =3D { .halt_reg =3D 0x9c004, - .halt_bit =3D 31, .halt_check =3D BRANCH_HALT_ENABLE, .clkr =3D { .enable_reg =3D 0x9c004, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_pcie_0_clkref_en", - .ops =3D &clk_branch_ops, + .ops =3D &clk_branch2_ops, }, }, }; @@ -2285,14 +2294,13 @@ static struct clk_branch gcc_tsc_etu_clk =3D { =20 static struct clk_branch gcc_usb2_clkref_en =3D { .halt_reg =3D 0x9c008, - .halt_bit =3D 31, .halt_check =3D BRANCH_HALT_ENABLE, .clkr =3D { .enable_reg =3D 0x9c008, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_usb2_clkref_en", - .ops =3D &clk_branch_ops, + .ops =3D &clk_branch2_ops, }, }, }; @@ -2402,6 +2410,39 @@ static struct clk_branch gcc_usb3_prim_phy_pipe_clk = =3D { }, }; =20 +static struct gdsc pcie_0_gdsc =3D { + .gdscr =3D 0x9d004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_pcie_0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc pcie_0_phy_gdsc =3D { + .gdscr =3D 0x7c004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .pd =3D { + .name =3D "gcc_pcie_0_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc usb30_prim_gdsc =3D { + .gdscr =3D 0x49004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_usb30_prim_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + static struct clk_regmap *gcc_qdu1000_clocks[] =3D { [GCC_AGGRE_NOC_ECPRI_DMA_CLK] =3D &gcc_aggre_noc_ecpri_dma_clk.clkr, [GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC] =3D &gcc_aggre_noc_ecpri_dma_clk_src.cl= kr, @@ -2534,6 +2575,14 @@ static struct clk_regmap *gcc_qdu1000_clocks[] =3D { [GCC_AGGRE_NOC_ECPRI_GSI_CLK] =3D &gcc_aggre_noc_ecpri_gsi_clk.clkr, [GCC_PCIE_0_PHY_AUX_CLK_SRC] =3D &gcc_pcie_0_phy_aux_clk_src.clkr, [GCC_PCIE_0_PIPE_CLK_SRC] =3D &gcc_pcie_0_pipe_clk_src.clkr, + [GCC_GPLL1_OUT_EVEN] =3D &gcc_gpll1_out_even.clkr, + [GCC_DDRSS_ECPRI_GSI_CLK] =3D NULL, +}; + +static struct gdsc *gcc_qdu1000_gdscs[] =3D { + [PCIE_0_GDSC] =3D &pcie_0_gdsc, + [PCIE_0_PHY_GDSC] =3D &pcie_0_phy_gdsc, + [USB30_PRIM_GDSC] =3D &usb30_prim_gdsc, }; =20 static const struct qcom_reset_map gcc_qdu1000_resets[] =3D { @@ -2597,10 +2646,13 @@ static const struct qcom_cc_desc gcc_qdu1000_desc = =3D { .num_clks =3D ARRAY_SIZE(gcc_qdu1000_clocks), .resets =3D gcc_qdu1000_resets, .num_resets =3D ARRAY_SIZE(gcc_qdu1000_resets), + .gdscs =3D gcc_qdu1000_gdscs, + .num_gdscs =3D ARRAY_SIZE(gcc_qdu1000_gdscs), }; =20 static const struct of_device_id gcc_qdu1000_match_table[] =3D { { .compatible =3D "qcom,qdu1000-gcc" }, + { .compatible =3D "qcom,qdu1000-gcc-v2" }, { } }; MODULE_DEVICE_TABLE(of, gcc_qdu1000_match_table); @@ -2617,6 +2669,12 @@ static int gcc_qdu1000_probe(struct platform_device = *pdev) /* Update FORCE_MEM_CORE_ON for gcc_pcie_0_mstr_axi_clk */ regmap_update_bits(regmap, 0x9d024, BIT(14), BIT(14)); =20 + if (of_device_is_compatible(pdev->dev.of_node, "qcom,qdu1000-gcc-v2")) { + gcc_qdu1000_clocks[GCC_DDRSS_ECPRI_GSI_CLK] =3D &gcc_ddrss_ecpri_gsi_clk= .clkr; + gcc_pcie_0_clkref_en.halt_check =3D BRANCH_HALT_DELAY; + gcc_usb2_clkref_en.halt_check =3D BRANCH_HALT_DELAY; + } + ret =3D qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); if (ret) --=20 2.25.1