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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000EDD6.mail.protection.outlook.com (10.167.241.210) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6500.22 via Frontend Transport; Fri, 16 Jun 2023 08:55:29 +0000 Received: from SATLEXMB06.amd.com (10.181.40.147) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Fri, 16 Jun 2023 03:55:24 -0500 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB06.amd.com (10.181.40.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Fri, 16 Jun 2023 03:55:23 -0500 Received: from xhdakumarma40u.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.23 via Frontend Transport; Fri, 16 Jun 2023 03:55:19 -0500 From: Amit Kumar Mahapatra To: , , , , , , , CC: , , , , , , Amit Kumar Mahapatra Subject: [PATCH v2 1/2] dt-bindings: mtd: jedec, spi-nor: Add DT property to avoid setting SRWD bit in status register Date: Fri, 16 Jun 2023 14:25:12 +0530 Message-ID: <20230616085513.17632-2-amit.kumar-mahapatra@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230616085513.17632-1-amit.kumar-mahapatra@amd.com> References: <20230616085513.17632-1-amit.kumar-mahapatra@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD6:EE_|DS7PR12MB8229:EE_ X-MS-Office365-Filtering-Correlation-Id: 815ed521-7859-49f6-0371-08db6e476f6d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jun 2023 08:55:29.3112 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 815ed521-7859-49f6-0371-08db6e476f6d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD6.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8229 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If the WP signal of the flash device is not connected and the software sets the status register write disable (SRWD) bit in the status register then thestatus register permanently becomes read-only. To avoid this added a new boolean DT property "broken-wp". If WP signal is not connected, then this property should be set in the DT to avoid setting the SRWD during status register write operation. Signed-off-by: Amit Kumar Mahapatra Reviewed-by: Conor Dooley --- .../devicetree/bindings/mtd/jedec,spi-nor.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Doc= umentation/devicetree/bindings/mtd/jedec,spi-nor.yaml index 89959e5c47ba..10a6df752f6f 100644 --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml @@ -70,6 +70,21 @@ properties: be used on such systems, to denote the absence of a reliable reset mechanism. =20 + broken-wp: + type: boolean + description: + The status register write disable (SRWD) bit in status register, com= bined + with the WP signal, provides hardware data protection for the device= . When + the SRWD bit is set to 1, and the WP signal is either driven LOW or = hard + strapped to LOW, the status register nonvolatile bits become read-on= ly and + the WRITE STATUS REGISTER operation will not execute. The only way t= o exit + this hardware-protected mode is to drive WP HIGH. If the WP signal o= f the + flash device is not connected then status register permanently becom= es + read-only as the SRWD bit cannot be reset. This boolean flag can be = used + on systems in which WP signal is not connected, to avoid setting the= SRWD + bit while writing the status register. If the WP signal is hard stra= pped + to LOW then it is not broken as it can be a valid use case. + reset-gpios: description: A GPIO line connected to the RESET (active low) signal of the device. --=20 2.17.1