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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000EDD6.mail.protection.outlook.com (10.167.241.210) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6500.22 via Frontend Transport; Fri, 16 Jun 2023 08:55:29 +0000 Received: from SATLEXMB06.amd.com (10.181.40.147) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Fri, 16 Jun 2023 03:55:24 -0500 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB06.amd.com (10.181.40.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Fri, 16 Jun 2023 03:55:23 -0500 Received: from xhdakumarma40u.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.23 via Frontend Transport; Fri, 16 Jun 2023 03:55:19 -0500 From: Amit Kumar Mahapatra To: , , , , , , , CC: , , , , , , Amit Kumar Mahapatra Subject: [PATCH v2 1/2] dt-bindings: mtd: jedec, spi-nor: Add DT property to avoid setting SRWD bit in status register Date: Fri, 16 Jun 2023 14:25:12 +0530 Message-ID: <20230616085513.17632-2-amit.kumar-mahapatra@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230616085513.17632-1-amit.kumar-mahapatra@amd.com> References: <20230616085513.17632-1-amit.kumar-mahapatra@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD6:EE_|DS7PR12MB8229:EE_ X-MS-Office365-Filtering-Correlation-Id: 815ed521-7859-49f6-0371-08db6e476f6d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jun 2023 08:55:29.3112 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 815ed521-7859-49f6-0371-08db6e476f6d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD6.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8229 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If the WP signal of the flash device is not connected and the software sets the status register write disable (SRWD) bit in the status register then thestatus register permanently becomes read-only. To avoid this added a new boolean DT property "broken-wp". If WP signal is not connected, then this property should be set in the DT to avoid setting the SRWD during status register write operation. Signed-off-by: Amit Kumar Mahapatra Reviewed-by: Conor Dooley --- .../devicetree/bindings/mtd/jedec,spi-nor.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Doc= umentation/devicetree/bindings/mtd/jedec,spi-nor.yaml index 89959e5c47ba..10a6df752f6f 100644 --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml @@ -70,6 +70,21 @@ properties: be used on such systems, to denote the absence of a reliable reset mechanism. =20 + broken-wp: + type: boolean + description: + The status register write disable (SRWD) bit in status register, com= bined + with the WP signal, provides hardware data protection for the device= . When + the SRWD bit is set to 1, and the WP signal is either driven LOW or = hard + strapped to LOW, the status register nonvolatile bits become read-on= ly and + the WRITE STATUS REGISTER operation will not execute. The only way t= o exit + this hardware-protected mode is to drive WP HIGH. If the WP signal o= f the + flash device is not connected then status register permanently becom= es + read-only as the SRWD bit cannot be reset. This boolean flag can be = used + on systems in which WP signal is not connected, to avoid setting the= SRWD + bit while writing the status register. If the WP signal is hard stra= pped + to LOW then it is not broken as it can be a valid use case. + reset-gpios: description: A GPIO line connected to the RESET (active low) signal of the device. --=20 2.17.1 From nobody Sat Feb 7 19:45:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD4B6EB64DA for ; Fri, 16 Jun 2023 08:55:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242804AbjFPIzq (ORCPT ); Fri, 16 Jun 2023 04:55:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244917AbjFPIze (ORCPT ); Fri, 16 Jun 2023 04:55:34 -0400 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2040.outbound.protection.outlook.com [40.107.237.40]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6136C30F4; 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Fri, 16 Jun 2023 03:55:28 -0500 Received: from xhdakumarma40u.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.23 via Frontend Transport; Fri, 16 Jun 2023 03:55:24 -0500 From: Amit Kumar Mahapatra To: , , , , , , , CC: , , , , , , Amit Kumar Mahapatra Subject: [PATCH v2 2/2] mtd: spi-nor: Avoid setting SRWD bit in SR if WP signal not connected Date: Fri, 16 Jun 2023 14:25:13 +0530 Message-ID: <20230616085513.17632-3-amit.kumar-mahapatra@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230616085513.17632-1-amit.kumar-mahapatra@amd.com> References: <20230616085513.17632-1-amit.kumar-mahapatra@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD4:EE_|LV8PR12MB9262:EE_ X-MS-Office365-Filtering-Correlation-Id: 21fd9a29-cb37-47a8-3d8e-08db6e476fc6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: h2xxJWOOph0QicVAa+eJDJzXkUp/JG/R27St2wuCyhY+sbKEqjMz8/R7jC4YhmXU2KtLqa+dmzV4KX/268zL6oC0BJ8LTPdfzUyHsu3jrgX0EzDlkRAadBmHY6hY3ysbZxOFkV0ntyIpqFH0c9gGAvaRgz000mU6KMg3vz0GPa+tQym1aK2Td37XNQuITJrXttz7axDAK5wM0p75Gg+Ss9Gh8jUaawL3xxVm7h/Tt54lmRoX/pbVfjp4tDNd+dMQFaqQ013ok8CywyNu7wPQof9DP9effFj+nRJwt5aA/0naElCzR05WH22VUSZPfZVrZiXCiNtYD83TOEpz53PdxTw6E/1ZBXFAovvQc0pH19agmjxFJUnUdC9VXihcyS7Fxx5r2tTK6IDGD5TTq6Ze9dJmQOU9nkKVvnVHxXlcAOMX20i9YTiuaxv8BDaN6PsXvI3m5X5IFaMnVVrAT3Fe9yasjTejWKqkSvxCzbShrDl+Lc07KbOZEhhaqp2syS87YTbLnOtGJo+B6A+HOS2kqBk6njBB3HFEMsUzqkRFvTHzFYXn9LiQSakSJFWgCAILR5LfGWX/JCuZoum7+YMw8XL8b75atK8+DpXrhkkaoAMFXo21ak/hh+pLIRLjknLkB8LOUKyPd8Z/bYRvw9xGC+UqjG4qlDY9lgwX2gUPwHkSz4T+0RVvWs0iXB1gDOfHnmuqetmHRfv9CbN7sV1E9KDkpKjCPMmnjATKiC66ngPzmn3UUZwkEeeWgWnerwfuBghzWzI2+Vxr+1QvinCwQg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(136003)(376002)(396003)(39860400002)(346002)(451199021)(46966006)(40470700004)(36840700001)(40460700003)(82740400003)(5660300002)(81166007)(356005)(336012)(2616005)(83380400001)(1076003)(426003)(186003)(2906002)(36860700001)(7416002)(47076005)(26005)(478600001)(40480700001)(70206006)(6666004)(8936002)(316002)(8676002)(41300700001)(86362001)(82310400005)(36756003)(4326008)(70586007)(54906003)(110136005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jun 2023 08:55:29.8959 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 21fd9a29-cb37-47a8-3d8e-08db6e476fc6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9262 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Setting the status register write disable (SRWD) bit in the status register (SR) with WP signal of the flash not connected will configure the SR permanently as read-only. If WP signal is not connected, avoid setting SRWD bit while writing the SR during flash protection. Signed-off-by: Amit Kumar Mahapatra --- drivers/mtd/spi-nor/core.c | 3 +++ drivers/mtd/spi-nor/core.h | 1 + drivers/mtd/spi-nor/swp.c | 9 +++++++-- 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 0bb0ad14a2fc..81b57c51f41c 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2864,6 +2864,9 @@ static void spi_nor_init_flags(struct spi_nor *nor) if (flags & NO_CHIP_ERASE) nor->flags |=3D SNOR_F_NO_OP_CHIP_ERASE; =20 + if (of_property_read_bool(np, "broken-wp")) + nor->flags |=3D SNOR_F_BROKEN_WP; + if (flags & SPI_NOR_RWW && nor->info->n_banks > 1 && !nor->controller_ops) nor->flags |=3D SNOR_F_RWW; diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 4fb5ff09c63a..6ac932eba913 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -132,6 +132,7 @@ enum spi_nor_option_flags { SNOR_F_SWP_IS_VOLATILE =3D BIT(13), SNOR_F_RWW =3D BIT(14), SNOR_F_ECC =3D BIT(15), + SNOR_F_BROKEN_WP =3D BIT(16), }; =20 struct spi_nor_read_command { diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index 0ba716e84377..5d91f152c2cc 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -214,8 +214,13 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t= ofs, uint64_t len) =20 status_new =3D (status_old & ~mask & ~tb_mask) | val; =20 - /* Disallow further writes if WP pin is asserted */ - status_new |=3D SR_SRWD; + /* + * Disallow further writes if WP pin is not broken. WP pin is + * considered broken only if the WP signal of the flash device + * is not connected. + */ + if (!(nor->flags & SNOR_F_BROKEN_WP)) + status_new |=3D SR_SRWD; =20 if (!use_top) status_new |=3D tb_mask; --=20 2.17.1