From nobody Sun Feb 8 09:27:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E204CEB64D8 for ; Fri, 16 Jun 2023 07:20:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244726AbjFPHU0 (ORCPT ); Fri, 16 Jun 2023 03:20:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57818 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243483AbjFPHUN (ORCPT ); Fri, 16 Jun 2023 03:20:13 -0400 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CEDCE1FF7; Fri, 16 Jun 2023 00:20:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1686900012; x=1718436012; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=d5CSDyfpcwogrVwSeDi4wB4m0Q0tiotgMun3y07NDXo=; b=LcrPEXTYz4v5ectpBfYHZD0Zos+EUC4gipycesLIHv+kWUtQ1bBAyVRE GCxJ2fJjUaC+nK8uFkg9Y5su7JfmZhdilM3nW0+Dg9+JCeBTtXGjU1szr CUXgzXsRBHi1YwC7Ts7FiyuwKfx/x70T+jzu1UtPt2EeYm8KajMkFmGHI CH7FmonC387FJffvPBorUzeS6e6fib7X2E+OTHIcmZRuRQxcC/UjLDBpl dPShbIPIgQOifUEJGKp95GVfD/YtFmTwRNNEtyli0La3wIOBvs0ukdFrc Npt/1tKQ0GrCPNf8T8rEFW7Td73EGunUiVQhI1vY8wPsgKSqoKcsJvzV6 A==; X-IronPort-AV: E=Sophos;i="6.00,246,1681164000"; d="scan'208";a="31460051" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 16 Jun 2023 09:20:07 +0200 Received: from steina-w.tq-net.de (unknown [10.123.53.21]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by vtuxmail01.tq-net.de (Postfix) with ESMTPSA id 7612E280086; Fri, 16 Jun 2023 09:20:07 +0200 (CEST) From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Fabio Estevam , Marek Vasut Cc: Markus Niebel , Pengutronix Kernel Team , NXP Linux Team , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux@ew.tq-group.com, Alexander Stein Subject: [PATCH v2 1/3] dt-bindings: arm: add TQMa93xxLA SOM Date: Fri, 16 Jun 2023 09:20:03 +0200 Message-Id: <20230616072005.1781043-2-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230616072005.1781043-1-alexander.stein@ew.tq-group.com> References: <20230616072005.1781043-1-alexander.stein@ew.tq-group.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Markus Niebel TQMa93xxLA is a SOM variant in the TQ-Systems GmbH TQMa93xx series using NXP i.MX93 CPU on an LGA type board. MBa93xxCA is a starterkit base board for TQMa93xxLA on an adapter board. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/arm/fsl.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 2510eaa8906dd..8048c7f6a299d 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1219,6 +1219,25 @@ properties: - fsl,imxrt1170-evk # i.MXRT1170 EVK Board - const: fsl,imxrt1170 =20 + - description: + TQMa93xxLA and TQMa93xxCA are two series of feature compatible S= OM + using NXP i.MX93 SOC in 11x11 mm package. + TQMa93xxLA is designed to be soldered on different carrier board= s. + TQMa93xxCA is a compatible variant using board to board connecto= rs. + All SOM and CPU variants use the same device tree hence only one + compatible is needed. Bootloader disables all features not prese= nt + in the assembled SOC. + MBa93xxCA mainboard can be used as starterkit for the SOM + soldered on an adapter board or for the connector variant + MBa93xxLA mainboard is a single board computer using the soldera= ble + SOM variant + items: + - enum: + - tq,imx93-tqma9352-mba93xxca # TQ-Systems GmbH i.MX93 TQMa9= 3xxCA/LA SOM on MBa93xxCA + - tq,imx93-tqma9352-mba93xxla # TQ-Systems GmbH i.MX93 TQMa9= 3xxLA SOM on MBa93xxLA SBC + - const: tq,imx93-tqma9352 # TQ-Systems GmbH i.MX93 TQMa9= 3xxCA/LA SOM + - const: fsl,imx93 + - description: Freescale Vybrid Platform Device Tree Bindings =20 --=20 2.34.1 From nobody Sun Feb 8 09:27:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24989EB64D7 for ; Fri, 16 Jun 2023 07:20:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243768AbjFPHUi (ORCPT ); Fri, 16 Jun 2023 03:20:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58130 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244858AbjFPHU0 (ORCPT ); Fri, 16 Jun 2023 03:20:26 -0400 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2BC8D2942; Fri, 16 Jun 2023 00:20:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1686900013; x=1718436013; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VDGTdd2asmGXzZ9OXdY4A5e4jH7X+LG0Bb1uLvLm6Ww=; b=U/6c4kLxNAovbOjT0M78uPEyk0/fzkjTf8SFFWfCK6EAHFC1JJYb/G/V dJC5b6Xy2SppDHkRB0JSnChHljyKKcM0AlDIMh2XnvkmUhX07cROUOV52 Y98gVMOknosgaYvKTP/9GpXrbFH3JmNmIqJfhz/VAml/5AgvVlE2AdKUa xJO1AUofwXoqMDI4xcfFf+y0NB4kd21YTjgIDmI9Gatuajt8JlEqYEGrN oVaZ89YRZ7Sl5guy5kxq/cGrYoyP2dOEZK9ZLINDBBzqDLCTKR6hRg0vw efKp67fgse5lTuFXoETMd1lNnNgve61ttuCtNEQGeqY0MESZ83glDALG3 A==; X-IronPort-AV: E=Sophos;i="6.00,246,1681164000"; d="scan'208";a="31460052" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 16 Jun 2023 09:20:08 +0200 Received: from steina-w.tq-net.de (unknown [10.123.53.21]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by vtuxmail01.tq-net.de (Postfix) with ESMTPSA id B7BB0280087; Fri, 16 Jun 2023 09:20:07 +0200 (CEST) From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Fabio Estevam , Marek Vasut Cc: Alexander Stein , Pengutronix Kernel Team , NXP Linux Team , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux@ew.tq-group.com Subject: [PATCH v2 2/3] arm64: dts: freescale: add initial device tree for MBa93xxLA SBC board Date: Fri, 16 Jun 2023 09:20:04 +0200 Message-Id: <20230616072005.1781043-3-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230616072005.1781043-1-alexander.stein@ew.tq-group.com> References: <20230616072005.1781043-1-alexander.stein@ew.tq-group.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds support for TQMa93xx module and MBa93xxLA SBC board. TQMa93xx is a SOM using i.MX93 SOC. The SOM features PMIC, RAM, e-MMC and some optional peripherals like SPI-NOR, RTC, EEPROM, gyroscope and secure element. TQMa93xxLA is a solder on type SOM and can be used directly on MBa93XXLA. TQMa93xxCA is a feature compatible, socketable type SOM. Signed-off-by: Alexander Stein --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../freescale/imx93-tqma9352-mba93xxla.dts | 629 ++++++++++++++++++ .../boot/dts/freescale/imx93-tqma9352.dtsi | 213 ++++++ 3 files changed, 843 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.= dts create mode 100644 arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index a750be13ace89..2d5e9f495a646 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -141,6 +141,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8qxp-colibri-iris-v2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8qxp-mek.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-11x11-evk.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx93-tqma9352-mba93xxla.dtb =20 imx8mm-venice-gw72xx-0x-imx219-dtbs :=3D imx8mm-venice-gw73xx-0x.dtb imx8m= m-venice-gw73xx-0x-imx219.dtbo imx8mm-venice-gw72xx-0x-rs232-rts-dtbs :=3D imx8mm-venice-gw72xx-0x.dtb im= x8mm-venice-gw72xx-0x-rs232-rts.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts b/a= rch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts new file mode 100644 index 0000000000000..a98a6592ecd83 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts @@ -0,0 +1,629 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2022-2023 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + * Author: Alexander Stein + */ +/dts-v1/; + +#include +#include +#include +#include +#include +#include "imx93-tqma9352.dtsi" + +/{ + model =3D "TQ-Systems i.MX93 TQMa93xxLA on MBa93xxLA SBC"; + compatible =3D "tq,imx93-tqma9352-mba93xxla", + "tq,imx93-tqma9352", "fsl,imx93"; + + chosen { + stdout-path =3D &lpuart1; + }; + + aliases { + eeprom0 =3D &eeprom0; + rtc0 =3D &pcf85063; + rtc1 =3D &bbnsm_rtc; + }; + + backlight_lvds: backlight { + compatible =3D "pwm-backlight"; + pwms =3D <&tpm5 0 5000000 0>; + brightness-levels =3D <0 4 8 16 32 64 128 255>; + default-brightness-level =3D <7>; + power-supply =3D <®_12v0>; + enable-gpios =3D <&expander2 2 GPIO_ACTIVE_HIGH>; + status =3D "disabled"; + }; + + dp_refclk: dp-refclk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <26000000>; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + autorepeat; + + switch-a { + label =3D "switcha"; + linux,code =3D ; + gpios =3D <&expander0 6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + switch-b { + label =3D "switchb"; + linux,code =3D ; + gpios =3D <&expander0 7 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio-leds { + compatible =3D "gpio-leds"; + + led-1 { + color =3D ; + function =3D LED_FUNCTION_STATUS; + gpios =3D <&expander2 6 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "default-on"; + }; + + led-2 { + color =3D ; + function =3D LED_FUNCTION_HEARTBEAT; + gpios =3D <&expander2 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + }; + + iio-hwmon { + compatible =3D "iio-hwmon"; + io-channels =3D <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>; + }; + + reg_3v3: regulator-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_3V3_MB"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + reg_3v8: regulator-3v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_3V8"; + regulator-min-microvolt =3D <3800000>; + regulator-max-microvolt =3D <3800000>; + gpio =3D <&expander0 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* TODO: this is supply for IOT module */ + regulator-always-on; + }; + + reg_5v0: regulator-5v0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_5V0_MB"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; + + reg_12v0: regulator-12v0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_12V"; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + gpio =3D <&expander1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&adc1 { + status =3D "okay"; +}; + +&eqos { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_eqos>; + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðphy_eqos>; + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy_eqos: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_eqos_phy>; + reset-gpios =3D <&expander1 0 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <500000>; + reset-deassert-us =3D <50000>; + ti,rx-internal-delay =3D ; + ti,tx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel =3D ; + enet-phy-lane-no-swap; + interrupt-parent =3D <&gpio3>; + interrupts =3D <26 IRQ_TYPE_EDGE_FALLING>; + }; + }; +}; + +&fec { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_fec>; + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðphy_fec>; + fsl,magic-packet; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <5000000>; + + ethphy_fec: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_fec_phy>; + reset-gpios =3D <&expander1 1 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <500000>; + reset-deassert-us =3D <50000>; + ti,rx-internal-delay =3D ; + ti,tx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel =3D ; + enet-phy-lane-no-swap; + interrupt-parent =3D <&gpio3>; + interrupts =3D <27 IRQ_TYPE_EDGE_FALLING>; + }; + }; +}; + +&flexcan1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan1>; + xceiver-supply =3D <®_3v3>; + status =3D "okay"; +}; + +&flexcan2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan2>; + xceiver-supply =3D <®_3v3>; + status =3D "okay"; +}; + +&gpio1 { + expander-irq-hog { + gpio-hog; + gpios =3D <12 GPIO_ACTIVE_LOW>; + input; + line-name =3D "PEX_INT#"; + }; + + rtc-irq-hog { + gpio-hog; + gpios =3D <14 GPIO_ACTIVE_LOW>; + input; + line-name =3D "RTC_EVENT#"; + }; +}; + +&gpio3 { + ethphy-eqos-irq-hog { + gpio-hog; + gpios =3D <26 GPIO_ACTIVE_LOW>; + input; + line-name =3D "ENET0_IRQ#"; + }; + + ethphy-fec-irq-hog { + gpio-hog; + gpios =3D <27 GPIO_ACTIVE_LOW>; + input; + line-name =3D "ENET1_IRQ#"; + }; +}; + +&lpi2c3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <400000>; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&pinctrl_lpi2c3>; + pinctrl-1 =3D <&pinctrl_lpi2c3>; + status =3D "okay"; + + temperature-sensor@1c { + compatible =3D "nxp,se97b", "jedec,jc-42.4-temp"; + reg =3D <0x1c>; + }; + + eeprom2: eeprom@54 { + compatible =3D "nxp,se97b", "atmel,24c02"; + reg =3D <0x54>; + pagesize =3D <16>; + vcc-supply =3D <®_3v3>; + }; + + expander0: gpio@70 { + compatible =3D "nxp,pca9538"; + reg =3D <0x70>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pexp_irq>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <12 IRQ_TYPE_LEVEL_LOW>; + vcc-supply =3D <®_3v3>; + gpio-line-names =3D "3V8_EN", "", + "", "IOT_PWRKEY", + "IOT_RESET", "IOT_W_DISABLE", + "BUTTON_A#", "BUTTON_B#"; + + /* + * Controls the IOT W_DISABLE pin which is low active + * as disable signal but inverted as seen from the CPU. + * The output-low states, the signal is + * inactive, e.g. not disabled + */ + iot_wdisable_hog: iot-wdisable-hog { + gpio-hog; + gpios =3D <5 GPIO_ACTIVE_HIGH>; + output-low; + line-name =3D "IOT_W_DISABLE"; + }; + }; + + expander1: gpio@71 { + compatible =3D "nxp,pca9538"; + reg =3D <0x71>; + gpio-controller; + #gpio-cells =3D <2>; + vcc-supply =3D <®_3v3>; + gpio-line-names =3D "ENET1_RESET#", "ENET2_RESET#", + "USB_RESET#", "", + "WLAN_PD#", "WLAN_W_DISABLE#", + "WLAN_PERST#", "12V_EN"; + + /* + * Controls the WiFi card PD pin which is low active + * as power down signal. The output-low states, the signal + * is inactive, e.g. not power down + */ + wlan-pd-hog { + gpio-hog; + gpios =3D <4 GPIO_ACTIVE_LOW>; + output-low; + line-name =3D "WLAN_PD#"; + }; + + /* + * Controls the WiFi card disable pin which is low active + * as disable signal. The output-low states, the signal + * is inactive, e.g. not disabled + */ + wlan-wdisable-hog { + gpio-hog; + gpios =3D <5 GPIO_ACTIVE_LOW>; + output-low; + line-name =3D "WLAN_W_DISABLE#"; + }; + + /* + * Controls the WiFi card reset pin which is low active + * as reset signal. The output-low states, the signal + * is inactive, e.g. not in reset + */ + wlan-perst-hog { + gpio-hog; + gpios =3D <6 GPIO_ACTIVE_LOW>; + output-low; + line-name =3D "WLAN_PERST#"; + }; + }; + + expander2: gpio@72 { + compatible =3D "nxp,pca9538"; + reg =3D <0x72>; + gpio-controller; + #gpio-cells =3D <2>; + vcc-supply =3D <®_3v3>; + gpio-line-names =3D "LCD_RESET#", "LCD_PWR_EN", + "LCD_BL_EN", "DP_EN", + "MIPI_CSI_EN", "MIPI_CSI_RST#", + "USER_LED1", "USER_LED2"; + }; +}; + +&lpi2c5 { + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <400000>; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&pinctrl_lpi2c5>; + pinctrl-1 =3D <&pinctrl_lpi2c5>; + status =3D "okay"; + + dp_bridge: dp-bridge@f { + compatible =3D "toshiba,tc358767"; + reg =3D <0x0f>; + reset-gpios =3D <&expander2 3 GPIO_ACTIVE_LOW>; + clock-names =3D "ref"; + clocks =3D <&dp_refclk>; + toshiba,hpd-pin =3D <0>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dp_dsi_in: endpoint { + }; + }; + }; + }; +}; + +&lpuart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; + status =3D "okay"; +}; + +&lpuart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + status =3D "okay"; +}; + +/* disabled per default, console for M33 */ +&lpuart3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart3>; + status =3D "disabled"; +}; + +&lpuart6 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart6>; + status =3D "okay"; +}; + +&lpuart8 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart8>; + status =3D "okay"; +}; + +&pcf85063 { + /* RTC_EVENT# is connected on MBa93xxLA */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pcf85063>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <14 IRQ_TYPE_EDGE_FALLING>; +}; + +&tpm5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_tpm5>; +}; + +&usdhc2 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; + cd-gpios =3D <&gpio3 00 GPIO_ACTIVE_LOW>; + vmmc-supply =3D <®_usdhc2_vmmc>; + bus-width =3D <4>; + no-sdio; + no-mmc; + disable-wp; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins =3D < + /* PD | FSEL_2 | DSE X4 */ + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x51e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000051e + /* PD | FSEL_2 | DSE X6 */ + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + /* PD | FSEL_3 | DSE X6 */ + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + /* PD | FSEL_2 | DSE X4 */ + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x51e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x51e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x51e + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x51e + /* PD | FSEL_3 | DSE X3 */ + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e + >; + }; + + pinctrl_eqos_phy: eqosphygrp { + fsl,pins =3D < + MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x1306 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins =3D < + /* PD | FSEL_2 | DSE X4 */ + MX93_PAD_ENET2_MDC__ENET1_MDC 0x51e + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000051e + /* PD | FSEL_2 | DSE X6 */ + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e + /* PD | FSEL_3 | DSE X6 */ + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + /* PD | FSEL_2 | DSE X4 */ + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x51e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x51e + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x51e + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x51e + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x51e + /* PD | FSEL_3 | DSE X3 */ + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e + >; + }; + + pinctrl_fec_phy: fecphygrp { + fsl,pins =3D < + MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x1306 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins =3D < + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + MX93_PAD_PDM_CLK__CAN1_TX 0x139e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO25__CAN2_TX 0x139e + MX93_PAD_GPIO_IO27__CAN2_RX 0x139e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e + MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e + >; + }; + + pinctrl_pcf85063: pcf85063grp { + fsl,pins =3D < + MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x1306 + >; + }; + + pinctrl_pexp_irq: pexpirqgrp { + fsl,pins =3D < + MX93_PAD_SAI1_TXC__GPIO1_IO12 0x1306 + >; + }; + + pinctrl_tpm5: tpm5grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO06__TPM5_CH0 0x57e + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins =3D < + MX93_PAD_I2C2_SCL__GPIO1_IO02 0x1306 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins =3D < + MX93_PAD_UART2_TXD__LPUART2_TX 0x31e + MX93_PAD_UART2_RXD__LPUART2_RX 0x31e + MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x31e + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO14__LPUART3_TX 0x31e + MX93_PAD_GPIO_IO15__LPUART3_RX 0x31e + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e + MX93_PAD_GPIO_IO05__LPUART6_RX 0x31e + >; + }; + + pinctrl_uart8: uart8grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO12__LPUART8_TX 0x31e + MX93_PAD_GPIO_IO13__LPUART8_RX 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins =3D < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + pinctrl_usdhc2_hs: usdhc2hsgrp { + fsl,pins =3D < + /* HYS | PD | PU | FSEL_3 | DSE X5 */ + MX93_PAD_SD2_CLK__USDHC2_CLK 0x17be + /* HYS | PD | PU | FSEL_3 | DSE X4 */ + MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e + /* HYS | PD | PU | FSEL_3 | DSE X3 */ + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + /* PD | PU | FSEL_2 | DSE X3 */ + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x50e + >; + }; + + pinctrl_usdhc2_uhs: usdhc2uhsgrp { + fsl,pins =3D < + /* HYS | PD | PU | FSEL_3 | DSE X6 */ + MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe + /* HYS | PD | PU | FSEL_3 | DSE X4 */ + MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e + /* PD | PU | FSEL_2 | DSE X3 */ + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x50e + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi b/arch/arm64= /boot/dts/freescale/imx93-tqma9352.dtsi new file mode 100644 index 0000000000000..2f2bb2c49f04c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi @@ -0,0 +1,213 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2022 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + */ + +#include "imx93.dtsi" + +/{ + model =3D "TQ-Systems i.MX93 TQMa93xxLA/TQMa93xxCA SOM"; + compatible =3D "tq,imx93-tqma9352", "fsl,imx93"; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + linux,cma { + compatible =3D "shared-dma-pool"; + reusable; + alloc-ranges =3D <0 0x60000000 0 0x40000000>; + size =3D <0 0x10000000>; + linux,cma-default; + }; + }; + + reg_v1v8: regulator-v1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_1V8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + reg_v3v3: regulator-v3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + /* SD2 RST# via PMIC SW_EN */ + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usdhc2_vmmc>; + regulator-name =3D "VSD_3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <®_v3v3>; + gpio =3D <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&adc1 { + vref-supply =3D <®_v1v8>; +}; + +&flexspi1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexspi1>; + status =3D "okay"; + + flash0: flash@0 { + reg =3D <0>; + compatible =3D "jedec,spi-nor"; + /* + * no DQS, RXCLKSRC internal loop back, max 66 MHz + * clk framework uses CLK_DIVIDER_ROUND_CLOSEST + * selected value together with root from + * IMX93_CLK_SYS_PLL_PFD1 @ 800.000.000 Hz helps to + * respect the maximum value. + */ + spi-max-frequency =3D <62000000>; + spi-tx-bus-width =3D <4>; + spi-rx-bus-width =3D <4>; + }; +}; + +&gpio1 { + pmic-irq-hog { + gpio-hog; + gpios =3D <2 GPIO_ACTIVE_LOW>; + input; + line-name =3D "PMIC_IRQ#"; + }; +}; + +&lpi2c1 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&pinctrl_lpi2c1>; + pinctrl-1 =3D <&pinctrl_lpi2c1>; + status =3D "okay"; + + se97_som: temperature-sensor@1b { + compatible =3D "nxp,se97b", "jedec,jc-42.4-temp"; + reg =3D <0x1b>; + }; + + pcf85063: rtc@51 { + compatible =3D "nxp,pcf85063a"; + reg =3D <0x51>; + quartz-load-femtofarads =3D <7000>; + }; + + eeprom0: eeprom@53 { + compatible =3D "nxp,se97b", "atmel,24c02"; + reg =3D <0x53>; + pagesize =3D <16>; + read-only; + vcc-supply =3D <®_v3v3>; + }; + + eeprom1: eeprom@57 { + compatible =3D "atmel,24c64"; + reg =3D <0x57>; + pagesize =3D <32>; + vcc-supply =3D <®_v3v3>; + }; + + /* protectable identification memory (part of M24C64-D @57) */ + eeprom@5f { + compatible =3D "st,24c64", "atmel,24c64"; + reg =3D <0x5f>; + size =3D <32>; + pagesize =3D <32>; + vcc-supply =3D <®_v3v3>; + }; + + imu@6a { + compatible =3D "st,ism330dhcx"; + reg =3D <0x6a>; + vdd-supply =3D <®_v3v3>; + vddio-supply =3D <®_v3v3>; + }; +}; + +&usdhc1 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1>; + pinctrl-2 =3D <&pinctrl_usdhc1>; + bus-width =3D <8>; + non-removable; + no-sdio; + no-sd; + status =3D "okay"; +}; + +&wdog3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_wdog>; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_flexspi1: flexspi1grp { + fsl,pins =3D < + MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x3fe + MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x3fe + MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x3fe + MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x3fe + MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x3fe + MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x3fe + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins =3D < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_pca9451: pca9451grp { + fsl,pins =3D < + MX93_PAD_I2C2_SDA__GPIO1_IO03 0x1306 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins =3D < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x1306 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + /* HYS | PU | PD | FSEL_3 | X5 */ + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x17be + /* HYS | PU | FSEL_3 | X5 */ + MX93_PAD_SD1_CMD__USDHC1_CMD 0x13be + /* HYS | PU | FSEL_3 | X4 */ + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x139e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x139e + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x139e + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x139e + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x139e + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x139e + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x139e + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x139e + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins =3D < + MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e + >; + }; +}; --=20 2.34.1 From nobody Sun Feb 8 09:27:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 306C0EB64DA for ; Fri, 16 Jun 2023 07:20:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244987AbjFPHUd (ORCPT ); Fri, 16 Jun 2023 03:20:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244798AbjFPHUZ (ORCPT ); Fri, 16 Jun 2023 03:20:25 -0400 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36444296B; Fri, 16 Jun 2023 00:20:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; 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Fri, 16 Jun 2023 09:20:08 +0200 (CEST) From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Fabio Estevam , Marek Vasut Cc: Alexander Stein , Pengutronix Kernel Team , NXP Linux Team , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux@ew.tq-group.com Subject: [PATCH v2 3/3] arm64: defconfig: Enable i.MX93 devices Date: Fri, 16 Jun 2023 09:20:05 +0200 Message-Id: <20230616072005.1781043-4-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230616072005.1781043-1-alexander.stein@ew.tq-group.com> References: <20230616072005.1781043-1-alexander.stein@ew.tq-group.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" These drivers are used on i.MX93 based devices. Signed-off-by: Alexander Stein --- arch/arm64/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 57c6b7bb88d44..81ce5c4b6020a 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -427,6 +427,7 @@ CONFIG_TOUCHSCREEN_GOODIX=3Dm CONFIG_TOUCHSCREEN_ELAN=3Dm CONFIG_TOUCHSCREEN_EDT_FT5X06=3Dm CONFIG_INPUT_MISC=3Dy +CONFIG_INPUT_BBNSM_PWRKEY=3Dm CONFIG_INPUT_PM8941_PWRKEY=3Dy CONFIG_INPUT_PM8XXX_VIBRATOR=3Dm CONFIG_INPUT_TPS65219_PWRBUTTON=3Dm @@ -676,6 +677,7 @@ CONFIG_SUNXI_WATCHDOG=3Dm CONFIG_NPCM7XX_WATCHDOG=3Dy CONFIG_IMX2_WDT=3Dy CONFIG_IMX_SC_WDT=3Dm +CONFIG_IMX7ULP_WDT=3Dm CONFIG_QCOM_WDT=3Dm CONFIG_MESON_GXBB_WATCHDOG=3Dm CONFIG_MESON_WATCHDOG=3Dm @@ -1091,6 +1093,7 @@ CONFIG_RTC_DRV_ARMADA38X=3Dy CONFIG_RTC_DRV_PM8XXX=3Dm CONFIG_RTC_DRV_TEGRA=3Dy CONFIG_RTC_DRV_SNVS=3Dm +CONFIG_RTC_DRV_BBNSM=3Dm CONFIG_RTC_DRV_IMX_SC=3Dm CONFIG_RTC_DRV_MT6397=3Dm CONFIG_RTC_DRV_XGENE=3Dy @@ -1406,6 +1409,7 @@ CONFIG_ARM_SPE_PMU=3Dm CONFIG_ARM_DMC620_PMU=3Dm CONFIG_HISI_PMU=3Dy CONFIG_NVMEM_IMX_OCOTP=3Dy +CONFIG_NVMEM_IMX_OCOTP_ELE=3Dm CONFIG_NVMEM_IMX_OCOTP_SCU=3Dy CONFIG_NVMEM_LAYERSCAPE_SFP=3Dm CONFIG_NVMEM_MESON_EFUSE=3Dm --=20 2.34.1