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[94.181.180.60]) by smtp.gmail.com with ESMTPSA id h7-20020ac25967000000b004f13f4ec267sm244451lfp.186.2023.06.15.07.44.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 07:44:51 -0700 (PDT) From: Aleksandr Shubin To: linux-kernel@vger.kernel.org Cc: Aleksandr Shubin , Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Cristian Ciocaltea , Maxime Ripard , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org Subject: [PATCH v1 1/3] dt-bindings: pwm: Add binding for Allwinner D1/T113-S3/R329 PWM controller Date: Thu, 15 Jun 2023 17:43:56 +0300 Message-Id: <20230615144423.828698-2-privatesub2@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230615144423.828698-1-privatesub2@gmail.com> References: <20230615144423.828698-1-privatesub2@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Allwinner's D1, T113-S3 and R329 SoCs have a new pwm controller witch is different from the previous pwm-sun4i. D1 and T113s SoCs have one PWM controller with 8 channels. R329 SoC has two PWM controllers in both power domains, one of them has 9 channels (CPUX one) and the other has 6 (CPUS one). Add a device tree binding for them. Signed-off-by: Aleksandr Shubin --- .../bindings/pwm/allwinner,sun20i-pwm.yaml | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/allwinner,sun20i-= pwm.yaml diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yam= l b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml new file mode 100644 index 000000000000..e5f9cb2d5c4f --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/allwinner,sun20i-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner D1, T113-S3 and R329 PWM + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: allwinner,sun20i-d1-pwm + + reg: + maxItems: 1 + + "#pwm-cells": + const: 3 + + clocks: + items: + - description: 24 MHz oscillator + - description: Bus Clock + + clock-names: + items: + - const: hosc + - const: bus + + resets: + items: + - description: module reset + + allwinner,pwm-channels: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The number of PWM channels configured for this instance + +required: + - compatible + - reg + - "#pwm-cells" + - clocks + - clock-names + - resets + - allwinner,pwm-channels + +additionalProperties: false + +examples: + - | + #include + #include + + pwm: pwm@2000c00 { + compatible =3D "allwinner,sun20i-d1-pwm"; + reg =3D <0x02000c00 0x400>; + clocks =3D <&dcxo>, <&ccu CLK_BUS_PWM>; + clock-names =3D "hosc", "bus"; + resets =3D <&ccu RST_BUS_PWM>; + allwinner,pwm-channels =3D <8>; + #pwm-cells =3D <0x3>; + }; + +... --=20 2.25.1 From nobody Mon Feb 9 00:25:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 975B1EB64DC for ; Thu, 15 Jun 2023 14:45:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344042AbjFOOpR (ORCPT ); Thu, 15 Jun 2023 10:45:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59704 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241542AbjFOOpN (ORCPT ); Thu, 15 Jun 2023 10:45:13 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 394DE2738; Thu, 15 Jun 2023 07:45:11 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id 2adb3069b0e04-4f611ac39c5so10878072e87.2; Thu, 15 Jun 2023 07:45:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686840309; x=1689432309; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Od+eFJu5Un7KQxaLhPRr3IFDtHMK7wuQZd5iaWBOH10=; b=fUz6JLSdDRz/tVup/zvfXMmNhkAvFf4elZjb866w5j9o8w7UZJvZ4fYnShm7SWfW9s pJFq27oqPsbABnjkpLREi8tW7t9kfgg7ogacwDKLOfAmx28X9DX53cCvZHFf3DSrTRsq DHY7Wfwn6QbUf9ArWK/S/TuneYwnSOo0/3Cb2ua2lZjdADxh0ZIiEqWju7JP0yO3XlMF YqIXoqMPPCGG8qKA/8Y79q/jYLQwwBKepzCeTMaDB0jnL5wjpqhH9vnA9PjK93Gh3r+6 oLGoXXVElJVzhnXNNPwAb0UldabuNvXSrVkjpkvEV41HdzLA4FfAdqIIwQkVdzBXXkEz ikZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686840309; x=1689432309; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Od+eFJu5Un7KQxaLhPRr3IFDtHMK7wuQZd5iaWBOH10=; b=LnU5xdY17PIB6h+KLUW1GM80W1PH/mYct/sdGrpMLF5ZV20nWsDLmtKyNApXF2pqIK JnPGqVDHPQ53lHUptDmxFyGYLpjRLXxQPKolDtt4HMYqQC8aunsvzvyMH4cHOQC+fC9T u3UbaDC59EEBbTf6cBeBmpfRIVaCMOzqLGgUcy1GrIY4DgDvVFm4hlLN/DrpFAE9BP53 ryHwVhniehZoJsUoSKikwFLTFMXt6bDk3qNBzxbwBF4+xkxBTIAZp/vXZY0K60IocVxM FFdrwQWpP3+h6cyo/c650VixTFCUxqKd0iYGXpfe0wllKJ88P2c0tlRjIOapnAQDi1fT akRA== X-Gm-Message-State: AC+VfDwHrW/YflPkGjtNHrUhKIMEsoUjUgQu0h32ZNneLWX/oPhQBGNs 6/Qm2mAKvEZHsUcdfo/L0KXw751nvUG2HzhwiQ== X-Google-Smtp-Source: ACHHUZ42J/0Jf+gDaLLKGQHbIyIlptOWp+NsU/XsK+8bJkVec+s53U9ItXSWHV2vOSUE3URFiJCKgQ== X-Received: by 2002:a19:6d1c:0:b0:4ef:fb4b:eb2d with SMTP id i28-20020a196d1c000000b004effb4beb2dmr9341785lfc.33.1686840309008; Thu, 15 Jun 2023 07:45:09 -0700 (PDT) Received: from localhost.localdomain (mail.pulsar-telecom.ru. [94.181.180.60]) by smtp.gmail.com with ESMTPSA id h7-20020ac25967000000b004f13f4ec267sm244451lfp.186.2023.06.15.07.45.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 07:45:08 -0700 (PDT) From: Aleksandr Shubin To: linux-kernel@vger.kernel.org Cc: Aleksandr Shubin , Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Cristian Ciocaltea , Heiko Stuebner , Maxime Ripard , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org Subject: [PATCH v1 2/3] pwm: Add Allwinner's D1/T113-S3/R329 SoCs PWM support Date: Thu, 15 Jun 2023 17:43:57 +0300 Message-Id: <20230615144423.828698-3-privatesub2@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230615144423.828698-1-privatesub2@gmail.com> References: <20230615144423.828698-1-privatesub2@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Allwinner's D1, T113-S3 and R329 SoCs have a quite different PWM controllers with ones supported by pwm-sun4i driver. This patch adds a PWM controller driver for Allwinner's D1, T113-S3 and R329 SoCs. The main difference between these SoCs is the number of channels defined by the DT property. Signed-off-by: Aleksandr Shubin --- drivers/pwm/Kconfig | 12 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-sun20i.c | 364 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 377 insertions(+) create mode 100644 drivers/pwm/pwm-sun20i.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 8df861b1f4a3..b435e50fbd3e 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -594,6 +594,18 @@ config PWM_SUN4I To compile this driver as a module, choose M here: the module will be called pwm-sun4i. =20 +config PWM_SUN20I + tristate "Allwinner D1/T113s/R329 PWM support" + depends on ARCH_SUNXI || COMPILE_TEST + depends on COMMON_CLK + help + Generic PWM framework driver for Allwinner D1/T113s/R329 SoCs. + The main difference between these SoCs is the number of + channels defined by the DT property. + + To compile this driver as a module, choose M here: the module + will be called pwm-sun20i. + config PWM_SUNPLUS tristate "Sunplus PWM support" depends on ARCH_SUNPLUS || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 19899b912e00..cea872e22c78 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -55,6 +55,7 @@ obj-$(CONFIG_PWM_STM32) +=3D pwm-stm32.o obj-$(CONFIG_PWM_STM32_LP) +=3D pwm-stm32-lp.o obj-$(CONFIG_PWM_STMPE) +=3D pwm-stmpe.o obj-$(CONFIG_PWM_SUN4I) +=3D pwm-sun4i.o +obj-$(CONFIG_PWM_SUN20I) +=3D pwm-sun20i.o obj-$(CONFIG_PWM_SUNPLUS) +=3D pwm-sunplus.o obj-$(CONFIG_PWM_TEGRA) +=3D pwm-tegra.o obj-$(CONFIG_PWM_TIECAP) +=3D pwm-tiecap.o diff --git a/drivers/pwm/pwm-sun20i.c b/drivers/pwm/pwm-sun20i.c new file mode 100644 index 000000000000..100b0f3bcec0 --- /dev/null +++ b/drivers/pwm/pwm-sun20i.c @@ -0,0 +1,364 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PWM Controller Driver for sunxi platforms (D1, T113-S3 and R329) + * + * Copyright (c) 2023 Aleksandr Shubin + */ + +#include +#include +#include +#include +#include +#include +#include + +#define PWM_CLK_CFG_REG(chan) (0x20 + (((chan) >> 1) * 0x4)) +#define PWM_CLK_SRC 7 +#define PWM_CLK_SRC_MASK GENMASK(8, PWM_CLK_SRC) +#define PWM_CLK_DIV_M 0 +#define PWM_CLK_DIV_M_MASK GENMASK(3, PWM_CLK_DIV_M) + +#define PWM_CLK_GATE_REG 0x40 +#define PWM_CLK_GATING(chan) BIT(chan) + +#define PWM_ENABLE_REG 0x80 +#define PWM_EN(chan) BIT(chan) + +#define PWM_CTL_REG(chan) (0x100 + (chan) * 0x20) +#define PWM_ACT_STA BIT(8) +#define PWM_PRESCAL_K 0 +#define PWM_PRESCAL_K_MASK GENMASK(7, PWM_PRESCAL_K) + +#define PWM_PERIOD_REG(chan) (0x104 + (chan) * 0x20) +#define PWM_ENTIRE_CYCLE 16 +#define PWM_ENTIRE_CYCLE_MASK GENMASK(31, PWM_ENTIRE_CYCLE) +#define PWM_ACT_CYCLE 0 +#define PWM_ACT_CYCLE_MASK GENMASK(15, PWM_ACT_CYCLE) + +#define SET_VALUE(reg_val, val, name) \ + (reg_val =3D (((reg_val) & ~name##_MASK) | ((val) << (name)))) +#define GET_VALUE(reg_val, name) \ + (((reg_val) & ~name##_MASK) >> (name)) + +struct sun20i_pwm_chip { + struct pwm_chip chip; + struct clk *clk_bus, *clk_hosc; + struct reset_control *rst; + void __iomem *base; + /* Mutex to protect pwm apply state */ + struct mutex mutex; +}; + +static inline struct sun20i_pwm_chip *to_sun20i_pwm_chip(struct pwm_chip *= chip) +{ + return container_of(chip, struct sun20i_pwm_chip, chip); +} + +static inline u32 sun20i_pwm_readl(struct sun20i_pwm_chip *chip, + unsigned long offset) +{ + return readl(chip->base + offset); +} + +static inline void sun20i_pwm_writel(struct sun20i_pwm_chip *chip, + u32 val, unsigned long offset) +{ + writel(val, chip->base + offset); +} + +static int sun20i_pwm_get_state(struct pwm_chip *chip, + struct pwm_device *pwm, + struct pwm_state *state) +{ + struct sun20i_pwm_chip *sun20i_chip =3D to_sun20i_pwm_chip(chip); + u64 clk_rate, tmp; + u32 val; + u16 clk_div, act_cycle; + u8 prescal, div_id; + u8 chn =3D pwm->hwpwm; + + mutex_lock(&sun20i_chip->mutex); + + val =3D sun20i_pwm_readl(sun20i_chip, PWM_CLK_CFG_REG(pwm->hwpwm)); + div_id =3D GET_VALUE(val, PWM_CLK_DIV_M); + if (GET_VALUE(val, PWM_CLK_SRC) =3D=3D 0) + clk_rate =3D clk_get_rate(sun20i_chip->clk_hosc); + else + clk_rate =3D clk_get_rate(sun20i_chip->clk_bus); + + val =3D sun20i_pwm_readl(sun20i_chip, PWM_CTL_REG(pwm->hwpwm)); + if (PWM_ACT_STA & val) + state->polarity =3D PWM_POLARITY_NORMAL; + else + state->polarity =3D PWM_POLARITY_INVERSED; + + prescal =3D PWM_PRESCAL_K & val; + + val =3D sun20i_pwm_readl(sun20i_chip, PWM_ENABLE_REG); + if (PWM_EN(chn) & val) + state->enabled =3D true; + else + state->enabled =3D false; + + val =3D sun20i_pwm_readl(sun20i_chip, PWM_PERIOD_REG(pwm->hwpwm)); + act_cycle =3D GET_VALUE(val, PWM_ACT_CYCLE); + clk_div =3D GET_VALUE(val, PWM_ENTIRE_CYCLE); + + tmp =3D act_cycle * prescal * (1U << div_id) * NSEC_PER_SEC; + state->duty_cycle =3D DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); + tmp =3D clk_div * prescal * (1U << div_id) * NSEC_PER_SEC; + state->period =3D DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); + + mutex_unlock(&sun20i_chip->mutex); + + return 0; +} + +static int sun20i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct pwm_state curstate; + int ret =3D 0; + u32 clk_gate, clk_cfg, pwm_en, ctl, period; + u64 bus_rate, hosc_rate, clk_div, val, clk_rate; + u16 prescaler, div_m; + bool use_bus_clk; + struct sun20i_pwm_chip *sun20i_chip =3D to_sun20i_pwm_chip(chip); + + mutex_lock(&sun20i_chip->mutex); + pwm_get_state(pwm, &curstate); + + pwm_en =3D sun20i_pwm_readl(sun20i_chip, PWM_ENABLE_REG); + if (state->polarity !=3D curstate.polarity || + state->duty_cycle !=3D curstate.duty_cycle || + state->period !=3D curstate.period) { + ctl =3D sun20i_pwm_readl(sun20i_chip, PWM_CTL_REG(pwm->hwpwm)); + clk_cfg =3D sun20i_pwm_readl(sun20i_chip, PWM_CLK_CFG_REG(pwm->hwpwm)); + hosc_rate =3D clk_get_rate(sun20i_chip->clk_hosc); + bus_rate =3D clk_get_rate(sun20i_chip->clk_bus); + + if (pwm_en & PWM_EN(pwm->hwpwm ^ 1)) { + /* check period only */ + if (GET_VALUE(clk_cfg, PWM_CLK_SRC) =3D=3D 0) + clk_rate =3D hosc_rate; + else + clk_rate =3D bus_rate; + + val =3D state->period * clk_rate; + do_div(val, NSEC_PER_SEC); + + div_m =3D GET_VALUE(clk_cfg, PWM_CLK_DIV_M); + + /* calculate and set prescaler, PWM entire cycle */ + clk_div =3D val; + for (prescaler =3D 0; clk_div > 65535; prescaler++) { + if (prescaler >=3D 256) { + dev_err(sun20i_chip->chip.dev, "Period is too long\n"); + ret =3D -EINVAL; + goto unlock_mutex; + } + + clk_div =3D val; + do_div(clk_div, 1U << div_m); + do_div(clk_div, prescaler + 1); + } + } else { + /* check period and select clock source */ + use_bus_clk =3D false; + val =3D state->period * hosc_rate; + do_div(val, NSEC_PER_SEC); + if (val <=3D 1) { + use_bus_clk =3D true; + val =3D state->period * bus_rate; + do_div(val, NSEC_PER_SEC); + if (val <=3D 1) { + dev_err(sun20i_chip->chip.dev, "Period is too small\n"); + ret =3D -EINVAL; + goto unlock_mutex; + } + } + + if (use_bus_clk) + SET_VALUE(clk_cfg, 1, PWM_CLK_SRC); + else + SET_VALUE(clk_cfg, 0, PWM_CLK_SRC); + + /* calculate and set prescaler, M factor, PWM entire cycle */ + clk_div =3D val; + for (prescaler =3D div_m =3D 0; clk_div > 65535; prescaler++) { + if (prescaler >=3D 256) { + prescaler =3D 0; + div_m++; + if (div_m >=3D 9) { + dev_err(sun20i_chip->chip.dev, "Period is too long\n"); + ret =3D -EINVAL; + goto unlock_mutex; + } + } + + clk_div =3D val; + do_div(clk_div, 1U << div_m); + do_div(clk_div, prescaler + 1); + } + + /* set up the M factor */ + SET_VALUE(clk_cfg, div_m, PWM_CLK_DIV_M); + + sun20i_pwm_writel(sun20i_chip, clk_cfg, PWM_CLK_CFG_REG(pwm->hwpwm)); + } + + period =3D sun20i_pwm_readl(sun20i_chip, PWM_PERIOD_REG(pwm->hwpwm)); + + SET_VALUE(period, clk_div, PWM_ENTIRE_CYCLE); + SET_VALUE(ctl, prescaler, PWM_PRESCAL_K); + + /* set duty cycle */ + val =3D state->period; + do_div(val, clk_div); + clk_div =3D state->duty_cycle; + do_div(clk_div, val); + if (clk_div > 65535) + clk_div =3D 65535; + + SET_VALUE(period, clk_div, PWM_ACT_CYCLE); + sun20i_pwm_writel(sun20i_chip, period, PWM_PERIOD_REG(pwm->hwpwm)); + + if (state->polarity =3D=3D PWM_POLARITY_NORMAL) + ctl |=3D PWM_ACT_STA; + else + ctl &=3D ~PWM_ACT_STA; + + sun20i_pwm_writel(sun20i_chip, ctl, PWM_CTL_REG(pwm->hwpwm)); + } + + if (state->enabled !=3D curstate.enabled) { + clk_gate =3D sun20i_pwm_readl(sun20i_chip, PWM_CLK_GATE_REG); + + if (state->enabled) { + clk_gate |=3D PWM_CLK_GATING(pwm->hwpwm); + pwm_en |=3D PWM_EN(pwm->hwpwm); + } else { + clk_gate &=3D ~PWM_CLK_GATING(pwm->hwpwm); + pwm_en &=3D ~PWM_EN(pwm->hwpwm); + } + sun20i_pwm_writel(sun20i_chip, pwm_en, PWM_ENABLE_REG); + sun20i_pwm_writel(sun20i_chip, clk_gate, PWM_CLK_GATE_REG); + } + +unlock_mutex: + mutex_unlock(&sun20i_chip->mutex); + + return ret; +} + +static const struct pwm_ops sun20i_pwm_ops =3D { + .get_state =3D sun20i_pwm_get_state, + .apply =3D sun20i_pwm_apply, + .owner =3D THIS_MODULE, +}; + +static const struct of_device_id sun20i_pwm_dt_ids[] =3D { + { .compatible =3D "allwinner,sun20i-d1-pwm" }, + { }, +}; +MODULE_DEVICE_TABLE(of, sun20i_pwm_dt_ids); + +static int sun20i_pwm_probe(struct platform_device *pdev) +{ + struct sun20i_pwm_chip *sun20i_chip; + int ret; + + sun20i_chip =3D devm_kzalloc(&pdev->dev, sizeof(*sun20i_chip), GFP_KERNEL= ); + if (!sun20i_chip) + return -ENOMEM; + + sun20i_chip->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(sun20i_chip->base)) + return PTR_ERR(sun20i_chip->base); + + sun20i_chip->clk_bus =3D devm_clk_get(&pdev->dev, "bus"); + if (IS_ERR(sun20i_chip->clk_bus)) { + dev_err(&pdev->dev, "Failed to get bus clock\n"); + return PTR_ERR(sun20i_chip->clk_bus); + } + + sun20i_chip->clk_hosc =3D devm_clk_get(&pdev->dev, "hosc"); + if (IS_ERR(sun20i_chip->clk_hosc)) { + dev_err(&pdev->dev, "Failed to get hosc clock\n"); + return PTR_ERR(sun20i_chip->clk_hosc); + } + + sun20i_chip->rst =3D devm_reset_control_get(&pdev->dev, NULL); + if (IS_ERR(sun20i_chip->rst)) { + dev_err(&pdev->dev, "Failed to get bus reset\n"); + return PTR_ERR(sun20i_chip->rst); + } + + /* Deassert reset */ + ret =3D reset_control_deassert(sun20i_chip->rst); + if (ret) { + dev_err(&pdev->dev, "Failed to deassert reset\n"); + return ret; + } + + ret =3D clk_prepare_enable(sun20i_chip->clk_bus); + if (ret) { + dev_err(&pdev->dev, "Failed to ungate bus clock\n"); + goto err_bus; + } + + ret =3D of_property_read_u32(pdev->dev.of_node, + "allwinner,pwm-channels", + &sun20i_chip->chip.npwm); + if (ret) { + dev_err(&pdev->dev, "Can't get pwm-channels\n"); + goto err_pwm_add; + } + + sun20i_chip->chip.dev =3D &pdev->dev; + sun20i_chip->chip.ops =3D &sun20i_pwm_ops; + + mutex_init(&sun20i_chip->mutex); + + ret =3D pwmchip_add(&sun20i_chip->chip); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to add PWM chip: %d\n", ret); + goto err_pwm_add; + } + + platform_set_drvdata(pdev, sun20i_chip); + + return 0; + +err_pwm_add: + clk_disable_unprepare(sun20i_chip->clk_bus); +err_bus: + reset_control_assert(sun20i_chip->rst); + return ret; +} + +static void sun20i_pwm_remove(struct platform_device *pdev) +{ + struct sun20i_pwm_chip *sun20i_chip =3D platform_get_drvdata(pdev); + int ret; + + pwmchip_remove(&sun20i_chip->chip); + + clk_disable_unprepare(sun20i_chip->clk_bus); + reset_control_assert(sun20i_chip->rst); +} + +static struct platform_driver sun20i_pwm_driver =3D { + .driver =3D { + .name =3D "sun20i-pwm", + .of_match_table =3D sun20i_pwm_dt_ids, + }, + .probe =3D sun20i_pwm_probe, + .remove_new =3D sun20i_pwm_remove, +}; +module_platform_driver(sun20i_pwm_driver); + +MODULE_AUTHOR("Aleksandr Shubin "); +MODULE_DESCRIPTION("Allwinner sun20i PWM driver"); +MODULE_LICENSE("GPL"); --=20 2.25.1 From nobody Mon Feb 9 00:25:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 708E6EB64DB for ; Thu, 15 Jun 2023 14:45:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344237AbjFOOpm (ORCPT ); Thu, 15 Jun 2023 10:45:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241542AbjFOOpj (ORCPT ); Thu, 15 Jun 2023 10:45:39 -0400 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E781D294E; 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[94.181.180.60]) by smtp.gmail.com with ESMTPSA id h7-20020ac25967000000b004f13f4ec267sm244451lfp.186.2023.06.15.07.45.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 07:45:32 -0700 (PDT) From: Aleksandr Shubin To: linux-kernel@vger.kernel.org Cc: Aleksandr Shubin , Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Cristian Ciocaltea , Andre Przywara , Maxime Ripard , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org Subject: [PATCH v1 3/3] riscv: dts: allwinner: d1: Add pwm node Date: Thu, 15 Jun 2023 17:43:58 +0300 Message-Id: <20230615144423.828698-4-privatesub2@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230615144423.828698-1-privatesub2@gmail.com> References: <20230615144423.828698-1-privatesub2@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" D1 and T113s contain a pwm controller with 8 channels. This controller is supported by the sun20i-pwm driver. Add a device tree node for it. Signed-off-by: Aleksandr Shubin --- arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv= /boot/dts/allwinner/sunxi-d1s-t113.dtsi index 922e8e0e2c09..50f0f761527b 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -127,6 +127,18 @@ uart3_pb_pins: uart3-pb-pins { }; }; =20 + pwm: pwm@2000c00 { + compatible =3D "allwinner,sun20i-d1-pwm"; + reg =3D <0x02000c00 0x400>; + clocks =3D <&dcxo>, + <&ccu CLK_BUS_PWM>; + clock-names =3D "hosc", "bus"; + resets =3D <&ccu RST_BUS_PWM>; + allwinner,pwm-channels =3D <8>; + status =3D "disabled"; + #pwm-cells =3D <0x3>; + }; + ccu: clock-controller@2001000 { compatible =3D "allwinner,sun20i-d1-ccu"; reg =3D <0x2001000 0x1000>; --=20 2.25.1