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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by DM6NAM11FT054.mail.protection.outlook.com (10.13.173.95) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6500.27 via Frontend Transport; Thu, 15 Jun 2023 11:17:00 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Thu, 15 Jun 2023 06:16:59 -0500 Received: from xhdakumarma40u.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.23 via Frontend Transport; Thu, 15 Jun 2023 06:16:55 -0500 From: Amit Kumar Mahapatra To: , , , , , , , CC: , , , , , , Amit Kumar Mahapatra Subject: [PATCH 1/2] dt-bindings: mtd: jedec, spi-nor: Add DT property to avoid setting SRWD bit in status register Date: Thu, 15 Jun 2023 16:46:48 +0530 Message-ID: <20230615111649.36344-2-amit.kumar-mahapatra@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230615111649.36344-1-amit.kumar-mahapatra@amd.com> References: <20230615111649.36344-1-amit.kumar-mahapatra@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT054:EE_|MN2PR12MB4568:EE_ X-MS-Office365-Filtering-Correlation-Id: d3423403-08f0-452f-3db6-08db6d920a26 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jun 2023 11:17:00.5207 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d3423403-08f0-452f-3db6-08db6d920a26 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT054.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4568 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If the WP signal of the flash device is not connected and the software sets the status register write disable (SRWD) bit in the status register then thestatus register permanently becomes read-only. To avoid this added a new boolean DT property "broken-wp". If WP signal is not connected, then this property should be set in the DT to avoid setting the SRWD during status register write operation. Signed-off-by: Amit Kumar Mahapatra Reviewed-by: Conor Dooley --- .../devicetree/bindings/mtd/jedec,spi-nor.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Doc= umentation/devicetree/bindings/mtd/jedec,spi-nor.yaml index 89959e5c47ba..a509d34f14b2 100644 --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml @@ -70,6 +70,19 @@ properties: be used on such systems, to denote the absence of a reliable reset mechanism. =20 + broken-wp: + type: boolean + description: + The SRWD bit in status register, combined with the WP signal provides + hardware data protection for the device. When the SRWD bit is set to= 1, + and the WP signal is driven LOW, the status register nonvolatile bits + become read-only and the WRITE STATUS REGISTER operation will not ex= ecute. + The only way to exit this hardware-protected mode is to drive WP HIG= H. But + if the WP signal of the flash device is not connected then status re= gister + permanently becomes read-only as the SRWD bit cannot be reset. This = boolean + flag can be used on such systems in which WP signal is not connected= , to + avoid setting the SRWD bit while writing the status register. + reset-gpios: description: A GPIO line connected to the RESET (active low) signal of the device. --=20 2.17.1 From nobody Sun Feb 8 01:52:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 970F9EB64D9 for ; Thu, 15 Jun 2023 11:17:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241766AbjFOLRR (ORCPT ); Thu, 15 Jun 2023 07:17:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41568 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343654AbjFOLRK (ORCPT ); Thu, 15 Jun 2023 07:17:10 -0400 Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam02on2054.outbound.protection.outlook.com [40.107.212.54]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EFF982947; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jun 2023 11:17:05.0784 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1ae19120-460b-40a2-1693-08db6d920ce0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT103.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8802 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Setting the status register write disable (SRWD) bit in the status register (SR) with WP signal of the flash not connected will configure the SR permanently as read-only. If WP signal is not connected, avoid setting SRWD bit while writing the SR during flash protection. Signed-off-by: Amit Kumar Mahapatra --- drivers/mtd/spi-nor/core.c | 3 +++ drivers/mtd/spi-nor/core.h | 1 + drivers/mtd/spi-nor/swp.c | 5 +++-- 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 0bb0ad14a2fc..81b57c51f41c 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2864,6 +2864,9 @@ static void spi_nor_init_flags(struct spi_nor *nor) if (flags & NO_CHIP_ERASE) nor->flags |=3D SNOR_F_NO_OP_CHIP_ERASE; =20 + if (of_property_read_bool(np, "broken-wp")) + nor->flags |=3D SNOR_F_BROKEN_WP; + if (flags & SPI_NOR_RWW && nor->info->n_banks > 1 && !nor->controller_ops) nor->flags |=3D SNOR_F_RWW; diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 4fb5ff09c63a..6ac932eba913 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -132,6 +132,7 @@ enum spi_nor_option_flags { SNOR_F_SWP_IS_VOLATILE =3D BIT(13), SNOR_F_RWW =3D BIT(14), SNOR_F_ECC =3D BIT(15), + SNOR_F_BROKEN_WP =3D BIT(16), }; =20 struct spi_nor_read_command { diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index 0ba716e84377..074f3bce2034 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -214,8 +214,9 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t = ofs, uint64_t len) =20 status_new =3D (status_old & ~mask & ~tb_mask) | val; =20 - /* Disallow further writes if WP pin is asserted */ - status_new |=3D SR_SRWD; + /* Disallow further writes if WP pin is connected */ + if (!(nor->flags & SNOR_F_BROKEN_WP)) + status_new |=3D SR_SRWD; =20 if (!use_top) status_new |=3D tb_mask; --=20 2.17.1