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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT088.mail.protection.outlook.com (10.13.172.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6500.25 via Frontend Transport; Thu, 15 Jun 2023 05:18:09 +0000 Received: from BLR-5CG113396H.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Thu, 15 Jun 2023 00:17:19 -0500 From: Ravi Bangoria To: CC: , , , , , , , , , , , , , , , , , Subject: [PATCH v2 1/3] perf pmus: Describe semantics of 'core_pmus' and 'other_pmus' Date: Thu, 15 Jun 2023 10:46:58 +0530 Message-ID: <20230615051700.1833-2-ravi.bangoria@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230615051700.1833-1-ravi.bangoria@amd.com> References: <20230615051700.1833-1-ravi.bangoria@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT088:EE_|IA1PR12MB6436:EE_ X-MS-Office365-Filtering-Correlation-Id: fa87494f-759b-4bf6-567c-08db6d5fe8a7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jun 2023 05:18:09.4877 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fa87494f-759b-4bf6-567c-08db6d5fe8a7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT088.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6436 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Notion of 'core_pmus' and 'other_pmus' are independent of hw core and uncore pmus. For example, AMD IBS PMUs are present in each SMT-thread but they belongs to 'other_pmus'. Add a comment describing what these list contains and how they are treated. Signed-off-by: Ravi Bangoria --- tools/perf/util/pmus.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/tools/perf/util/pmus.c b/tools/perf/util/pmus.c index e1d0a93147e5..8c50ab8894b7 100644 --- a/tools/perf/util/pmus.c +++ b/tools/perf/util/pmus.c @@ -12,6 +12,21 @@ #include "pmu.h" #include "print-events.h" =20 +/* + * core_pmus: A PMU belongs to core_pmus if it's name is "cpu" or it's sy= sfs + * directory contains "cpus" file. All PMUs belonging to core_= pmus + * must have pmu->is_core=3D1. If there are more than one PMU = in + * this list, perf interprets it as a heterogeneous platform. + * (FWIW, certain ARM platforms having heterogeneous cores uses + * homogeneous PMU, and thus they are treated as homogeneous + * platform by perf because core_pmus will have only one entry) + * other_pmus: All other PMUs which are not part of core_pmus list. It doe= sn't + * matter whether PMU is present per SMT-thread or outside of = the + * core in the hw. For e.g., an instance of AMD ibs_fetch// and + * ibs_op// PMUs is present in each hw SMT thread, however they + * are captured under other_pmus. PMUs belonging to other_pmus + * must have pmu->is_core=3D0 but pmu->is_uncore could be 0 or= 1. + */ static LIST_HEAD(core_pmus); static LIST_HEAD(other_pmus); static bool read_sysfs_core_pmus; --=20 2.40.1