From nobody Mon Feb 9 00:55:11 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B590AEB64D9 for ; Wed, 14 Jun 2023 17:15:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235239AbjFNRPQ (ORCPT ); Wed, 14 Jun 2023 13:15:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234582AbjFNRPF (ORCPT ); Wed, 14 Jun 2023 13:15:05 -0400 Received: from imap4.hz.codethink.co.uk (imap4.hz.codethink.co.uk [188.40.203.114]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 96A381BF0; Wed, 14 Jun 2023 10:15:03 -0700 (PDT) Received: from [167.98.27.226] (helo=rainbowdash) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1q9U5D-00Exj2-C7; Wed, 14 Jun 2023 18:14:59 +0100 Received: from ben by rainbowdash with local (Exim 4.96) (envelope-from ) id 1q9U5C-000I0t-0z; Wed, 14 Jun 2023 18:14:58 +0100 From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ben.dooks@codethink.co.uk, u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v8 3/5] pwm: dwc: add PWM bit unset in get_state call Date: Wed, 14 Jun 2023 18:14:55 +0100 Message-Id: <20230614171457.69191-4-ben.dooks@sifive.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230614171457.69191-1-ben.dooks@sifive.com> References: <20230614171457.69191-1-ben.dooks@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If we are not in PWM mode, then the output is technically a 50% output based on a single timer instead of the high-low based on the two counters. Add a check for the PWM mode in dwc_pwm_get_state() and if DWC_TIM_CTRL_PWM is not set, then return a 50% cycle. This may only be an issue on initialisation, as the rest of the code currently assumes we're always going to have the extended PWM mode using two counters. Signed-off-by: Ben Dooks --- v8: - fixed rename issues v4: - fixed review comment on mulit-line calculations --- drivers/pwm/pwm-dwc-core.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-dwc-core.c b/drivers/pwm/pwm-dwc-core.c index 4b4b7b9e1d82..38cd2163fe01 100644 --- a/drivers/pwm/pwm-dwc-core.c +++ b/drivers/pwm/pwm-dwc-core.c @@ -122,24 +122,31 @@ static int dwc_pwm_get_state(struct pwm_chip *chip, s= truct pwm_device *pwm, { struct dwc_pwm *dwc =3D to_dwc_pwm(chip); u64 duty, period; + u32 ctrl, ld, ld2; =20 pm_runtime_get_sync(chip->dev); =20 - state->enabled =3D !!(dwc_pwm_readl(dwc, - DWC_TIM_CTRL(pwm->hwpwm)) & DWC_TIM_CTRL_EN); + ctrl =3D dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm->hwpwm)); + ld =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); + ld2 =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); =20 - duty =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); - duty +=3D 1; - duty *=3D dwc->clk_ns; - state->duty_cycle =3D duty; + state->enabled =3D !!(ctrl & DWC_TIM_CTRL_EN); =20 - period =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); - period +=3D 1; - period *=3D dwc->clk_ns; - period +=3D duty; - state->period =3D period; + /* If we're not in PWM, technically the output is a 50-50 + * based on the timer load-count only. + */ + if (ctrl & DWC_TIM_CTRL_PWM) { + duty =3D (ld + 1) * dwc->clk_ns; + period =3D (ld2 + 1) * dwc->clk_ns; + period +=3D duty; + } else { + duty =3D (ld + 1) * dwc->clk_ns; + period =3D duty * 2; + } =20 state->polarity =3D PWM_POLARITY_INVERSED; + state->period =3D period; + state->duty_cycle =3D duty; =20 pm_runtime_put_sync(chip->dev); =20 --=20 2.39.2