From nobody Sun Feb 8 12:36:39 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA100EB64D9 for ; Wed, 14 Jun 2023 15:43:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244550AbjFNPnl (ORCPT ); Wed, 14 Jun 2023 11:43:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244362AbjFNPnh (ORCPT ); Wed, 14 Jun 2023 11:43:37 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD5D42101 for ; Wed, 14 Jun 2023 08:43:35 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-561ceb5b584so11999697b3.3 for ; Wed, 14 Jun 2023 08:43:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1686757415; x=1689349415; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=xwDD9pVjLa+TJXAJEbbYyI+224KEPbc+a+2w73kHUiI=; b=XcbpIeR43JDZfn4lLCsVf0JdsLi6nRjRM50ZNMNNgoiXVaiw+/ZGHnE5KTJjMCs9aO vnK/+7uf6oxkg7kl2xEDoB5F4B2QtCLAzLVEn4t/E3os9JAaCcYrN3AO74r8GCTCI1ai CNeyG9s42Dtj6TN/jMZhQ7UQlbA6doeYtm3JtoHKSi/95yADdM887JCovkOxifmKCPA2 z9m+8SiMXacLLqG5IobUr532pG3VZDDME93RDKR+p2TzHi9YlbOhVRmhqLQz3NpdaYUk zE23NqAZ3c+vCO3XhN19QdpZYVPa2PS0tkE5LTgBL+aO1vkz+gKWJS2k5UoUETqYjKW/ Dl/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686757415; x=1689349415; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=xwDD9pVjLa+TJXAJEbbYyI+224KEPbc+a+2w73kHUiI=; b=Hh6tVOmnI3vqq6paByUgg6VUJ0DwT1wK7dlIk6rpSeuqzOgkotpqQmoKO5ztiVpMjG lEyOgr9HmdY/3mzF6ssi8PtMoFbwtfCAEYV0bjaejRfFCj7kmehrqgcIFpg+asAJJ2GG Xal5dLXhd+ILQgzx3Dtl42Msml3sh+jY4Yc5JwvCaDe+R23Xtmco6fZCvEsoTUB6MEWP eNQFOVQ3jW35QMtwLyvva5i71CCvkdR+YH0aIBnaFgmb9sh3TdosIAbR/QLT84oR3ru3 xsYblU4fRYiKI1KDTi8JHlTHJX5uenQuISJsKvgRYqr7wSWNPZsSmuqrpdFyKQRCwoC4 Rhww== X-Gm-Message-State: AC+VfDzMO2pMrxtfh5xBjvPYf79JKVb40hdF98bSSyBASugZly0evlAC hDedJTz/GzIxsp+FX/VhSvpObS0ZiXZr X-Google-Smtp-Source: ACHHUZ6p8for2Qz1f423vXRFsQW/AZzRMixrBtrLwCsmjpkKSoWyMi0rfNyVEkzE8Fw0M2x5Q3BMJBOn9mnK X-Received: from mshavit.ntc.corp.google.com ([2401:fa00:95:20c:c6e6:49bf:5c44:5965]) (user=mshavit job=sendgmr) by 2002:a81:ac49:0:b0:561:c9c0:98d9 with SMTP id z9-20020a81ac49000000b00561c9c098d9mr1044537ywj.4.1686757414962; Wed, 14 Jun 2023 08:43:34 -0700 (PDT) Date: Wed, 14 Jun 2023 23:41:53 +0800 In-Reply-To: <20230614154304.2860121-1-mshavit@google.com> Mime-Version: 1.0 References: <20230614154304.2860121-1-mshavit@google.com> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog Message-ID: <20230614154304.2860121-2-mshavit@google.com> Subject: [PATCH v3 01/13] iommu/arm-smmu-v3: Move ctx_desc out of s1_cfg From: Michael Shavit To: Will Deacon , Robin Murphy , Joerg Roedel Cc: Michael Shavit , jean-philippe@linaro.org, nicolinc@nvidia.com, jgg@nvidia.com, baolu.lu@linux.intel.com, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" s1_cfg describes the CD table that is inserted into an SMMU's STEs. It's weird for s1_cfg to also own ctx_desc which describes a CD that is inserted into that table. It is more appropriate for arm_smmu_domain to own ctx_desc. Signed-off-by: Michael Shavit --- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 2 +- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 23 +++++++-------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 28 ++++++++++--------- 3 files changed, 28 insertions(+), 25 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index a5a63b1c947eb..968559d625c40 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -62,7 +62,7 @@ arm_smmu_share_asid(struct mm_struct *mm, u16 asid) return cd; } =20 - smmu_domain =3D container_of(cd, struct arm_smmu_domain, s1_cfg.cd); + smmu_domain =3D container_of(cd, struct arm_smmu_domain, cd); smmu =3D smmu_domain->smmu; =20 ret =3D xa_alloc(&arm_smmu_asid_xa, &new_asid, cd, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 3fd83fb757227..beff04b897718 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1863,7 +1863,7 @@ static void arm_smmu_tlb_inv_context(void *cookie) * careful, 007. */ if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { - arm_smmu_tlb_inv_asid(smmu, smmu_domain->s1_cfg.cd.asid); + arm_smmu_tlb_inv_asid(smmu, smmu_domain->cd.asid); } else { cmd.opcode =3D CMDQ_OP_TLBI_S12_VMALL; cmd.tlbi.vmid =3D smmu_domain->s2_cfg.vmid; @@ -1946,7 +1946,7 @@ static void arm_smmu_tlb_inv_range_domain(unsigned lo= ng iova, size_t size, if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { cmd.opcode =3D smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? CMDQ_OP_TLBI_EL2_VA : CMDQ_OP_TLBI_NH_VA; - cmd.tlbi.asid =3D smmu_domain->s1_cfg.cd.asid; + cmd.tlbi.asid =3D smmu_domain->cd.asid; } else { cmd.opcode =3D CMDQ_OP_TLBI_S2_IPA; cmd.tlbi.vmid =3D smmu_domain->s2_cfg.vmid; @@ -2077,7 +2077,7 @@ static void arm_smmu_domain_free(struct iommu_domain = *domain) mutex_lock(&arm_smmu_asid_lock); if (cfg->cdcfg.cdtab) arm_smmu_free_cd_tables(smmu_domain); - arm_smmu_free_asid(&cfg->cd); + arm_smmu_free_asid(&smmu_domain->cd); mutex_unlock(&arm_smmu_asid_lock); } else { struct arm_smmu_s2_cfg *cfg =3D &smmu_domain->s2_cfg; @@ -2096,13 +2096,14 @@ static int arm_smmu_domain_finalise_s1(struct arm_s= mmu_domain *smmu_domain, u32 asid; struct arm_smmu_device *smmu =3D smmu_domain->smmu; struct arm_smmu_s1_cfg *cfg =3D &smmu_domain->s1_cfg; + struct arm_smmu_ctx_desc *cd =3D &smmu_domain->cd; typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr =3D &pgtbl_cfg->arm_lpae_s1_c= fg.tcr; =20 - refcount_set(&cfg->cd.refs, 1); + refcount_set(&cd->refs, 1); =20 /* Prevent SVA from modifying the ASID until it is written to the CD */ mutex_lock(&arm_smmu_asid_lock); - ret =3D xa_alloc(&arm_smmu_asid_xa, &asid, &cfg->cd, + ret =3D xa_alloc(&arm_smmu_asid_xa, &asid, cd, XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); if (ret) goto out_unlock; @@ -2115,23 +2116,23 @@ static int arm_smmu_domain_finalise_s1(struct arm_s= mmu_domain *smmu_domain, if (ret) goto out_free_asid; =20 - cfg->cd.asid =3D (u16)asid; - cfg->cd.ttbr =3D pgtbl_cfg->arm_lpae_s1_cfg.ttbr; - cfg->cd.tcr =3D FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, tcr->tsz) | + cd->asid =3D (u16)asid; + cd->ttbr =3D pgtbl_cfg->arm_lpae_s1_cfg.ttbr; + cd->tcr =3D FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, tcr->tsz) | FIELD_PREP(CTXDESC_CD_0_TCR_TG0, tcr->tg) | FIELD_PREP(CTXDESC_CD_0_TCR_IRGN0, tcr->irgn) | FIELD_PREP(CTXDESC_CD_0_TCR_ORGN0, tcr->orgn) | FIELD_PREP(CTXDESC_CD_0_TCR_SH0, tcr->sh) | FIELD_PREP(CTXDESC_CD_0_TCR_IPS, tcr->ips) | CTXDESC_CD_0_TCR_EPD1 | CTXDESC_CD_0_AA64; - cfg->cd.mair =3D pgtbl_cfg->arm_lpae_s1_cfg.mair; + cd->mair =3D pgtbl_cfg->arm_lpae_s1_cfg.mair; =20 /* * Note that this will end up calling arm_smmu_sync_cd() before * the master has been added to the devices list for this domain. * This isn't an issue because the STE hasn't been installed yet. */ - ret =3D arm_smmu_write_ctx_desc(smmu_domain, 0, &cfg->cd); + ret =3D arm_smmu_write_ctx_desc(smmu_domain, 0, cd); if (ret) goto out_free_cd_tables; =20 @@ -2141,7 +2142,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_smm= u_domain *smmu_domain, out_free_cd_tables: arm_smmu_free_cd_tables(smmu_domain); out_free_asid: - arm_smmu_free_asid(&cfg->cd); + arm_smmu_free_asid(cd); out_unlock: mutex_unlock(&arm_smmu_asid_lock); return ret; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index b574c58a34876..68d519f21dbd8 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -593,7 +593,6 @@ struct arm_smmu_ctx_desc_cfg { =20 struct arm_smmu_s1_cfg { struct arm_smmu_ctx_desc_cfg cdcfg; - struct arm_smmu_ctx_desc cd; u8 s1fmt; u8 s1cdmax; }; @@ -707,25 +706,28 @@ enum arm_smmu_domain_stage { }; =20 struct arm_smmu_domain { - struct arm_smmu_device *smmu; - struct mutex init_mutex; /* Protects smmu pointer */ + struct arm_smmu_device *smmu; + struct mutex init_mutex; /* Protects smmu pointer */ =20 - struct io_pgtable_ops *pgtbl_ops; - bool stall_enabled; - atomic_t nr_ats_masters; + struct io_pgtable_ops *pgtbl_ops; + bool stall_enabled; + atomic_t nr_ats_masters; =20 - enum arm_smmu_domain_stage stage; + enum arm_smmu_domain_stage stage; union { - struct arm_smmu_s1_cfg s1_cfg; - struct arm_smmu_s2_cfg s2_cfg; + struct { + struct arm_smmu_ctx_desc cd; + struct arm_smmu_s1_cfg s1_cfg; + }; + struct arm_smmu_s2_cfg s2_cfg; }; =20 - struct iommu_domain domain; + struct iommu_domain domain; =20 - struct list_head devices; - spinlock_t devices_lock; + struct list_head devices; + spinlock_t devices_lock; =20 - struct list_head mmu_notifiers; + struct list_head mmu_notifiers; }; =20 static inline struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *= dom) --=20 2.41.0.162.gfafddb0af9-goog