From nobody Mon Feb 9 02:15:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B532EB64D9 for ; Wed, 14 Jun 2023 11:14:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243819AbjFNLOx (ORCPT ); Wed, 14 Jun 2023 07:14:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35846 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230249AbjFNLOe (ORCPT ); Wed, 14 Jun 2023 07:14:34 -0400 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id AE4C91FC1; Wed, 14 Jun 2023 04:14:31 -0700 (PDT) Received: from loongson.cn (unknown [10.20.42.116]) by gateway (Coremail) with SMTP id _____8DxTusUoYlkPBoFAA--.10766S3; Wed, 14 Jun 2023 19:14:28 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.42.116]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Bx+OQSoYlk_IkaAA--.10128S3; Wed, 14 Jun 2023 19:14:28 +0800 (CST) From: Jianmin Lv To: Thomas Gleixner , Marc Zyngier Cc: linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Lorenzo Pieralisi , Jiaxun Yang , Huacai Chen , WANG Xuerui , loongson-kernel@lists.loongnix.cn, stable@vger.kernel.org Subject: [PATCH V1 1/4] irqchip/loongson-pch-pic: Fix initialization of HT vector register Date: Wed, 14 Jun 2023 19:14:23 +0800 Message-Id: <20230614111426.5545-2-lvjianmin@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20230614111426.5545-1-lvjianmin@loongson.cn> References: <20230614111426.5545-1-lvjianmin@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8Bx+OQSoYlk_IkaAA--.10128S3 X-CM-SenderInfo: 5oymxthqpl0qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoW7AF17uFyrZF1rXFWkJF43Arc_yoW8uw4xpa yaqa1avr4UJr4UKFy8Ga1rXFy3Ja9xC39rKa1Yyrn3Xws8Ca4DKrsrA3W0vFWxCrW7Z3W3 ZrWSv3WrC3W5AFcCm3ZEXasCq-sJn29KB7ZKAUJUUUU3529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUBYb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r126r13M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVWxJr0_GcWl84ACjcxK6I8E87Iv6xkF7I0E14v2 6rxl6s0DM2kKe7AKxVWUAVWUtwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYI kI8VC2zVCFFI0UMc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUtVWr XwAv7VC2z280aVAFwI0_Gr0_Cr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI4 8JMxkF7I0En4kS14v26r126r1DMxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j 6r4UMxCIbckI1I0E14v26r126r1DMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwV AFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv2 0xvE14v26r4j6ryUMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4 v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY1x0267AK xVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7IU8Gii3UUUUU== Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In a dual-bridge system based ACPI, the IRQ on PCH PIC of each bridge sent to CPU is always a zero-based number, which means that the IRQ on PCH PIC of each bridge is mapped into vector range from 0 to 63 of upstream irqchip(e.g. EIOINTC). EIOINTC N: [0 ... 63 | 64 ... 255] -------- ---------- ^ ^ | | PCH PIC N | PCH MSI N For example, the IRQ vector number of sata controller on PCH PIC of each bridge is 16, which is sent to upstream irqchip of EIOINTC when an interrupt occurs, which will set bit 16 of EIOINTC. Since hwirq of 16 on EIOINTC has been mapped to a irq_desc for sata controller during hierarchy irq allocation, the related mapped IRQ will be found through irq_resolve_mapping() in the IRQ domain of EIOINTC. So, the IRQ number set in HT vector register should be fixed to be a zero-based number. Cc: stable@vger.kernel.org Signed-off-by: Jianmin Lv Signed-off-by: liuyun --- drivers/irqchip/irq-loongson-pch-pic.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-l= oongson-pch-pic.c index e5fe4d50be05..921c5c0190d1 100644 --- a/drivers/irqchip/irq-loongson-pch-pic.c +++ b/drivers/irqchip/irq-loongson-pch-pic.c @@ -401,14 +401,12 @@ static int __init acpi_cascade_irqdomain_init(void) int __init pch_pic_acpi_init(struct irq_domain *parent, struct acpi_madt_bio_pic *acpi_pchpic) { - int ret, vec_base; + int ret; struct fwnode_handle *domain_handle; =20 if (find_pch_pic(acpi_pchpic->gsi_base) >=3D 0) return 0; =20 - vec_base =3D acpi_pchpic->gsi_base - GSI_MIN_PCH_IRQ; - domain_handle =3D irq_domain_alloc_fwnode(&acpi_pchpic->address); if (!domain_handle) { pr_err("Unable to allocate domain handle\n"); @@ -416,7 +414,7 @@ int __init pch_pic_acpi_init(struct irq_domain *parent, } =20 ret =3D pch_pic_init(acpi_pchpic->address, acpi_pchpic->size, - vec_base, parent, domain_handle, acpi_pchpic->gsi_base); + 0, parent, domain_handle, acpi_pchpic->gsi_base); =20 if (ret < 0) { irq_domain_free_fwnode(domain_handle); --=20 2.31.1 From nobody Mon Feb 9 02:15:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5659EB64DA for ; Wed, 14 Jun 2023 11:14:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235253AbjFNLOq (ORCPT ); Wed, 14 Jun 2023 07:14:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35812 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230301AbjFNLOb (ORCPT ); Wed, 14 Jun 2023 07:14:31 -0400 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 142F71BE5; Wed, 14 Jun 2023 04:14:29 -0700 (PDT) Received: from loongson.cn (unknown [10.20.42.116]) by gateway (Coremail) with SMTP id _____8Cx8OgUoYlkRBoFAA--.8923S3; Wed, 14 Jun 2023 19:14:28 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.42.116]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Bx+OQSoYlk_IkaAA--.10128S4; Wed, 14 Jun 2023 19:14:28 +0800 (CST) From: Jianmin Lv To: Thomas Gleixner , Marc Zyngier Cc: linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Lorenzo Pieralisi , Jiaxun Yang , Huacai Chen , WANG Xuerui , loongson-kernel@lists.loongnix.cn, Liu Peibao , stable@vger.kernel.org Subject: [PATCH V1 2/4] irqchip/loongson-pch-pic: Fix potential incorrect hwirq assignment Date: Wed, 14 Jun 2023 19:14:24 +0800 Message-Id: <20230614111426.5545-3-lvjianmin@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20230614111426.5545-1-lvjianmin@loongson.cn> References: <20230614111426.5545-1-lvjianmin@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8Bx+OQSoYlk_IkaAA--.10128S4 X-CM-SenderInfo: 5oymxthqpl0qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoW7uF48ZrWxXFWfGr4kXw47Awc_yoW8Cr1kpF 4UCw4S9F4DAF1jyw18Gw4kW343A39xtFW7Ka1SyF93Wr1kJ34qkF1UZF1F9r1kArWfAFWU ZrZI9FWY9F1xAFXCm3ZEXasCq-sJn29KB7ZKAUJUUUU3529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUBYb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1a6r1DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVWxJr0_GcWl84ACjcxK6I8E87Iv6xkF7I0E14v2 6rxl6s0DM2kKe7AKxVWUAVWUtwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYI kI8VC2zVCFFI0UMc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUtVWr XwAv7VC2z280aVAFwI0_Gr0_Cr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI4 8JMxkF7I0En4kS14v26r126r1DMxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j 6r4UMxCIbckI1I0E14v26r126r1DMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwV AFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv2 0xvE14v26ryj6F1UMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4 v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY1x0267AK xVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7IU14v3UUUUUU== Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Liu Peibao In DeviceTree path, when ht_vec_base is not zero, the hwirq of PCH PIC will be assigned incorrectly. Because when pch_pic_domain_translate() adds the ht_vec_base to hwirq, the hwirq dose not subtract the ht_vec_base when calling irq_domain_set_info(). The ht_vec_base is designed for the parent irq chip/domain of the PCH PIC. It seems not proper to deal this in callbacks of the PCH PIC domain and let's put this back like the initial commit ef8c01eb64ca ("irqchip: Add Loongson PCH PIC controller"). Fixes: bcdd75c596c8 ("irqchip/loongson-pch-pic: Add ACPI init support") Cc: stable@vger.kernel.org Signed-off-by: Liu Peibao Signed-off-by: Jianmin Lv --- drivers/irqchip/irq-loongson-pch-pic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-l= oongson-pch-pic.c index 921c5c0190d1..93a71f66efeb 100644 --- a/drivers/irqchip/irq-loongson-pch-pic.c +++ b/drivers/irqchip/irq-loongson-pch-pic.c @@ -164,7 +164,7 @@ static int pch_pic_domain_translate(struct irq_domain *= d, if (fwspec->param_count < 2) return -EINVAL; =20 - *hwirq =3D fwspec->param[0] + priv->ht_vec_base; + *hwirq =3D fwspec->param[0]; *type =3D fwspec->param[1] & IRQ_TYPE_SENSE_MASK; } else { if (fwspec->param_count < 1) @@ -196,7 +196,7 @@ static int pch_pic_alloc(struct irq_domain *domain, uns= igned int virq, =20 parent_fwspec.fwnode =3D domain->parent->fwnode; parent_fwspec.param_count =3D 1; - parent_fwspec.param[0] =3D hwirq; + parent_fwspec.param[0] =3D hwirq + priv->ht_vec_base; =20 err =3D irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec); if (err) --=20 2.31.1 From nobody Mon Feb 9 02:15:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A39AEB64D9 for ; Wed, 14 Jun 2023 11:14:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243799AbjFNLOs (ORCPT ); Wed, 14 Jun 2023 07:14:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235926AbjFNLOc (ORCPT ); Wed, 14 Jun 2023 07:14:32 -0400 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 2E2231BF3; Wed, 14 Jun 2023 04:14:30 -0700 (PDT) Received: from loongson.cn (unknown [10.20.42.116]) by gateway (Coremail) with SMTP id _____8Cx_eoUoYlkUBoFAA--.11011S3; Wed, 14 Jun 2023 19:14:28 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.42.116]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Bx+OQSoYlk_IkaAA--.10128S5; Wed, 14 Jun 2023 19:14:28 +0800 (CST) From: Jianmin Lv To: Thomas Gleixner , Marc Zyngier Cc: linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Lorenzo Pieralisi , Jiaxun Yang , Huacai Chen , WANG Xuerui , loongson-kernel@lists.loongnix.cn, stable@vger.kernel.org Subject: [PATCH V1 3/4] irqchip/loongson-liointc: Fix IRQ trigger polarity Date: Wed, 14 Jun 2023 19:14:25 +0800 Message-Id: <20230614111426.5545-4-lvjianmin@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20230614111426.5545-1-lvjianmin@loongson.cn> References: <20230614111426.5545-1-lvjianmin@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8Bx+OQSoYlk_IkaAA--.10128S5 X-CM-SenderInfo: 5oymxthqpl0qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoW7Zw1rKF1rtr1UZr1kGrWfZwc_yoW8ur13p3 yfC3Wktr4aqFyUW3WUKr48X3W3JwnIqwsrKa13W345uFZ0kan5A3yrZFZFvr1xKa48GF42 krWrGay5Way3uwbCm3ZEXasCq-sJn29KB7ZKAUJUUUU3529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUBFb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r126r13M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Ar0_tr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Cr0_Gr1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AK xVW0oVCq3wAaw2AFwI0_JF0_Jw1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0c Ia020Ex4CE44I27wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Wrv_ ZF1lYx0Ex4A2jsIE14v26r4j6F4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwI xGrwCY1x0262kKe7AKxVWUAVWUtwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWU JVW8JwCFI7km07C267AKxVWUAVWUtwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4 vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IY x2IY67AKxVW5JVW7JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26c xKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIEc7CjxVAF wI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x07jfyCLUUUUU= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" For IRQ controller INT_POLARITY regitser of Loongson-2K CPU series, '0' indicates high level or rising edge triggered IRQ, '1' indicates low level or falling edge triggered IRQ. For Loongson-3A CPU series, setting INT_POLARITY register is not supported and writting it has no effect. So trigger polarity setting shouled be fixed for Loongson-2K CPU series. Fixes: 17343d0b4039 ("irqchip/loongson-liointc: Support to set IRQ type for= ACPI path") Cc: stable@vger.kernel.org Signed-off-by: Chong Qiao Signed-off-by: Jianmin Lv --- drivers/irqchip/irq-loongson-liointc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-l= oongson-liointc.c index 8d00a9ad5b00..9a9c2bf048a3 100644 --- a/drivers/irqchip/irq-loongson-liointc.c +++ b/drivers/irqchip/irq-loongson-liointc.c @@ -116,19 +116,19 @@ static int liointc_set_type(struct irq_data *data, un= signed int type) switch (type) { case IRQ_TYPE_LEVEL_HIGH: liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false); - liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true); + liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false); break; case IRQ_TYPE_LEVEL_LOW: liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false); - liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false); + liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true); break; case IRQ_TYPE_EDGE_RISING: liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true); - liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true); + liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false); break; case IRQ_TYPE_EDGE_FALLING: liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true); - liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false); + liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true); break; default: irq_gc_unlock_irqrestore(gc, flags); --=20 2.31.1 From nobody Mon Feb 9 02:15:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB815EB64D9 for ; Wed, 14 Jun 2023 11:14:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243710AbjFNLOn (ORCPT ); Wed, 14 Jun 2023 07:14:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35818 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235961AbjFNLOc (ORCPT ); Wed, 14 Jun 2023 07:14:32 -0400 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 46F1A1BF6 for ; Wed, 14 Jun 2023 04:14:31 -0700 (PDT) Received: from loongson.cn (unknown [10.20.42.116]) by gateway (Coremail) with SMTP id _____8DxSuoUoYlkTxoFAA--.10737S3; Wed, 14 Jun 2023 19:14:28 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.42.116]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Bx+OQSoYlk_IkaAA--.10128S6; Wed, 14 Jun 2023 19:14:28 +0800 (CST) From: Jianmin Lv To: Thomas Gleixner , Marc Zyngier Cc: linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Lorenzo Pieralisi , Jiaxun Yang , Huacai Chen , WANG Xuerui , loongson-kernel@lists.loongnix.cn, Yinbo Zhu Subject: [PATCH V1 4/4] irqchip/loongson-liointc: Add IRQCHIP_SKIP_SET_WAKE flag Date: Wed, 14 Jun 2023 19:14:26 +0800 Message-Id: <20230614111426.5545-5-lvjianmin@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20230614111426.5545-1-lvjianmin@loongson.cn> References: <20230614111426.5545-1-lvjianmin@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8Bx+OQSoYlk_IkaAA--.10128S6 X-CM-SenderInfo: 5oymxthqpl0qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj9xXoW7Jry3XF48ZrW3Wr4UtrW8GrX_yoWkXFg_WF y7Jwn5CryIvrsIka4xCr4Utr1F93y5uanrua1FvFs3Z348tw45Cay3Z3ZxGFWUKryjvF93 Kr48Wr4rCrWxtosvyTuYvTs0mTUanT9S1TB71UUUUj7qnTZGkaVYY2UrUUUUj1kv1TuYvT s0mT0YCTnIWjqI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUI cSsGvfJTRUUUbfAYFVCjjxCrM7AC8VAFwI0_Jr0_Gr1l1xkIjI8I6I8E6xAIw20EY4v20x vaj40_Wr0E3s1l1IIY67AEw4v_JF0_JFyl8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxS w2x7M28EF7xvwVC0I7IYx2IY67AKxVW7JVWDJwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxV WxJVW8Jr1l84ACjcxK6I8E87Iv67AKxVWxJr0_GcWl84ACjcxK6I8E87Iv6xkF7I0E14v2 6rxl6s0DM2kKe7AKxVWUAVWUtwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYI kI8VC2zVCFFI0UMc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWrXVW3 AwAv7VC2z280aVAFwI0_Gr0_Cr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI4 8JMxkF7I0En4kS14v26r126r1DMxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j 6r4UMxCIbckI1I0E14v26r126r1DMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwV AFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv2 0xvE14v26ryj6F1UMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4 v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY1x0267AK xVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7IU0XzstUUUUU== Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yinbo Zhu Liointc doesn't require specific logic to work with wakeup IRQs, and no irq_set_wake callback is needed. To allow registered IRQs from liointc to be used as a wakeup-source, and ensure irq_set_irq_wake() works well, the flag IRQCHIP_SKIP_SET_WAKE should be added. Signed-off-by: Yinbo Zhu Signed-off-by: Jianmin Lv --- drivers/irqchip/irq-loongson-liointc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-l= oongson-liointc.c index 9a9c2bf048a3..dbd1ccce0fb2 100644 --- a/drivers/irqchip/irq-loongson-liointc.c +++ b/drivers/irqchip/irq-loongson-liointc.c @@ -291,6 +291,7 @@ static int liointc_init(phys_addr_t addr, unsigned long= size, int revision, ct->chip.irq_mask =3D irq_gc_mask_disable_reg; ct->chip.irq_mask_ack =3D irq_gc_mask_disable_reg; ct->chip.irq_set_type =3D liointc_set_type; + ct->chip.flags =3D IRQCHIP_SKIP_SET_WAKE; =20 gc->mask_cache =3D 0; priv->gc =3D gc; --=20 2.31.1