From nobody Tue Feb 10 13:55:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80D7BEB64DD for ; Wed, 14 Jun 2023 10:48:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243620AbjFNKsZ (ORCPT ); Wed, 14 Jun 2023 06:48:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53996 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243391AbjFNKsM (ORCPT ); Wed, 14 Jun 2023 06:48:12 -0400 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 16C05196; Wed, 14 Jun 2023 03:48:11 -0700 (PDT) Received: by mail-lf1-x12b.google.com with SMTP id 2adb3069b0e04-4f004cc54f4so8309405e87.3; Wed, 14 Jun 2023 03:48:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686739689; x=1689331689; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tM8oQ5AlHX+UtLTwuEHmAQC8MFGQX+BK7/3h+w5idWQ=; b=L2mvdjB12HTMe/Ko13qtOnLqgQSnFQnZ2adLuqHuT2Fg8AkxyrgAl1RDkxwu0YHZ7n BHR6aqhNpuLgf9lBdJjkyBEYSJAFseA8519zmBlGw5RGLGh66OpbHnpOEfl5boynmRY2 QvWbM+IWoVyWq2+5BzFNc3jEAfIbNKrq5mFHvQliB5F6jnh8ImG8KE+gcDjJV1aXt1VA EQUMtxVBiU9ANvF7cvoMEcpsM4Qfi+SZKPO3fRDE4owr86nNmcejA4TjO6jPCYoiAG8d iueoTjU9nHapbFyEHtc+zHXJVpeliWg/tokyf874LzrMFswgE5G0UbFig/qrnyJfOZU7 Khmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686739689; x=1689331689; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tM8oQ5AlHX+UtLTwuEHmAQC8MFGQX+BK7/3h+w5idWQ=; b=aQ0X6xRxGpAOSjPJ5yIinjWpDATliDYJhYp1g3Mntla5GK6m9hBzRX2Qn5jMT0Y9/T pSNzEiE2xyakVkZxmuJxlgGQIVDVEaYvTvv2aAwsuDsYfI7C7UtUQV+bWvaAlE8Q9rvu 2BjbX2SXBe+Avs06r0VXqSt4KyEOpazUGLigVF176Wt73nI2KAFX+reA2szwhGSBMcl7 ULoJ/yqj1Akz/bJoxzAqiWAENrC5zYQG7bMpDiJrOpD4sYis+kfwm+eWm/B7ze8NuQGQ 0wcYMuYRUf9kYt9FqYHFWUvsFJm1NSMdu1aHv6LD4RQgDazX9ThCMeakW0ws3U+Avz+Z 6SAA== X-Gm-Message-State: AC+VfDw/FUMMf82EsBf8ENgdCTk9dn1e5Da55Qh5SdkRw0RQrmi9M8ws i6ltj8B8IQcmT4q1H11Y1ZI= X-Google-Smtp-Source: ACHHUZ5+wolNsUfzELG5dXQ99D3K3lMZap+4xaVfFXGKTV3ZVZZBWPyFtpylgV/LfPhL4hNikMLXfw== X-Received: by 2002:a19:661a:0:b0:4f7:6891:a511 with SMTP id a26-20020a19661a000000b004f76891a511mr794311lfc.40.1686739689115; Wed, 14 Jun 2023 03:48:09 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:64d6:8737:b80d:a298]) by smtp.gmail.com with ESMTPSA id y10-20020a1c4b0a000000b003f5ffba9ae1sm17154904wma.24.2023.06.14.03.48.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jun 2023 03:48:08 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Arnd Bergmann , Conor Dooley , Geert Uytterhoeven , Guo Ren , Andrew Jones , Paul Walmsley , Palmer Dabbelt , Albert Ou , Samuel Holland , linux-riscv@lists.infradead.org, Christoph Hellwig Cc: Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar , Rob Herring Subject: [PATCH v9 4/6] dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller Date: Wed, 14 Jun 2023 11:47:57 +0100 Message-Id: <20230614104759.228372-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230614104759.228372-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20230614104759.228372-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add DT binding documentation for L2 cache controller found on RZ/Five SoC. The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) from Andes. The AX45MP core has an L2 cache controller, this patch describes the L2 cache block. Signed-off-by: Lad Prabhakar Reviewed-by: Rob Herring Reviewed-by: Conor Dooley --- v8 -> v9 * No Change v7 -> v8 * Updated commit header message v6 -> v7 * No Change v5 -> v6 * Included RB tag from Rob v4 -> v5 * Dropped L2 cache configuration properties * Dropped PMA configuration properties * Ordered the required list to match the properties list RFC v3 -> v4 * Dropped l2 cache configuration parameters * s/larger/large * Added minItems/maxItems for andestech,pma-regions --- .../cache/andestech,ax45mp-cache.yaml | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/cache/andestech,ax45m= p-cache.yaml diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache= .yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml new file mode 100644 index 000000000000..9ab5f0c435d4 --- /dev/null +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2023 Renesas Electronics Corp. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andestech AX45MP L2 Cache Controller + +maintainers: + - Lad Prabhakar + +description: + A level-2 cache (L2C) is used to improve the system performance by provi= ding + a large amount of cache line entries and reasonable access delays. The L= 2C + is shared between cores, and a non-inclusive non-exclusive policy is use= d. + +select: + properties: + compatible: + contains: + enum: + - andestech,ax45mp-cache + + required: + - compatible + +properties: + compatible: + items: + - const: andestech,ax45mp-cache + - const: cache + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + cache-line-size: + const: 64 + + cache-level: + const: 2 + + cache-sets: + const: 1024 + + cache-size: + enum: [131072, 262144, 524288, 1048576, 2097152] + + cache-unified: true + + next-level-cache: true + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - cache-line-size + - cache-level + - cache-sets + - cache-size + - cache-unified + +examples: + - | + #include + + cache-controller@2010000 { + compatible =3D "andestech,ax45mp-cache", "cache"; + reg =3D <0x13400000 0x100000>; + interrupts =3D <508 IRQ_TYPE_LEVEL_HIGH>; + cache-line-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <1024>; + cache-size =3D <262144>; + cache-unified; + }; --=20 2.25.1