From nobody Sat Feb 7 18:21:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64A2AC001B0 for ; Tue, 13 Jun 2023 22:51:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241152AbjFMWvq (ORCPT ); Tue, 13 Jun 2023 18:51:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45312 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240075AbjFMWvi (ORCPT ); Tue, 13 Jun 2023 18:51:38 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 304081BE8; Tue, 13 Jun 2023 15:51:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686696696; x=1718232696; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=I60/32haUYfAuABbHChphwlOIug946wG47T0uZuxnoM=; b=USQOcvpcJ5cs5QIikBr6RdkBPrcDojeJsZjyEx8of9H01jc5evaQbUfs R7/7QfwOu8CSuefnRAfzC8EwbEArBDKbj3IJsIZZWWq1tHMLLJjMwFEnR GIqbSt6dh6tr5yvPr9rvEfJoMJIkD9U2MNm/1/mk4atz+ybGNKyDzYwRI 4k8miuOSuoCV+XL8hTg+QnM1hyAsg2tO0y2hSd6ObgbybITrLci2UAg3U lj++UPtiTnTkfbD5C70oHWjjkzYnampWuCWjZ6EKNRGD5ZAw2ecZ3PBsI DuFE4snke436qWfk8ZCSEV2F+m3QspWlsKRjBmgHBZC/xKSDMekBEX2B6 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10740"; a="444842175" X-IronPort-AV: E=Sophos;i="6.00,241,1681196400"; d="scan'208";a="444842175" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jun 2023 15:51:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10740"; a="824589630" X-IronPort-AV: E=Sophos;i="6.00,241,1681196400"; d="scan'208";a="824589630" Received: from linux.intel.com ([10.54.29.200]) by fmsmga002.fm.intel.com with ESMTP; 13 Jun 2023 15:51:35 -0700 Received: from rjingar-desk5.amr.corp.intel.com (hciettox-mobl.amr.corp.intel.com [10.212.23.107]) by linux.intel.com (Postfix) with ESMTP id 9A8B5580BEE; Tue, 13 Jun 2023 15:51:34 -0700 (PDT) From: Rajvi Jingar To: david.e.box@linux.intel.com, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, hdegoede@redhat.com Cc: xi.pardee@intel.com, Rajvi Jingar Subject: [PATCH 1/8] platform/x86:intel/pmc: Update maps for Meteor Lake P/M platforms Date: Tue, 13 Jun 2023 15:53:40 -0700 Message-Id: <20230613225347.2720665-2-rajvi.jingar@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613225347.2720665-1-rajvi.jingar@linux.intel.com> References: <20230613225347.2720665-1-rajvi.jingar@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xi Pardee Fix the IP name errors in the register maps used by the following debugfs attributes in the Meteor Lake SOC-M PMC. pfear_sts lpm_sts ltr_show Fixes: c5ad454a12c6 ("platform/x86: intel/pmc/core: Add Meteor Lake support= to pmc core driver") Signed-off-by: Xi Pardee Signed-off-by: Rajvi Jingar Reviewed-by: Ilpo J=C3=A4rvinen --- drivers/platform/x86/intel/pmc/core.h | 28 +- drivers/platform/x86/intel/pmc/mtl.c | 448 +++++++++++++++++++++++++- 2 files changed, 466 insertions(+), 10 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/i= ntel/pmc/core.h index 7c95586e742b..86d38270000a 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/drivers/platform/x86/intel/pmc/core.h @@ -249,6 +249,14 @@ enum ppfear_regs { #define MTL_LPM_STATUS_LATCH_EN_OFFSET 0x16F8 #define MTL_LPM_STATUS_OFFSET 0x1700 #define MTL_LPM_LIVE_STATUS_OFFSET 0x175C +#define MTL_PMC_LTR_IOE_PMC 0x1C0C +#define MTL_PMC_LTR_ESE 0x1BAC +#define MTL_SOCM_NUM_IP_IGN_ALLOWED 25 +#define MTL_SOC_PMC_MMIO_REG_LEN 0x2708 +#define MTL_PMC_LTR_SPG 0x1B74 + +/* Meteor Lake PGD PFET Enable Ack Status */ +#define MTL_SOCM_PPFEAR_NUM_ENTRIES 8 =20 extern const char *pmc_lpm_modes[]; =20 @@ -395,7 +403,25 @@ extern const struct pmc_bit_map adl_vnn_req_status_3_m= ap[]; extern const struct pmc_bit_map adl_vnn_misc_status_map[]; extern const struct pmc_bit_map *adl_lpm_maps[]; extern const struct pmc_reg_map adl_reg_map; -extern const struct pmc_reg_map mtl_reg_map; +extern const struct pmc_bit_map mtl_socm_pfear_map[]; +extern const struct pmc_bit_map *ext_mtl_socm_pfear_map[]; +extern const struct pmc_bit_map mtl_socm_ltr_show_map[]; +extern const struct pmc_bit_map mtl_socm_clocksource_status_map[]; +extern const struct pmc_bit_map mtl_socm_power_gating_status_0_map[]; +extern const struct pmc_bit_map mtl_socm_power_gating_status_1_map[]; +extern const struct pmc_bit_map mtl_socm_power_gating_status_2_map[]; +extern const struct pmc_bit_map mtl_socm_d3_status_0_map[]; +extern const struct pmc_bit_map mtl_socm_d3_status_1_map[]; +extern const struct pmc_bit_map mtl_socm_d3_status_2_map[]; +extern const struct pmc_bit_map mtl_socm_d3_status_3_map[]; +extern const struct pmc_bit_map mtl_socm_vnn_req_status_0_map[]; +extern const struct pmc_bit_map mtl_socm_vnn_req_status_1_map[]; +extern const struct pmc_bit_map mtl_socm_vnn_req_status_2_map[]; +extern const struct pmc_bit_map mtl_socm_vnn_req_status_3_map[]; +extern const struct pmc_bit_map mtl_socm_vnn_misc_status_map[]; +extern const struct pmc_bit_map mtl_socm_signal_status_map[]; +extern const struct pmc_bit_map *mtl_socm_lpm_maps[]; +extern const struct pmc_reg_map mtl_socm_reg_map; =20 extern void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev); extern int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value); diff --git a/drivers/platform/x86/intel/pmc/mtl.c b/drivers/platform/x86/in= tel/pmc/mtl.c index 2b00ad9da621..cdcf743b5e2c 100644 --- a/drivers/platform/x86/intel/pmc/mtl.c +++ b/drivers/platform/x86/intel/pmc/mtl.c @@ -11,28 +11,458 @@ #include #include "core.h" =20 -const struct pmc_reg_map mtl_reg_map =3D { - .pfear_sts =3D ext_tgl_pfear_map, +/* + * Die Mapping to Product. + * Product SOCDie IOEDie PCHDie + * MTL-M SOC-M IOE-M None + * MTL-P SOC-M IOE-P None + * MTL-S SOC-S IOE-P PCH-S + */ + +const struct pmc_bit_map mtl_socm_pfear_map[] =3D { + {"PMC", BIT(0)}, + {"OPI", BIT(1)}, + {"SPI", BIT(2)}, + {"XHCI", BIT(3)}, + {"SPA", BIT(4)}, + {"SPB", BIT(5)}, + {"SPC", BIT(6)}, + {"GBE", BIT(7)}, + + {"SATA", BIT(0)}, + {"DSP0", BIT(1)}, + {"DSP1", BIT(2)}, + {"DSP2", BIT(3)}, + {"DSP3", BIT(4)}, + {"SPD", BIT(5)}, + {"LPSS", BIT(6)}, + {"LPC", BIT(7)}, + + {"SMB", BIT(0)}, + {"ISH", BIT(1)}, + {"P2SB", BIT(2)}, + {"NPK_VNN", BIT(3)}, + {"SDX", BIT(4)}, + {"SPE", BIT(5)}, + {"FUSE", BIT(6)}, + {"SBR8", BIT(7)}, + + {"RSVD24", BIT(0)}, + {"OTG", BIT(1)}, + {"EXI", BIT(2)}, + {"CSE", BIT(3)}, + {"CSME_KVM", BIT(4)}, + {"CSME_PMT", BIT(5)}, + {"CSME_CLINK", BIT(6)}, + {"CSME_PTIO", BIT(7)}, + + {"CSME_USBR", BIT(0)}, + {"CSME_SUSRAM", BIT(1)}, + {"CSME_SMT1", BIT(2)}, + {"RSVD35", BIT(3)}, + {"CSME_SMS2", BIT(4)}, + {"CSME_SMS", BIT(5)}, + {"CSME_RTC", BIT(6)}, + {"CSME_PSF", BIT(7)}, + + {"SBR0", BIT(0)}, + {"SBR1", BIT(1)}, + {"SBR2", BIT(2)}, + {"SBR3", BIT(3)}, + {"SBR4", BIT(4)}, + {"SBR5", BIT(5)}, + {"RSVD46", BIT(6)}, + {"PSF1", BIT(7)}, + + {"PSF2", BIT(0)}, + {"PSF3", BIT(1)}, + {"PSF4", BIT(2)}, + {"CNVI", BIT(3)}, + {"UFSX2", BIT(4)}, + {"EMMC", BIT(5)}, + {"SPF", BIT(6)}, + {"SBR6", BIT(7)}, + + {"SBR7", BIT(0)}, + {"NPK_AON", BIT(1)}, + {"HDA4", BIT(2)}, + {"HDA5", BIT(3)}, + {"HDA6", BIT(4)}, + {"PSF6", BIT(5)}, + {"RSVD62", BIT(6)}, + {"RSVD63", BIT(7)}, + {} +}; + +const struct pmc_bit_map *ext_mtl_socm_pfear_map[] =3D { + mtl_socm_pfear_map, + NULL +}; + +const struct pmc_bit_map mtl_socm_ltr_show_map[] =3D { + {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, + {"SOUTHPORT_B", CNP_PMC_LTR_SPB}, + {"SATA", CNP_PMC_LTR_SATA}, + {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE}, + {"XHCI", CNP_PMC_LTR_XHCI}, + {"SOUTHPORT_F", ADL_PMC_LTR_SPF}, + {"ME", CNP_PMC_LTR_ME}, + {"SATA1", CNP_PMC_LTR_EVA}, + {"SOUTHPORT_C", CNP_PMC_LTR_SPC}, + {"HD_AUDIO", CNP_PMC_LTR_AZ}, + {"CNV", CNP_PMC_LTR_CNV}, + {"LPSS", CNP_PMC_LTR_LPSS}, + {"SOUTHPORT_D", CNP_PMC_LTR_SPD}, + {"SOUTHPORT_E", CNP_PMC_LTR_SPE}, + {"SATA2", CNP_PMC_LTR_CAM}, + {"ESPI", CNP_PMC_LTR_ESPI}, + {"SCC", CNP_PMC_LTR_SCC}, + {"ISH", CNP_PMC_LTR_ISH}, + {"UFSX2", CNP_PMC_LTR_UFSX2}, + {"EMMC", CNP_PMC_LTR_EMMC}, + {"WIGIG", ICL_PMC_LTR_WIGIG}, + {"THC0", TGL_PMC_LTR_THC0}, + {"THC1", TGL_PMC_LTR_THC1}, + {"SOUTHPORT_G", MTL_PMC_LTR_SPG}, + {"ESE", MTL_PMC_LTR_ESE}, + {"IOE_PMC", MTL_PMC_LTR_IOE_PMC}, + + /* Below two cannot be used for LTR_IGNORE */ + {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT}, + {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT}, + {} +}; + +const struct pmc_bit_map mtl_socm_clocksource_status_map[] =3D { + {"AON2_OFF_STS", BIT(0)}, + {"AON3_OFF_STS", BIT(1)}, + {"AON4_OFF_STS", BIT(2)}, + {"AON5_OFF_STS", BIT(3)}, + {"AON1_OFF_STS", BIT(4)}, + {"XTAL_LVM_OFF_STS", BIT(5)}, + {"MPFPW1_0_PLL_OFF_STS", BIT(6)}, + {"MPFPW1_1_PLL_OFF_STS", BIT(7)}, + {"USB3_PLL_OFF_STS", BIT(8)}, + {"AON3_SPL_OFF_STS", BIT(9)}, + {"MPFPW2_0_PLL_OFF_STS", BIT(12)}, + {"MPFPW3_0_PLL_OFF_STS", BIT(13)}, + {"XTAL_AGGR_OFF_STS", BIT(17)}, + {"USB2_PLL_OFF_STS", BIT(18)}, + {"FILTER_PLL_OFF_STS", BIT(22)}, + {"ACE_PLL_OFF_STS", BIT(24)}, + {"FABRIC_PLL_OFF_STS", BIT(25)}, + {"SOC_PLL_OFF_STS", BIT(26)}, + {"PCIFAB_PLL_OFF_STS", BIT(27)}, + {"REF_PLL_OFF_STS", BIT(28)}, + {"IMG_PLL_OFF_STS", BIT(29)}, + {"RTC_PLL_OFF_STS", BIT(31)}, + {} +}; + +const struct pmc_bit_map mtl_socm_power_gating_status_0_map[] =3D { + {"PMC_PGD0_PG_STS", BIT(0)}, + {"DMI_PGD0_PG_STS", BIT(1)}, + {"ESPISPI_PGD0_PG_STS", BIT(2)}, + {"XHCI_PGD0_PG_STS", BIT(3)}, + {"SPA_PGD0_PG_STS", BIT(4)}, + {"SPB_PGD0_PG_STS", BIT(5)}, + {"SPC_PGD0_PG_STS", BIT(6)}, + {"GBE_PGD0_PG_STS", BIT(7)}, + {"SATA_PGD0_PG_STS", BIT(8)}, + {"PSF13_PGD0_PG_STS", BIT(9)}, + {"SOC_D2D_PGD3_PG_STS", BIT(10)}, + {"MPFPW3_PGD0_PG_STS", BIT(11)}, + {"ESE_PGD0_PG_STS", BIT(12)}, + {"SPD_PGD0_PG_STS", BIT(13)}, + {"LPSS_PGD0_PG_STS", BIT(14)}, + {"LPC_PGD0_PG_STS", BIT(15)}, + {"SMB_PGD0_PG_STS", BIT(16)}, + {"ISH_PGD0_PG_STS", BIT(17)}, + {"P2S_PGD0_PG_STS", BIT(18)}, + {"NPK_PGD0_PG_STS", BIT(19)}, + {"DBG_SBR_PGD0_PG_STS", BIT(20)}, + {"SBRG_PGD0_PG_STS", BIT(21)}, + {"FUSE_PGD0_PG_STS", BIT(22)}, + {"SBR8_PGD0_PG_STS", BIT(23)}, + {"SOC_D2D_PGD2_PG_STS", BIT(24)}, + {"XDCI_PGD0_PG_STS", BIT(25)}, + {"EXI_PGD0_PG_STS", BIT(26)}, + {"CSE_PGD0_PG_STS", BIT(27)}, + {"KVMCC_PGD0_PG_STS", BIT(28)}, + {"PMT_PGD0_PG_STS", BIT(29)}, + {"CLINK_PGD0_PG_STS", BIT(30)}, + {"PTIO_PGD0_PG_STS", BIT(31)}, + {} +}; + +const struct pmc_bit_map mtl_socm_power_gating_status_1_map[] =3D { + {"USBR0_PGD0_PG_STS", BIT(0)}, + {"SUSRAM_PGD0_PG_STS", BIT(1)}, + {"SMT1_PGD0_PG_STS", BIT(2)}, + {"FIACPCB_U_PGD0_PG_STS", BIT(3)}, + {"SMS2_PGD0_PG_STS", BIT(4)}, + {"SMS1_PGD0_PG_STS", BIT(5)}, + {"CSMERTC_PGD0_PG_STS", BIT(6)}, + {"CSMEPSF_PGD0_PG_STS", BIT(7)}, + {"SBR0_PGD0_PG_STS", BIT(8)}, + {"SBR1_PGD0_PG_STS", BIT(9)}, + {"SBR2_PGD0_PG_STS", BIT(10)}, + {"SBR3_PGD0_PG_STS", BIT(11)}, + {"U3FPW1_PGD0_PG_STS", BIT(12)}, + {"SBR5_PGD0_PG_STS", BIT(13)}, + {"MPFPW1_PGD0_PG_STS", BIT(14)}, + {"UFSPW1_PGD0_PG_STS", BIT(15)}, + {"FIA_X_PGD0_PG_STS", BIT(16)}, + {"SOC_D2D_PGD0_PG_STS", BIT(17)}, + {"MPFPW2_PGD0_PG_STS", BIT(18)}, + {"CNVI_PGD0_PG_STS", BIT(19)}, + {"UFSX2_PGD0_PG_STS", BIT(20)}, + {"ENDBG_PGD0_PG_STS", BIT(21)}, + {"DBG_PSF_PGD0_PG_STS", BIT(22)}, + {"SBR6_PGD0_PG_STS", BIT(23)}, + {"SBR7_PGD0_PG_STS", BIT(24)}, + {"NPK_PGD1_PG_STS", BIT(25)}, + {"FIACPCB_X_PGD0_PG_STS", BIT(26)}, + {"DBC_PGD0_PG_STS", BIT(27)}, + {"FUSEGPSB_PGD0_PG_STS", BIT(28)}, + {"PSF6_PGD0_PG_STS", BIT(29)}, + {"PSF7_PGD0_PG_STS", BIT(30)}, + {"GBETSN1_PGD0_PG_STS", BIT(31)}, + {} +}; + +const struct pmc_bit_map mtl_socm_power_gating_status_2_map[] =3D { + {"PSF8_PGD0_PG_STS", BIT(0)}, + {"FIA_PGD0_PG_STS", BIT(1)}, + {"SOC_D2D_PGD1_PG_STS", BIT(2)}, + {"FIA_U_PGD0_PG_STS", BIT(3)}, + {"TAM_PGD0_PG_STS", BIT(4)}, + {"GBETSN_PGD0_PG_STS", BIT(5)}, + {"TBTLSX_PGD0_PG_STS", BIT(6)}, + {"THC0_PGD0_PG_STS", BIT(7)}, + {"THC1_PGD0_PG_STS", BIT(8)}, + {"PMC_PGD1_PG_STS", BIT(9)}, + {"GNA_PGD0_PG_STS", BIT(10)}, + {"ACE_PGD0_PG_STS", BIT(11)}, + {"ACE_PGD1_PG_STS", BIT(12)}, + {"ACE_PGD2_PG_STS", BIT(13)}, + {"ACE_PGD3_PG_STS", BIT(14)}, + {"ACE_PGD4_PG_STS", BIT(15)}, + {"ACE_PGD5_PG_STS", BIT(16)}, + {"ACE_PGD6_PG_STS", BIT(17)}, + {"ACE_PGD7_PG_STS", BIT(18)}, + {"ACE_PGD8_PG_STS", BIT(19)}, + {"FIA_PGS_PGD0_PG_STS", BIT(20)}, + {"FIACPCB_PGS_PGD0_PG_STS", BIT(21)}, + {"FUSEPMSB_PGD0_PG_STS", BIT(22)}, + {} +}; + +const struct pmc_bit_map mtl_socm_d3_status_0_map[] =3D { + {"LPSS_D3_STS", BIT(3)}, + {"XDCI_D3_STS", BIT(4)}, + {"XHCI_D3_STS", BIT(5)}, + {"SPA_D3_STS", BIT(12)}, + {"SPB_D3_STS", BIT(13)}, + {"SPC_D3_STS", BIT(14)}, + {"SPD_D3_STS", BIT(15)}, + {"ESPISPI_D3_STS", BIT(18)}, + {"SATA_D3_STS", BIT(20)}, + {"PSTH_D3_STS", BIT(21)}, + {"DMI_D3_STS", BIT(22)}, + {} +}; + +const struct pmc_bit_map mtl_socm_d3_status_1_map[] =3D { + {"GBETSN1_D3_STS", BIT(14)}, + {"GBE_D3_STS", BIT(19)}, + {"ITSS_D3_STS", BIT(23)}, + {"P2S_D3_STS", BIT(24)}, + {"CNVI_D3_STS", BIT(27)}, + {"UFSX2_D3_STS", BIT(28)}, + {} +}; + +const struct pmc_bit_map mtl_socm_d3_status_2_map[] =3D { + {"GNA_D3_STS", BIT(0)}, + {"CSMERTC_D3_STS", BIT(1)}, + {"SUSRAM_D3_STS", BIT(2)}, + {"CSE_D3_STS", BIT(4)}, + {"KVMCC_D3_STS", BIT(5)}, + {"USBR0_D3_STS", BIT(6)}, + {"ISH_D3_STS", BIT(7)}, + {"SMT1_D3_STS", BIT(8)}, + {"SMT2_D3_STS", BIT(9)}, + {"SMT3_D3_STS", BIT(10)}, + {"CLINK_D3_STS", BIT(14)}, + {"PTIO_D3_STS", BIT(16)}, + {"PMT_D3_STS", BIT(17)}, + {"SMS1_D3_STS", BIT(18)}, + {"SMS2_D3_STS", BIT(19)}, + {} +}; + +const struct pmc_bit_map mtl_socm_d3_status_3_map[] =3D { + {"ESE_D3_STS", BIT(2)}, + {"GBETSN_D3_STS", BIT(13)}, + {"THC0_D3_STS", BIT(14)}, + {"THC1_D3_STS", BIT(15)}, + {"ACE_D3_STS", BIT(23)}, + {} +}; + +const struct pmc_bit_map mtl_socm_vnn_req_status_0_map[] =3D { + {"LPSS_VNN_REQ_STS", BIT(3)}, + {"FIA_VNN_REQ_STS", BIT(17)}, + {"ESPISPI_VNN_REQ_STS", BIT(18)}, + {} +}; + +const struct pmc_bit_map mtl_socm_vnn_req_status_1_map[] =3D { + {"NPK_VNN_REQ_STS", BIT(4)}, + {"DFXAGG_VNN_REQ_STS", BIT(8)}, + {"EXI_VNN_REQ_STS", BIT(9)}, + {"P2D_VNN_REQ_STS", BIT(18)}, + {"GBE_VNN_REQ_STS", BIT(19)}, + {"SMB_VNN_REQ_STS", BIT(25)}, + {"LPC_VNN_REQ_STS", BIT(26)}, + {} +}; + +const struct pmc_bit_map mtl_socm_vnn_req_status_2_map[] =3D { + {"CSMERTC_VNN_REQ_STS", BIT(1)}, + {"CSE_VNN_REQ_STS", BIT(4)}, + {"ISH_VNN_REQ_STS", BIT(7)}, + {"SMT1_VNN_REQ_STS", BIT(8)}, + {"CLINK_VNN_REQ_STS", BIT(14)}, + {"SMS1_VNN_REQ_STS", BIT(18)}, + {"SMS2_VNN_REQ_STS", BIT(19)}, + {"GPIOCOM4_VNN_REQ_STS", BIT(20)}, + {"GPIOCOM3_VNN_REQ_STS", BIT(21)}, + {"GPIOCOM2_VNN_REQ_STS", BIT(22)}, + {"GPIOCOM1_VNN_REQ_STS", BIT(23)}, + {"GPIOCOM0_VNN_REQ_STS", BIT(24)}, + {} +}; + +const struct pmc_bit_map mtl_socm_vnn_req_status_3_map[] =3D { + {"ESE_VNN_REQ_STS", BIT(2)}, + {"DTS0_VNN_REQ_STS", BIT(7)}, + {"GPIOCOM5_VNN_REQ_STS", BIT(11)}, + {} +}; + +const struct pmc_bit_map mtl_socm_vnn_misc_status_map[] =3D { + {"CPU_C10_REQ_STS", BIT(0)}, + {"TS_OFF_REQ_STS", BIT(1)}, + {"PNDE_MET_REQ_STS", BIT(2)}, + {"PCIE_DEEP_PM_REQ_STS", BIT(3)}, + {"PMC_CLK_THROTTLE_EN_REQ_STS", BIT(4)}, + {"NPK_VNNAON_REQ_STS", BIT(5)}, + {"VNN_SOC_REQ_STS", BIT(6)}, + {"ISH_VNNAON_REQ_STS", BIT(7)}, + {"IOE_COND_MET_S02I2_0_REQ_STS", BIT(8)}, + {"IOE_COND_MET_S02I2_1_REQ_STS", BIT(9)}, + {"IOE_COND_MET_S02I2_2_REQ_STS", BIT(10)}, + {"PLT_GREATER_REQ_STS", BIT(11)}, + {"PCIE_CLKREQ_REQ_STS", BIT(12)}, + {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13)}, + {"PM_SYNC_STATES_REQ_STS", BIT(14)}, + {"EA_REQ_STS", BIT(15)}, + {"MPHY_CORE_OFF_REQ_STS", BIT(16)}, + {"BRK_EV_EN_REQ_STS", BIT(17)}, + {"AUTO_DEMO_EN_REQ_STS", BIT(18)}, + {"ITSS_CLK_SRC_REQ_STS", BIT(19)}, + {"LPC_CLK_SRC_REQ_STS", BIT(20)}, + {"ARC_IDLE_REQ_STS", BIT(21)}, + {"MPHY_SUS_REQ_STS", BIT(22)}, + {"FIA_DEEP_PM_REQ_STS", BIT(23)}, + {"UXD_CONNECTED_REQ_STS", BIT(24)}, + {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25)}, + {"USB2_VNNAON_ACT_REQ_STS", BIT(26)}, + {"PRE_WAKE0_REQ_STS", BIT(27)}, + {"PRE_WAKE1_REQ_STS", BIT(28)}, + {"PRE_WAKE2_EN_REQ_STS", BIT(29)}, + {"WOV_REQ_STS", BIT(30)}, + {"CNVI_V1P05_REQ_STS", BIT(31)}, + {} +}; + +const struct pmc_bit_map mtl_socm_signal_status_map[] =3D { + {"LSX_Wake0_En_STS", BIT(0)}, + {"LSX_Wake0_Pol_STS", BIT(1)}, + {"LSX_Wake1_En_STS", BIT(2)}, + {"LSX_Wake1_Pol_STS", BIT(3)}, + {"LSX_Wake2_En_STS", BIT(4)}, + {"LSX_Wake2_Pol_STS", BIT(5)}, + {"LSX_Wake3_En_STS", BIT(6)}, + {"LSX_Wake3_Pol_STS", BIT(7)}, + {"LSX_Wake4_En_STS", BIT(8)}, + {"LSX_Wake4_Pol_STS", BIT(9)}, + {"LSX_Wake5_En_STS", BIT(10)}, + {"LSX_Wake5_Pol_STS", BIT(11)}, + {"LSX_Wake6_En_STS", BIT(12)}, + {"LSX_Wake6_Pol_STS", BIT(13)}, + {"LSX_Wake7_En_STS", BIT(14)}, + {"LSX_Wake7_Pol_STS", BIT(15)}, + {"LPSS_Wake0_En_STS", BIT(16)}, + {"LPSS_Wake0_Pol_STS", BIT(17)}, + {"LPSS_Wake1_En_STS", BIT(18)}, + {"LPSS_Wake1_Pol_STS", BIT(19)}, + {"Int_Timer_SS_Wake0_En_STS", BIT(20)}, + {"Int_Timer_SS_Wake0_Pol_STS", BIT(21)}, + {"Int_Timer_SS_Wake1_En_STS", BIT(22)}, + {"Int_Timer_SS_Wake1_Pol_STS", BIT(23)}, + {"Int_Timer_SS_Wake2_En_STS", BIT(24)}, + {"Int_Timer_SS_Wake2_Pol_STS", BIT(25)}, + {"Int_Timer_SS_Wake3_En_STS", BIT(26)}, + {"Int_Timer_SS_Wake3_Pol_STS", BIT(27)}, + {"Int_Timer_SS_Wake4_En_STS", BIT(28)}, + {"Int_Timer_SS_Wake4_Pol_STS", BIT(29)}, + {"Int_Timer_SS_Wake5_En_STS", BIT(30)}, + {"Int_Timer_SS_Wake5_Pol_STS", BIT(31)}, + {} +}; + +const struct pmc_bit_map *mtl_socm_lpm_maps[] =3D { + mtl_socm_clocksource_status_map, + mtl_socm_power_gating_status_0_map, + mtl_socm_power_gating_status_1_map, + mtl_socm_power_gating_status_2_map, + mtl_socm_d3_status_0_map, + mtl_socm_d3_status_1_map, + mtl_socm_d3_status_2_map, + mtl_socm_d3_status_3_map, + mtl_socm_vnn_req_status_0_map, + mtl_socm_vnn_req_status_1_map, + mtl_socm_vnn_req_status_2_map, + mtl_socm_vnn_req_status_3_map, + mtl_socm_vnn_misc_status_map, + mtl_socm_signal_status_map, + NULL +}; + +const struct pmc_reg_map mtl_socm_reg_map =3D { + .pfear_sts =3D ext_mtl_socm_pfear_map, .slp_s0_offset =3D CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, .slp_s0_res_counter_step =3D TGL_PMC_SLP_S0_RES_COUNTER_STEP, - .ltr_show_sts =3D adl_ltr_show_map, + .ltr_show_sts =3D mtl_socm_ltr_show_map, .msr_sts =3D msr_map, .ltr_ignore_offset =3D CNP_PMC_LTR_IGNORE_OFFSET, - .regmap_length =3D CNP_PMC_MMIO_REG_LEN, + .regmap_length =3D MTL_SOC_PMC_MMIO_REG_LEN, .ppfear0_offset =3D CNP_PMC_HOST_PPFEAR0A, - .ppfear_buckets =3D ICL_PPFEAR_NUM_ENTRIES, + .ppfear_buckets =3D MTL_SOCM_PPFEAR_NUM_ENTRIES, .pm_cfg_offset =3D CNP_PMC_PM_CFG_OFFSET, .pm_read_disable_bit =3D CNP_PMC_READ_DISABLE_BIT, - .ltr_ignore_max =3D ADL_NUM_IP_IGN_ALLOWED, - .lpm_num_modes =3D ADL_LPM_NUM_MODES, .lpm_num_maps =3D ADL_LPM_NUM_MAPS, + .ltr_ignore_max =3D MTL_SOCM_NUM_IP_IGN_ALLOWED, .lpm_res_counter_step_x2 =3D TGL_PMC_LPM_RES_COUNTER_STEP_X2, .etr3_offset =3D ETR3_OFFSET, .lpm_sts_latch_en_offset =3D MTL_LPM_STATUS_LATCH_EN_OFFSET, .lpm_priority_offset =3D MTL_LPM_PRI_OFFSET, .lpm_en_offset =3D MTL_LPM_EN_OFFSET, .lpm_residency_offset =3D MTL_LPM_RESIDENCY_OFFSET, - .lpm_sts =3D adl_lpm_maps, + .lpm_sts =3D mtl_socm_lpm_maps, .lpm_status_offset =3D MTL_LPM_STATUS_OFFSET, .lpm_live_status_offset =3D MTL_LPM_LIVE_STATUS_OFFSET, }; @@ -87,7 +517,7 @@ static int mtl_resume(struct pmc_dev *pmcdev) =20 void mtl_core_init(struct pmc_dev *pmcdev) { - pmcdev->map =3D &mtl_reg_map; + pmcdev->map =3D &mtl_socm_reg_map; pmcdev->core_configure =3D mtl_core_configure; =20 mtl_d3_fixup(); --=20 2.25.1 From nobody Sat Feb 7 18:21:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31B0FC001B1 for ; Tue, 13 Jun 2023 22:51:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240890AbjFMWvs (ORCPT ); Tue, 13 Jun 2023 18:51:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241135AbjFMWvi (ORCPT ); Tue, 13 Jun 2023 18:51:38 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AAE891732; Tue, 13 Jun 2023 15:51:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686696696; x=1718232696; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=liv5qZIzM+Le5APnzo6PyFKea9u3jjhGd/AsZAO4fxw=; b=Z1KO35VId/eEo659ZvNCWlJ2mTbaxmIE71ckLJVOvpmuUI4ZFZdxWbiJ Q4OLjK2Ssmk5Xzw7o8x1qfUuMPDYbtpj8SB7IkoHeCPxkii2ndwey4Nqc fbJrpeRDjBN4sZ0EK4puKhnUKAo3x8QRalmfEonnBJCL8P0ZayIyg2NQZ lZkW0Cwnodio3CXl1nmSBjtCM9r9mv/14Dlef6DloUutNKBZeXqULPDuL jO21dOaiU/BAp8vNpkqaVuBzdUMKAa0W1ckl6bpUtR2KPeYa9W10f+sNm bZgBLhf3jjatDOUegpj2vLULfiD1bzAFZDjzaH/wiKnH8tPg5ti+1EUqJ w==; X-IronPort-AV: E=McAfee;i="6600,9927,10740"; a="444842178" X-IronPort-AV: E=Sophos;i="6.00,241,1681196400"; d="scan'208";a="444842178" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jun 2023 15:51:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10740"; a="824589634" X-IronPort-AV: E=Sophos;i="6.00,241,1681196400"; d="scan'208";a="824589634" Received: from linux.intel.com ([10.54.29.200]) by fmsmga002.fm.intel.com with ESMTP; 13 Jun 2023 15:51:35 -0700 Received: from rjingar-desk5.amr.corp.intel.com (hciettox-mobl.amr.corp.intel.com [10.212.23.107]) by linux.intel.com (Postfix) with ESMTP id 55DE3580D61; Tue, 13 Jun 2023 15:51:35 -0700 (PDT) From: Rajvi Jingar To: david.e.box@linux.intel.com, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, hdegoede@redhat.com Cc: xi.pardee@intel.com Subject: [PATCH 2/8] platform/x86:intel/pmc: Combine core_init() and core_configure() Date: Tue, 13 Jun 2023 15:53:41 -0700 Message-Id: <20230613225347.2720665-3-rajvi.jingar@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613225347.2720665-1-rajvi.jingar@linux.intel.com> References: <20230613225347.2720665-1-rajvi.jingar@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xi Pardee Combine core_init() and core_configure() functions to have a cleaner setup for platforms. Signed-off-by: Xi Pardee Reviewed-by: Ilpo J=C3=A4rvinen --- drivers/platform/x86/intel/pmc/adl.c | 15 +++++---- drivers/platform/x86/intel/pmc/cnp.c | 15 ++++++++- drivers/platform/x86/intel/pmc/core.c | 47 +++++++++++++++------------ drivers/platform/x86/intel/pmc/core.h | 19 +++++------ drivers/platform/x86/intel/pmc/icl.c | 3 +- drivers/platform/x86/intel/pmc/mtl.c | 26 ++++++++------- drivers/platform/x86/intel/pmc/spt.c | 3 +- drivers/platform/x86/intel/pmc/tgl.c | 15 +++++---- 8 files changed, 85 insertions(+), 58 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/adl.c b/drivers/platform/x86/in= tel/pmc/adl.c index 5cbd40979f2a..f678ce308cc7 100644 --- a/drivers/platform/x86/intel/pmc/adl.c +++ b/drivers/platform/x86/intel/pmc/adl.c @@ -309,17 +309,20 @@ const struct pmc_reg_map adl_reg_map =3D { .lpm_live_status_offset =3D ADL_LPM_LIVE_STATUS_OFFSET, }; =20 -void adl_core_configure(struct pmc_dev *pmcdev) +int adl_core_init(struct pmc_dev *pmcdev) { + int ret; + + pmcdev->map =3D &adl_reg_map; + ret =3D get_primary_reg_base(pmcdev); + if (ret) + return ret; + /* Due to a hardware limitation, the GBE LTR blocks PC10 * when a cable is attached. Tell the PMC to ignore it. */ dev_dbg(&pmcdev->pdev->dev, "ignoring GBE LTR\n"); pmc_core_send_ltr_ignore(pmcdev, 3); -} =20 -void adl_core_init(struct pmc_dev *pmcdev) -{ - pmcdev->map =3D &adl_reg_map; - pmcdev->core_configure =3D adl_core_configure; + return 0; } diff --git a/drivers/platform/x86/intel/pmc/cnp.c b/drivers/platform/x86/in= tel/pmc/cnp.c index 7fb38815c4eb..5fb2d191ce30 100644 --- a/drivers/platform/x86/intel/pmc/cnp.c +++ b/drivers/platform/x86/intel/pmc/cnp.c @@ -204,7 +204,20 @@ const struct pmc_reg_map cnp_reg_map =3D { .etr3_offset =3D ETR3_OFFSET, }; =20 -void cnp_core_init(struct pmc_dev *pmcdev) +int cnp_core_init(struct pmc_dev *pmcdev) { + int ret; + pmcdev->map =3D &cnp_reg_map; + ret =3D get_primary_reg_base(pmcdev); + if (ret) + return ret; + + /* Due to a hardware limitation, the GBE LTR blocks PC10 + * when a cable is attached. Tell the PMC to ignore it. + */ + dev_dbg(&pmcdev->pdev->dev, "ignoring GBE LTR\n"); + pmc_core_send_ltr_ignore(pmcdev, 3); + + return 0; } diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/i= ntel/pmc/core.c index ed91ef9d1cf6..0d4cda7c1833 100644 --- a/drivers/platform/x86/intel/pmc/core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -948,6 +948,25 @@ static void pmc_core_get_low_power_modes(struct platfo= rm_device *pdev) } } =20 +int get_primary_reg_base(struct pmc_dev *pmcdev) +{ + u64 slp_s0_addr; + + if (lpit_read_residency_count_address(&slp_s0_addr)) { + pmcdev->base_addr =3D PMC_BASE_ADDR_DEFAULT; + + if (page_is_ram(PHYS_PFN(pmcdev->base_addr))) + return -ENODEV; + } else { + pmcdev->base_addr =3D slp_s0_addr - pmcdev->map->slp_s0_offset; + } + + pmcdev->regbase =3D ioremap(pmcdev->base_addr, pmcdev->map->regmap_length= ); + if (!pmcdev->regbase) + return -ENOMEM; + return 0; +} + static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev) { debugfs_remove_recursive(pmcdev->dbgfs_dir); @@ -1099,8 +1118,8 @@ static int pmc_core_probe(struct platform_device *pde= v) static bool device_initialized; struct pmc_dev *pmcdev; const struct x86_cpu_id *cpu_id; - void (*core_init)(struct pmc_dev *pmcdev); - u64 slp_s0_addr; + int (*core_init)(struct pmc_dev *pmcdev); + int ret; =20 if (device_initialized) return -ENODEV; @@ -1116,7 +1135,7 @@ static int pmc_core_probe(struct platform_device *pde= v) if (!cpu_id) return -ENODEV; =20 - core_init =3D (void (*)(struct pmc_dev *))cpu_id->driver_data; + core_init =3D (int (*)(struct pmc_dev *))cpu_id->driver_data; =20 /* * Coffee Lake has CPU ID of Kaby Lake and Cannon Lake PCH. So here @@ -1127,26 +1146,12 @@ static int pmc_core_probe(struct platform_device *p= dev) core_init =3D cnp_core_init; =20 mutex_init(&pmcdev->lock); - core_init(pmcdev); - - - if (lpit_read_residency_count_address(&slp_s0_addr)) { - pmcdev->base_addr =3D PMC_BASE_ADDR_DEFAULT; - - if (page_is_ram(PHYS_PFN(pmcdev->base_addr))) - return -ENODEV; - } else { - pmcdev->base_addr =3D slp_s0_addr - pmcdev->map->slp_s0_offset; + ret =3D core_init(pmcdev); + if (ret) { + mutex_destroy(&pmcdev->lock); + return ret; } =20 - pmcdev->regbase =3D ioremap(pmcdev->base_addr, - pmcdev->map->regmap_length); - if (!pmcdev->regbase) - return -ENOMEM; - - if (pmcdev->core_configure) - pmcdev->core_configure(pmcdev); - pmcdev->pmc_xram_read_bit =3D pmc_core_check_read_lock_bit(pmcdev); pmc_core_get_low_power_modes(pdev); pmc_core_do_dmi_quirks(pmcdev); diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/i= ntel/pmc/core.h index 86d38270000a..a672659b8659 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/drivers/platform/x86/intel/pmc/core.h @@ -334,7 +334,6 @@ struct pmc_reg_map { * @num_lpm_modes: Count of enabled modes * @lpm_en_modes: Array of enabled modes from lowest to highest priority * @lpm_req_regs: List of substate requirements - * @core_configure: Function pointer to configure the platform * @resume: Function to perform platform specific resume * * pmc_dev contains info about power management controller device. @@ -353,7 +352,6 @@ struct pmc_dev { int num_lpm_modes; int lpm_en_modes[LPM_MAX_NUM_MODES]; u32 *lpm_req_regs; - void (*core_configure)(struct pmc_dev *pmcdev); int (*resume)(struct pmc_dev *pmcdev); }; =20 @@ -427,15 +425,14 @@ extern void pmc_core_get_tgl_lpm_reqs(struct platform= _device *pdev); extern int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value); =20 int pmc_core_resume_common(struct pmc_dev *pmcdev); -void spt_core_init(struct pmc_dev *pmcdev); -void cnp_core_init(struct pmc_dev *pmcdev); -void icl_core_init(struct pmc_dev *pmcdev); -void tgl_core_init(struct pmc_dev *pmcdev); -void adl_core_init(struct pmc_dev *pmcdev); -void mtl_core_init(struct pmc_dev *pmcdev); -void tgl_core_configure(struct pmc_dev *pmcdev); -void adl_core_configure(struct pmc_dev *pmcdev); -void mtl_core_configure(struct pmc_dev *pmcdev); +int get_primary_reg_base(struct pmc_dev *pmcdev); + +int spt_core_init(struct pmc_dev *pmcdev); +int cnp_core_init(struct pmc_dev *pmcdev); +int icl_core_init(struct pmc_dev *pmcdev); +int tgl_core_init(struct pmc_dev *pmcdev); +int adl_core_init(struct pmc_dev *pmcdev); +int mtl_core_init(struct pmc_dev *pmcdev); =20 #define pmc_for_each_mode(i, mode, pmcdev) \ for (i =3D 0, mode =3D pmcdev->lpm_en_modes[i]; \ diff --git a/drivers/platform/x86/intel/pmc/icl.c b/drivers/platform/x86/in= tel/pmc/icl.c index 2f11b1a6daeb..a671d7e86431 100644 --- a/drivers/platform/x86/intel/pmc/icl.c +++ b/drivers/platform/x86/intel/pmc/icl.c @@ -50,7 +50,8 @@ const struct pmc_reg_map icl_reg_map =3D { .etr3_offset =3D ETR3_OFFSET, }; =20 -void icl_core_init(struct pmc_dev *pmcdev) +int icl_core_init(struct pmc_dev *pmcdev) { pmcdev->map =3D &icl_reg_map; + return get_primary_reg_base(pmcdev); } diff --git a/drivers/platform/x86/intel/pmc/mtl.c b/drivers/platform/x86/in= tel/pmc/mtl.c index cdcf743b5e2c..a2fc96f9ef11 100644 --- a/drivers/platform/x86/intel/pmc/mtl.c +++ b/drivers/platform/x86/intel/pmc/mtl.c @@ -467,15 +467,6 @@ const struct pmc_reg_map mtl_socm_reg_map =3D { .lpm_live_status_offset =3D MTL_LPM_LIVE_STATUS_OFFSET, }; =20 -void mtl_core_configure(struct pmc_dev *pmcdev) -{ - /* Due to a hardware limitation, the GBE LTR blocks PC10 - * when a cable is attached. Tell the PMC to ignore it. - */ - dev_dbg(&pmcdev->pdev->dev, "ignoring GBE LTR\n"); - pmc_core_send_ltr_ignore(pmcdev, 3); -} - #define MTL_GNA_PCI_DEV 0x7e4c #define MTL_IPU_PCI_DEV 0x7d19 #define MTL_VPU_PCI_DEV 0x7d1d @@ -515,12 +506,25 @@ static int mtl_resume(struct pmc_dev *pmcdev) return pmc_core_resume_common(pmcdev); } =20 -void mtl_core_init(struct pmc_dev *pmcdev) +int mtl_core_init(struct pmc_dev *pmcdev) { + int ret; + pmcdev->map =3D &mtl_socm_reg_map; - pmcdev->core_configure =3D mtl_core_configure; =20 mtl_d3_fixup(); =20 pmcdev->resume =3D mtl_resume; + + ret =3D get_primary_reg_base(pmcdev); + if (ret) + return ret; + + /* Due to a hardware limitation, the GBE LTR blocks PC10 + * when a cable is attached. Tell the PMC to ignore it. + */ + dev_dbg(&pmcdev->pdev->dev, "ignoring GBE LTR\n"); + pmc_core_send_ltr_ignore(pmcdev, 3); + + return 0; } diff --git a/drivers/platform/x86/intel/pmc/spt.c b/drivers/platform/x86/in= tel/pmc/spt.c index e16982236778..f34015692bb8 100644 --- a/drivers/platform/x86/intel/pmc/spt.c +++ b/drivers/platform/x86/intel/pmc/spt.c @@ -134,7 +134,8 @@ const struct pmc_reg_map spt_reg_map =3D { .pm_vric1_offset =3D SPT_PMC_VRIC1_OFFSET, }; =20 -void spt_core_init(struct pmc_dev *pmcdev) +int spt_core_init(struct pmc_dev *pmcdev) { pmcdev->map =3D &spt_reg_map; + return get_primary_reg_base(pmcdev); } diff --git a/drivers/platform/x86/intel/pmc/tgl.c b/drivers/platform/x86/in= tel/pmc/tgl.c index c245ada849d0..90807bd947ed 100644 --- a/drivers/platform/x86/intel/pmc/tgl.c +++ b/drivers/platform/x86/intel/pmc/tgl.c @@ -252,18 +252,21 @@ void pmc_core_get_tgl_lpm_reqs(struct platform_device= *pdev) ACPI_FREE(out_obj); } =20 -void tgl_core_configure(struct pmc_dev *pmcdev) +int tgl_core_init(struct pmc_dev *pmcdev) { + int ret; + + pmcdev->map =3D &tgl_reg_map; + ret =3D get_primary_reg_base(pmcdev); + if (ret) + return ret; + pmc_core_get_tgl_lpm_reqs(pmcdev->pdev); /* Due to a hardware limitation, the GBE LTR blocks PC10 * when a cable is attached. Tell the PMC to ignore it. */ dev_dbg(&pmcdev->pdev->dev, "ignoring GBE LTR\n"); pmc_core_send_ltr_ignore(pmcdev, 3); -} =20 -void tgl_core_init(struct pmc_dev *pmcdev) -{ - pmcdev->map =3D &tgl_reg_map; - pmcdev->core_configure =3D tgl_core_configure; + return 0; } --=20 2.25.1 From nobody Sat Feb 7 18:21:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D2B2EB64D7 for ; Tue, 13 Jun 2023 22:52:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241381AbjFMWwE (ORCPT ); Tue, 13 Jun 2023 18:52:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240270AbjFMWvk (ORCPT ); Tue, 13 Jun 2023 18:51:40 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E2A01BE9; Tue, 13 Jun 2023 15:51:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686696697; x=1718232697; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=X+teYYfIYJhkibDp86kPy0XYQnCiN9+yD7YyNXjAa+o=; b=P8cO8mLYmn8SieJgiFQlM1pRM8Bnxk5yEDO3mtsmJuapWNZ7GKVUjCFl WRxRnCRepUyC52B4hiD+5wVvCPDFBPGVsOI/E1mGfxAg7FyE1714Px1LZ hRySH73OPDyv/KoTz80WSCQ0/ni84AqjR76zquC06P8lrqsIKn8lPxifu JLDFmAnaDzkZB6m4MCZSMG7iqZdqny8oJbsldwErIjEjGU7GpWBIY+Tgj U8wTRppQYIzTWzYZA/8EuL1qxuWDR3Zr5+IBFD2ApLT7X9hOVO+OblwHN SAC7vzdsZil2CZ1nK+eXLWLDscwfl1WFVEJO+CBT45p+QCntZKedqS+ao Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10740"; a="444842184" X-IronPort-AV: E=Sophos;i="6.00,241,1681196400"; d="scan'208";a="444842184" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jun 2023 15:51:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10740"; a="824589638" X-IronPort-AV: E=Sophos;i="6.00,241,1681196400"; d="scan'208";a="824589638" Received: from linux.intel.com ([10.54.29.200]) by fmsmga002.fm.intel.com with ESMTP; 13 Jun 2023 15:51:36 -0700 Received: from rjingar-desk5.amr.corp.intel.com (hciettox-mobl.amr.corp.intel.com [10.212.23.107]) by linux.intel.com (Postfix) with ESMTP id E5555580BF8; Tue, 13 Jun 2023 15:51:35 -0700 (PDT) From: Rajvi Jingar To: david.e.box@linux.intel.com, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, hdegoede@redhat.com Cc: xi.pardee@intel.com Subject: [PATCH 3/8] platform/x86:intel/pmc: Add support to handle multiple PMCs Date: Tue, 13 Jun 2023 15:53:42 -0700 Message-Id: <20230613225347.2720665-4-rajvi.jingar@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613225347.2720665-1-rajvi.jingar@linux.intel.com> References: <20230613225347.2720665-1-rajvi.jingar@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xi Pardee To support platforms with multiple PMCs, add a PMC device structure to support each PMC instance. Signed-off-by: Xi Pardee Reviewed-by: Ilpo J=C3=A4rvinen --- drivers/platform/x86/intel/pmc/adl.c | 5 +- drivers/platform/x86/intel/pmc/cnp.c | 5 +- drivers/platform/x86/intel/pmc/core.c | 272 ++++++++++++++------------ drivers/platform/x86/intel/pmc/core.h | 37 +++- drivers/platform/x86/intel/pmc/icl.c | 6 +- drivers/platform/x86/intel/pmc/mtl.c | 5 +- drivers/platform/x86/intel/pmc/spt.c | 6 +- drivers/platform/x86/intel/pmc/tgl.c | 10 +- 8 files changed, 205 insertions(+), 141 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/adl.c b/drivers/platform/x86/in= tel/pmc/adl.c index f678ce308cc7..5006008e01be 100644 --- a/drivers/platform/x86/intel/pmc/adl.c +++ b/drivers/platform/x86/intel/pmc/adl.c @@ -311,10 +311,11 @@ const struct pmc_reg_map adl_reg_map =3D { =20 int adl_core_init(struct pmc_dev *pmcdev) { + struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; int ret; =20 - pmcdev->map =3D &adl_reg_map; - ret =3D get_primary_reg_base(pmcdev); + pmc->map =3D &adl_reg_map; + ret =3D get_primary_reg_base(pmc); if (ret) return ret; =20 diff --git a/drivers/platform/x86/intel/pmc/cnp.c b/drivers/platform/x86/in= tel/pmc/cnp.c index 5fb2d191ce30..420aaa1d7c76 100644 --- a/drivers/platform/x86/intel/pmc/cnp.c +++ b/drivers/platform/x86/intel/pmc/cnp.c @@ -206,10 +206,11 @@ const struct pmc_reg_map cnp_reg_map =3D { =20 int cnp_core_init(struct pmc_dev *pmcdev) { + struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; int ret; =20 - pmcdev->map =3D &cnp_reg_map; - ret =3D get_primary_reg_base(pmcdev); + pmc->map =3D &cnp_reg_map; + ret =3D get_primary_reg_base(pmc); if (ret) return ret; =20 diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/i= ntel/pmc/core.c index 0d4cda7c1833..8d774461dd29 100644 --- a/drivers/platform/x86/intel/pmc/core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -53,18 +53,18 @@ const struct pmc_bit_map msr_map[] =3D { {} }; =20 -static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset) +static inline u32 pmc_core_reg_read(struct pmc *pmc, int reg_offset) { - return readl(pmcdev->regbase + reg_offset); + return readl(pmc->regbase + reg_offset); } =20 -static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int reg_offs= et, +static inline void pmc_core_reg_write(struct pmc *pmc, int reg_offset, u32 val) { - writel(val, pmcdev->regbase + reg_offset); + writel(val, pmc->regbase + reg_offset); } =20 -static inline u64 pmc_core_adjust_slp_s0_step(struct pmc_dev *pmcdev, u32 = value) +static inline u64 pmc_core_adjust_slp_s0_step(struct pmc *pmc, u32 value) { /* * ADL PCH does not have the SLP_S0 counter and LPM Residency counters are @@ -72,17 +72,18 @@ static inline u64 pmc_core_adjust_slp_s0_step(struct pm= c_dev *pmcdev, u32 value) * programs have the legacy SLP_S0 residency counter that is using the 122 * usec tick. */ - const int lpm_adj_x2 =3D pmcdev->map->lpm_res_counter_step_x2; + const int lpm_adj_x2 =3D pmc->map->lpm_res_counter_step_x2; =20 - if (pmcdev->map =3D=3D &adl_reg_map) + if (pmc->map =3D=3D &adl_reg_map) return (u64)value * GET_X2_COUNTER((u64)lpm_adj_x2); else - return (u64)value * pmcdev->map->slp_s0_res_counter_step; + return (u64)value * pmc->map->slp_s0_res_counter_step; } =20 static int set_etr3(struct pmc_dev *pmcdev) { - const struct pmc_reg_map *map =3D pmcdev->map; + struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; + const struct pmc_reg_map *map =3D pmc->map; u32 reg; int err; =20 @@ -92,7 +93,7 @@ static int set_etr3(struct pmc_dev *pmcdev) mutex_lock(&pmcdev->lock); =20 /* check if CF9 is locked */ - reg =3D pmc_core_reg_read(pmcdev, map->etr3_offset); + reg =3D pmc_core_reg_read(pmc, map->etr3_offset); if (reg & ETR3_CF9LOCK) { err =3D -EACCES; goto out_unlock; @@ -100,9 +101,9 @@ static int set_etr3(struct pmc_dev *pmcdev) =20 /* write CF9 global reset bit */ reg |=3D ETR3_CF9GR; - pmc_core_reg_write(pmcdev, map->etr3_offset, reg); + pmc_core_reg_write(pmc, map->etr3_offset, reg); =20 - reg =3D pmc_core_reg_read(pmcdev, map->etr3_offset); + reg =3D pmc_core_reg_read(pmc, map->etr3_offset); if (!(reg & ETR3_CF9GR)) { err =3D -EIO; goto out_unlock; @@ -120,11 +121,12 @@ static umode_t etr3_is_visible(struct kobject *kobj, { struct device *dev =3D kobj_to_dev(kobj); struct pmc_dev *pmcdev =3D dev_get_drvdata(dev); - const struct pmc_reg_map *map =3D pmcdev->map; + struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; + const struct pmc_reg_map *map =3D pmc->map; u32 reg; =20 mutex_lock(&pmcdev->lock); - reg =3D pmc_core_reg_read(pmcdev, map->etr3_offset); + reg =3D pmc_core_reg_read(pmc, map->etr3_offset); mutex_unlock(&pmcdev->lock); =20 return reg & ETR3_CF9LOCK ? attr->mode & (SYSFS_PREALLOC | 0444) : attr->= mode; @@ -134,7 +136,8 @@ static ssize_t etr3_show(struct device *dev, struct device_attribute *attr, char *buf) { struct pmc_dev *pmcdev =3D dev_get_drvdata(dev); - const struct pmc_reg_map *map =3D pmcdev->map; + struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; + const struct pmc_reg_map *map =3D pmc->map; u32 reg; =20 if (!map->etr3_offset) @@ -142,7 +145,7 @@ static ssize_t etr3_show(struct device *dev, =20 mutex_lock(&pmcdev->lock); =20 - reg =3D pmc_core_reg_read(pmcdev, map->etr3_offset); + reg =3D pmc_core_reg_read(pmc, map->etr3_offset); reg &=3D ETR3_CF9GR | ETR3_CF9LOCK; =20 mutex_unlock(&pmcdev->lock); @@ -191,37 +194,37 @@ static const struct attribute_group *pmc_dev_groups[]= =3D { =20 static int pmc_core_dev_state_get(void *data, u64 *val) { - struct pmc_dev *pmcdev =3D data; - const struct pmc_reg_map *map =3D pmcdev->map; + struct pmc *pmc =3D data; + const struct pmc_reg_map *map =3D pmc->map; u32 value; =20 - value =3D pmc_core_reg_read(pmcdev, map->slp_s0_offset); - *val =3D pmc_core_adjust_slp_s0_step(pmcdev, value); + value =3D pmc_core_reg_read(pmc, map->slp_s0_offset); + *val =3D pmc_core_adjust_slp_s0_step(pmc, value); =20 return 0; } =20 DEFINE_DEBUGFS_ATTRIBUTE(pmc_core_dev_state, pmc_core_dev_state_get, NULL,= "%llu\n"); =20 -static int pmc_core_check_read_lock_bit(struct pmc_dev *pmcdev) +static int pmc_core_check_read_lock_bit(struct pmc *pmc) { u32 value; =20 - value =3D pmc_core_reg_read(pmcdev, pmcdev->map->pm_cfg_offset); - return value & BIT(pmcdev->map->pm_read_disable_bit); + value =3D pmc_core_reg_read(pmc, pmc->map->pm_cfg_offset); + return value & BIT(pmc->map->pm_read_disable_bit); } =20 -static void pmc_core_slps0_display(struct pmc_dev *pmcdev, struct device *= dev, +static void pmc_core_slps0_display(struct pmc *pmc, struct device *dev, struct seq_file *s) { - const struct pmc_bit_map **maps =3D pmcdev->map->slps0_dbg_maps; + const struct pmc_bit_map **maps =3D pmc->map->slps0_dbg_maps; const struct pmc_bit_map *map; - int offset =3D pmcdev->map->slps0_dbg_offset; + int offset =3D pmc->map->slps0_dbg_offset; u32 data; =20 while (*maps) { map =3D *maps; - data =3D pmc_core_reg_read(pmcdev, offset); + data =3D pmc_core_reg_read(pmc, offset); offset +=3D 4; while (map->name) { if (dev) @@ -248,7 +251,7 @@ static int pmc_core_lpm_get_arr_size(const struct pmc_b= it_map **maps) return idx; } =20 -static void pmc_core_lpm_display(struct pmc_dev *pmcdev, struct device *de= v, +static void pmc_core_lpm_display(struct pmc *pmc, struct device *dev, struct seq_file *s, u32 offset, const char *str, const struct pmc_bit_map **maps) @@ -262,7 +265,7 @@ static void pmc_core_lpm_display(struct pmc_dev *pmcdev= , struct device *dev, return; =20 for (index =3D 0; index < arr_size; index++) { - lpm_regs[index] =3D pmc_core_reg_read(pmcdev, offset); + lpm_regs[index] =3D pmc_core_reg_read(pmc, offset); offset +=3D 4; } =20 @@ -291,9 +294,9 @@ static void pmc_core_lpm_display(struct pmc_dev *pmcdev= , struct device *dev, =20 static bool slps0_dbg_latch; =20 -static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset) +static inline u8 pmc_core_reg_read_byte(struct pmc *pmc, int offset) { - return readb(pmcdev->regbase + offset); + return readb(pmc->regbase + offset); } =20 static void pmc_core_display_map(struct seq_file *s, int index, int idx, i= nt ip, @@ -307,19 +310,20 @@ static void pmc_core_display_map(struct seq_file *s, = int index, int idx, int ip, static int pmc_core_ppfear_show(struct seq_file *s, void *unused) { struct pmc_dev *pmcdev =3D s->private; - const struct pmc_bit_map **maps =3D pmcdev->map->pfear_sts; + struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; + const struct pmc_bit_map **maps =3D pmc->map->pfear_sts; u8 pf_regs[PPFEAR_MAX_NUM_ENTRIES]; int index, iter, idx, ip =3D 0; =20 - iter =3D pmcdev->map->ppfear0_offset; + iter =3D pmc->map->ppfear0_offset; =20 - for (index =3D 0; index < pmcdev->map->ppfear_buckets && + for (index =3D 0; index < pmc->map->ppfear_buckets && index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++) - pf_regs[index] =3D pmc_core_reg_read_byte(pmcdev, iter); + pf_regs[index] =3D pmc_core_reg_read_byte(pmc, iter); =20 for (idx =3D 0; maps[idx]; idx++) { for (index =3D 0; maps[idx][index].name && - index < pmcdev->map->ppfear_buckets * 8; ip++, index++) + index < pmc->map->ppfear_buckets * 8; ip++, index++) pmc_core_display_map(s, index, idx, ip, pf_regs[index / 8], maps); } @@ -329,37 +333,38 @@ static int pmc_core_ppfear_show(struct seq_file *s, v= oid *unused) DEFINE_SHOW_ATTRIBUTE(pmc_core_ppfear); =20 /* This function should return link status, 0 means ready */ -static int pmc_core_mtpmc_link_status(struct pmc_dev *pmcdev) +static int pmc_core_mtpmc_link_status(struct pmc *pmc) { u32 value; =20 - value =3D pmc_core_reg_read(pmcdev, SPT_PMC_PM_STS_OFFSET); + value =3D pmc_core_reg_read(pmc, SPT_PMC_PM_STS_OFFSET); return value & BIT(SPT_PMC_MSG_FULL_STS_BIT); } =20 -static int pmc_core_send_msg(struct pmc_dev *pmcdev, u32 *addr_xram) +static int pmc_core_send_msg(struct pmc *pmc, u32 *addr_xram) { u32 dest; int timeout; =20 for (timeout =3D NUM_RETRIES; timeout > 0; timeout--) { - if (pmc_core_mtpmc_link_status(pmcdev) =3D=3D 0) + if (pmc_core_mtpmc_link_status(pmc) =3D=3D 0) break; msleep(5); } =20 - if (timeout <=3D 0 && pmc_core_mtpmc_link_status(pmcdev)) + if (timeout <=3D 0 && pmc_core_mtpmc_link_status(pmc)) return -EBUSY; =20 dest =3D (*addr_xram & MTPMC_MASK) | (1U << 1); - pmc_core_reg_write(pmcdev, SPT_PMC_MTPMC_OFFSET, dest); + pmc_core_reg_write(pmc, SPT_PMC_MTPMC_OFFSET, dest); return 0; } =20 static int pmc_core_mphy_pg_show(struct seq_file *s, void *unused) { struct pmc_dev *pmcdev =3D s->private; - const struct pmc_bit_map *map =3D pmcdev->map->mphy_sts; + struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; + const struct pmc_bit_map *map =3D pmc->map->mphy_sts; u32 mphy_core_reg_low, mphy_core_reg_high; u32 val_low, val_high; int index, err =3D 0; @@ -374,21 +379,21 @@ static int pmc_core_mphy_pg_show(struct seq_file *s, = void *unused) =20 mutex_lock(&pmcdev->lock); =20 - if (pmc_core_send_msg(pmcdev, &mphy_core_reg_low) !=3D 0) { + if (pmc_core_send_msg(pmc, &mphy_core_reg_low) !=3D 0) { err =3D -EBUSY; goto out_unlock; } =20 msleep(10); - val_low =3D pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET); + val_low =3D pmc_core_reg_read(pmc, SPT_PMC_MFPMC_OFFSET); =20 - if (pmc_core_send_msg(pmcdev, &mphy_core_reg_high) !=3D 0) { + if (pmc_core_send_msg(pmc, &mphy_core_reg_high) !=3D 0) { err =3D -EBUSY; goto out_unlock; } =20 msleep(10); - val_high =3D pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET); + val_high =3D pmc_core_reg_read(pmc, SPT_PMC_MFPMC_OFFSET); =20 for (index =3D 0; index < 8 && map[index].name; index++) { seq_printf(s, "%-32s\tState: %s\n", @@ -413,7 +418,8 @@ DEFINE_SHOW_ATTRIBUTE(pmc_core_mphy_pg); static int pmc_core_pll_show(struct seq_file *s, void *unused) { struct pmc_dev *pmcdev =3D s->private; - const struct pmc_bit_map *map =3D pmcdev->map->pll_sts; + struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; + const struct pmc_bit_map *map =3D pmc->map->pll_sts; u32 mphy_common_reg, val; int index, err =3D 0; =20 @@ -425,14 +431,14 @@ static int pmc_core_pll_show(struct seq_file *s, void= *unused) mphy_common_reg =3D (SPT_PMC_MPHY_COM_STS_0 << 16); mutex_lock(&pmcdev->lock); =20 - if (pmc_core_send_msg(pmcdev, &mphy_common_reg) !=3D 0) { + if (pmc_core_send_msg(pmc, &mphy_common_reg) !=3D 0) { err =3D -EBUSY; goto out_unlock; } =20 /* Observed PMC HW response latency for MTPMC-MFPMC is ~10 ms */ msleep(10); - val =3D pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET); + val =3D pmc_core_reg_read(pmc, SPT_PMC_MFPMC_OFFSET); =20 for (index =3D 0; map[index].name ; index++) { seq_printf(s, "%-32s\tState: %s\n", @@ -448,7 +454,8 @@ DEFINE_SHOW_ATTRIBUTE(pmc_core_pll); =20 int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value) { - const struct pmc_reg_map *map =3D pmcdev->map; + struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; + const struct pmc_reg_map *map =3D pmc->map; u32 reg; int err =3D 0; =20 @@ -459,9 +466,9 @@ int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u3= 2 value) goto out_unlock; } =20 - reg =3D pmc_core_reg_read(pmcdev, map->ltr_ignore_offset); + reg =3D pmc_core_reg_read(pmc, map->ltr_ignore_offset); reg |=3D BIT(value); - pmc_core_reg_write(pmcdev, map->ltr_ignore_offset, reg); + pmc_core_reg_write(pmc, map->ltr_ignore_offset, reg); =20 out_unlock: mutex_unlock(&pmcdev->lock); @@ -509,7 +516,8 @@ static const struct file_operations pmc_core_ltr_ignore= _ops =3D { =20 static void pmc_core_slps0_dbg_latch(struct pmc_dev *pmcdev, bool reset) { - const struct pmc_reg_map *map =3D pmcdev->map; + struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; + const struct pmc_reg_map *map =3D pmc->map; u32 fd; =20 mutex_lock(&pmcdev->lock); @@ -517,12 +525,12 @@ static void pmc_core_slps0_dbg_latch(struct pmc_dev *= pmcdev, bool reset) if (!reset && !slps0_dbg_latch) goto out_unlock; =20 - fd =3D pmc_core_reg_read(pmcdev, map->slps0_dbg_offset); + fd =3D pmc_core_reg_read(pmc, map->slps0_dbg_offset); if (reset) fd &=3D ~CNP_PMC_LATCH_SLPS0_EVENTS; else fd |=3D CNP_PMC_LATCH_SLPS0_EVENTS; - pmc_core_reg_write(pmcdev, map->slps0_dbg_offset, fd); + pmc_core_reg_write(pmc, map->slps0_dbg_offset, fd); =20 slps0_dbg_latch =3D false; =20 @@ -535,7 +543,7 @@ static int pmc_core_slps0_dbg_show(struct seq_file *s, = void *unused) struct pmc_dev *pmcdev =3D s->private; =20 pmc_core_slps0_dbg_latch(pmcdev, false); - pmc_core_slps0_display(pmcdev, NULL, s); + pmc_core_slps0_display(pmcdev->pmcs[PMC_IDX_MAIN], NULL, s); pmc_core_slps0_dbg_latch(pmcdev, true); =20 return 0; @@ -578,8 +586,8 @@ static u32 convert_ltr_scale(u32 val) =20 static int pmc_core_ltr_show(struct seq_file *s, void *unused) { - struct pmc_dev *pmcdev =3D s->private; - const struct pmc_bit_map *map =3D pmcdev->map->ltr_show_sts; + struct pmc *pmc =3D s->private; + const struct pmc_bit_map *map =3D pmc->map->ltr_show_sts; u64 decoded_snoop_ltr, decoded_non_snoop_ltr; u32 ltr_raw_data, scale, val; u16 snoop_ltr, nonsnoop_ltr; @@ -587,7 +595,7 @@ static int pmc_core_ltr_show(struct seq_file *s, void *= unused) =20 for (index =3D 0; map[index].name ; index++) { decoded_snoop_ltr =3D decoded_non_snoop_ltr =3D 0; - ltr_raw_data =3D pmc_core_reg_read(pmcdev, + ltr_raw_data =3D pmc_core_reg_read(pmc, map[index].bit_mask); snoop_ltr =3D ltr_raw_data & ~MTPMC_MASK; nonsnoop_ltr =3D (ltr_raw_data >> 0x10) & ~MTPMC_MASK; @@ -613,10 +621,10 @@ static int pmc_core_ltr_show(struct seq_file *s, void= *unused) } DEFINE_SHOW_ATTRIBUTE(pmc_core_ltr); =20 -static inline u64 adjust_lpm_residency(struct pmc_dev *pmcdev, u32 offset, +static inline u64 adjust_lpm_residency(struct pmc *pmc, u32 offset, const int lpm_adj_x2) { - u64 lpm_res =3D pmc_core_reg_read(pmcdev, offset); + u64 lpm_res =3D pmc_core_reg_read(pmc, offset); =20 return GET_X2_COUNTER((u64)lpm_adj_x2 * lpm_res); } @@ -624,15 +632,16 @@ static inline u64 adjust_lpm_residency(struct pmc_dev= *pmcdev, u32 offset, static int pmc_core_substate_res_show(struct seq_file *s, void *unused) { struct pmc_dev *pmcdev =3D s->private; - const int lpm_adj_x2 =3D pmcdev->map->lpm_res_counter_step_x2; - u32 offset =3D pmcdev->map->lpm_residency_offset; + struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; + const int lpm_adj_x2 =3D pmc->map->lpm_res_counter_step_x2; + u32 offset =3D pmc->map->lpm_residency_offset; int i, mode; =20 seq_printf(s, "%-10s %-15s\n", "Substate", "Residency"); =20 pmc_for_each_mode(i, mode, pmcdev) { seq_printf(s, "%-10s %-15llu\n", pmc_lpm_modes[mode], - adjust_lpm_residency(pmcdev, offset + (4 * mode), lpm_adj_x2)); + adjust_lpm_residency(pmc, offset + (4 * mode), lpm_adj_x2)); } =20 return 0; @@ -642,10 +651,11 @@ DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_res); static int pmc_core_substate_sts_regs_show(struct seq_file *s, void *unuse= d) { struct pmc_dev *pmcdev =3D s->private; - const struct pmc_bit_map **maps =3D pmcdev->map->lpm_sts; - u32 offset =3D pmcdev->map->lpm_status_offset; + struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; + const struct pmc_bit_map **maps =3D pmc->map->lpm_sts; + u32 offset =3D pmc->map->lpm_status_offset; =20 - pmc_core_lpm_display(pmcdev, NULL, s, offset, "STATUS", maps); + pmc_core_lpm_display(pmc, NULL, s, offset, "STATUS", maps); =20 return 0; } @@ -654,10 +664,11 @@ DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_sts_regs); static int pmc_core_substate_l_sts_regs_show(struct seq_file *s, void *unu= sed) { struct pmc_dev *pmcdev =3D s->private; - const struct pmc_bit_map **maps =3D pmcdev->map->lpm_sts; - u32 offset =3D pmcdev->map->lpm_live_status_offset; + struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; + const struct pmc_bit_map **maps =3D pmc->map->lpm_sts; + u32 offset =3D pmc->map->lpm_live_status_offset; =20 - pmc_core_lpm_display(pmcdev, NULL, s, offset, "LIVE_STATUS", maps); + pmc_core_lpm_display(pmc, NULL, s, offset, "LIVE_STATUS", maps); =20 return 0; } @@ -678,11 +689,12 @@ static void pmc_core_substate_req_header_show(struct = seq_file *s) static int pmc_core_substate_req_regs_show(struct seq_file *s, void *unuse= d) { struct pmc_dev *pmcdev =3D s->private; - const struct pmc_bit_map **maps =3D pmcdev->map->lpm_sts; + struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; + const struct pmc_bit_map **maps =3D pmc->map->lpm_sts; const struct pmc_bit_map *map; - const int num_maps =3D pmcdev->map->lpm_num_maps; - u32 sts_offset =3D pmcdev->map->lpm_status_offset; - u32 *lpm_req_regs =3D pmcdev->lpm_req_regs; + const int num_maps =3D pmc->map->lpm_num_maps; + u32 sts_offset =3D pmc->map->lpm_status_offset; + u32 *lpm_req_regs =3D pmc->lpm_req_regs; int mp; =20 /* Display the header */ @@ -703,7 +715,7 @@ static int pmc_core_substate_req_regs_show(struct seq_f= ile *s, void *unused) req_mask |=3D lpm_req_regs[mp + (mode * num_maps)]; =20 /* Get the last latched status for this map */ - lpm_status =3D pmc_core_reg_read(pmcdev, sts_offset + (mp * 4)); + lpm_status =3D pmc_core_reg_read(pmc, sts_offset + (mp * 4)); =20 /* Loop over elements in this map */ map =3D maps[mp]; @@ -746,11 +758,12 @@ DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_req_regs); static int pmc_core_lpm_latch_mode_show(struct seq_file *s, void *unused) { struct pmc_dev *pmcdev =3D s->private; + struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; bool c10; u32 reg; int idx, mode; =20 - reg =3D pmc_core_reg_read(pmcdev, pmcdev->map->lpm_sts_latch_en_offset); + reg =3D pmc_core_reg_read(pmc, pmc->map->lpm_sts_latch_en_offset); if (reg & LPM_STS_LATCH_MODE) { seq_puts(s, "c10"); c10 =3D false; @@ -777,6 +790,7 @@ static ssize_t pmc_core_lpm_latch_mode_write(struct fil= e *file, { struct seq_file *s =3D file->private_data; struct pmc_dev *pmcdev =3D s->private; + struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; bool clear =3D false, c10 =3D false; unsigned char buf[8]; int idx, m, mode; @@ -813,9 +827,9 @@ static ssize_t pmc_core_lpm_latch_mode_write(struct fil= e *file, if (clear) { mutex_lock(&pmcdev->lock); =20 - reg =3D pmc_core_reg_read(pmcdev, pmcdev->map->etr3_offset); + reg =3D pmc_core_reg_read(pmc, pmc->map->etr3_offset); reg |=3D ETR3_CLEAR_LPM_EVENTS; - pmc_core_reg_write(pmcdev, pmcdev->map->etr3_offset, reg); + pmc_core_reg_write(pmc, pmc->map->etr3_offset, reg); =20 mutex_unlock(&pmcdev->lock); =20 @@ -825,9 +839,9 @@ static ssize_t pmc_core_lpm_latch_mode_write(struct fil= e *file, if (c10) { mutex_lock(&pmcdev->lock); =20 - reg =3D pmc_core_reg_read(pmcdev, pmcdev->map->lpm_sts_latch_en_offset); + reg =3D pmc_core_reg_read(pmc, pmc->map->lpm_sts_latch_en_offset); reg &=3D ~LPM_STS_LATCH_MODE; - pmc_core_reg_write(pmcdev, pmcdev->map->lpm_sts_latch_en_offset, reg); + pmc_core_reg_write(pmc, pmc->map->lpm_sts_latch_en_offset, reg); =20 mutex_unlock(&pmcdev->lock); =20 @@ -840,7 +854,7 @@ static ssize_t pmc_core_lpm_latch_mode_write(struct fil= e *file, */ reg =3D LPM_STS_LATCH_MODE | BIT(mode); mutex_lock(&pmcdev->lock); - pmc_core_reg_write(pmcdev, pmcdev->map->lpm_sts_latch_en_offset, reg); + pmc_core_reg_write(pmc, pmc->map->lpm_sts_latch_en_offset, reg); mutex_unlock(&pmcdev->lock); =20 return count; @@ -849,8 +863,8 @@ DEFINE_PMC_CORE_ATTR_WRITE(pmc_core_lpm_latch_mode); =20 static int pmc_core_pkgc_show(struct seq_file *s, void *unused) { - struct pmc_dev *pmcdev =3D s->private; - const struct pmc_bit_map *map =3D pmcdev->map->msr_sts; + struct pmc *pmc =3D s->private; + const struct pmc_bit_map *map =3D pmc->map->msr_sts; u64 pcstate_count; int index; =20 @@ -901,6 +915,7 @@ static bool pmc_core_pri_verify(u32 lpm_pri, u8 *mode_o= rder) static void pmc_core_get_low_power_modes(struct platform_device *pdev) { struct pmc_dev *pmcdev =3D platform_get_drvdata(pdev); + struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; u8 pri_order[LPM_MAX_NUM_MODES] =3D LPM_DEFAULT_PRI; u8 mode_order[LPM_MAX_NUM_MODES]; u32 lpm_pri; @@ -908,10 +923,10 @@ static void pmc_core_get_low_power_modes(struct platf= orm_device *pdev) int mode, i, p; =20 /* Use LPM Maps to indicate support for substates */ - if (!pmcdev->map->lpm_num_maps) + if (!pmc->map->lpm_num_maps) return; =20 - lpm_en =3D pmc_core_reg_read(pmcdev, pmcdev->map->lpm_en_offset); + lpm_en =3D pmc_core_reg_read(pmc, pmc->map->lpm_en_offset); /* For MTL, BIT 31 is not an lpm mode but a enable bit. * Lower byte is enough to cover the number of lpm modes for all * platforms and hence mask the upper 3 bytes. @@ -919,7 +934,7 @@ static void pmc_core_get_low_power_modes(struct platfor= m_device *pdev) pmcdev->num_lpm_modes =3D hweight32(lpm_en & 0xFF); =20 /* Read 32 bit LPM_PRI register */ - lpm_pri =3D pmc_core_reg_read(pmcdev, pmcdev->map->lpm_priority_offset); + lpm_pri =3D pmc_core_reg_read(pmc, pmc->map->lpm_priority_offset); =20 =20 /* @@ -948,21 +963,21 @@ static void pmc_core_get_low_power_modes(struct platf= orm_device *pdev) } } =20 -int get_primary_reg_base(struct pmc_dev *pmcdev) +int get_primary_reg_base(struct pmc *pmc) { u64 slp_s0_addr; =20 if (lpit_read_residency_count_address(&slp_s0_addr)) { - pmcdev->base_addr =3D PMC_BASE_ADDR_DEFAULT; + pmc->base_addr =3D PMC_BASE_ADDR_DEFAULT; =20 - if (page_is_ram(PHYS_PFN(pmcdev->base_addr))) + if (page_is_ram(PHYS_PFN(pmc->base_addr))) return -ENODEV; } else { - pmcdev->base_addr =3D slp_s0_addr - pmcdev->map->slp_s0_offset; + pmc->base_addr =3D slp_s0_addr - pmc->map->slp_s0_offset; } =20 - pmcdev->regbase =3D ioremap(pmcdev->base_addr, pmcdev->map->regmap_length= ); - if (!pmcdev->regbase) + pmc->regbase =3D ioremap(pmc->base_addr, pmc->map->regmap_length); + if (!pmc->regbase) return -ENOMEM; return 0; } @@ -974,36 +989,37 @@ static void pmc_core_dbgfs_unregister(struct pmc_dev = *pmcdev) =20 static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev) { + struct pmc *primary_pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; struct dentry *dir; =20 dir =3D debugfs_create_dir("pmc_core", NULL); pmcdev->dbgfs_dir =3D dir; =20 - debugfs_create_file("slp_s0_residency_usec", 0444, dir, pmcdev, + debugfs_create_file("slp_s0_residency_usec", 0444, dir, primary_pmc, &pmc_core_dev_state); =20 - if (pmcdev->map->pfear_sts) + if (primary_pmc->map->pfear_sts) debugfs_create_file("pch_ip_power_gating_status", 0444, dir, pmcdev, &pmc_core_ppfear_fops); =20 debugfs_create_file("ltr_ignore", 0644, dir, pmcdev, &pmc_core_ltr_ignore_ops); =20 - debugfs_create_file("ltr_show", 0444, dir, pmcdev, &pmc_core_ltr_fops); + debugfs_create_file("ltr_show", 0444, dir, primary_pmc, &pmc_core_ltr_fop= s); =20 - debugfs_create_file("package_cstate_show", 0444, dir, pmcdev, + debugfs_create_file("package_cstate_show", 0444, dir, primary_pmc, &pmc_core_pkgc_fops); =20 - if (pmcdev->map->pll_sts) + if (primary_pmc->map->pll_sts) debugfs_create_file("pll_status", 0444, dir, pmcdev, &pmc_core_pll_fops); =20 - if (pmcdev->map->mphy_sts) + if (primary_pmc->map->mphy_sts) debugfs_create_file("mphy_core_lanes_power_gating_status", 0444, dir, pmcdev, &pmc_core_mphy_pg_fops); =20 - if (pmcdev->map->slps0_dbg_maps) { + if (primary_pmc->map->slps0_dbg_maps) { debugfs_create_file("slp_s0_debug_status", 0444, dir, pmcdev, &pmc_core_slps0_dbg_fops); @@ -1012,13 +1028,13 @@ static void pmc_core_dbgfs_register(struct pmc_dev = *pmcdev) dir, &slps0_dbg_latch); } =20 - if (pmcdev->map->lpm_en_offset) { + if (primary_pmc->map->lpm_en_offset) { debugfs_create_file("substate_residencies", 0444, pmcdev->dbgfs_dir, pmcdev, &pmc_core_substate_res_fops); } =20 - if (pmcdev->map->lpm_status_offset) { + if (primary_pmc->map->lpm_status_offset) { debugfs_create_file("substate_status_registers", 0444, pmcdev->dbgfs_dir, pmcdev, &pmc_core_substate_sts_regs_fops); @@ -1030,7 +1046,7 @@ static void pmc_core_dbgfs_register(struct pmc_dev *p= mcdev) &pmc_core_lpm_latch_mode_fops); } =20 - if (pmcdev->lpm_req_regs) { + if (primary_pmc->lpm_req_regs) { debugfs_create_file("substate_requirements", 0444, pmcdev->dbgfs_dir, pmcdev, &pmc_core_substate_req_regs_fops); @@ -1081,16 +1097,16 @@ static int quirk_xtal_ignore(const struct dmi_syste= m_id *id) return 0; } =20 -static void pmc_core_xtal_ignore(struct pmc_dev *pmcdev) +static void pmc_core_xtal_ignore(struct pmc *pmc) { u32 value; =20 - value =3D pmc_core_reg_read(pmcdev, pmcdev->map->pm_vric1_offset); + value =3D pmc_core_reg_read(pmc, pmc->map->pm_vric1_offset); /* 24MHz Crystal Shutdown Qualification Disable */ value |=3D SPT_PMC_VRIC1_XTALSDQDIS; /* Low Voltage Mode Enable */ value &=3D ~SPT_PMC_VRIC1_SLPS0LVEN; - pmc_core_reg_write(pmcdev, pmcdev->map->pm_vric1_offset, value); + pmc_core_reg_write(pmc, pmc->map->pm_vric1_offset, value); } =20 static const struct dmi_system_id pmc_core_dmi_table[] =3D { @@ -1105,12 +1121,12 @@ static const struct dmi_system_id pmc_core_dmi_tabl= e[] =3D { {} }; =20 -static void pmc_core_do_dmi_quirks(struct pmc_dev *pmcdev) +static void pmc_core_do_dmi_quirks(struct pmc *pmc) { dmi_check_system(pmc_core_dmi_table); =20 if (xtal_ignore) - pmc_core_xtal_ignore(pmcdev); + pmc_core_xtal_ignore(pmc); } =20 static int pmc_core_probe(struct platform_device *pdev) @@ -1119,6 +1135,7 @@ static int pmc_core_probe(struct platform_device *pde= v) struct pmc_dev *pmcdev; const struct x86_cpu_id *cpu_id; int (*core_init)(struct pmc_dev *pmcdev); + struct pmc *primary_pmc; int ret; =20 if (device_initialized) @@ -1137,6 +1154,12 @@ static int pmc_core_probe(struct platform_device *pd= ev) =20 core_init =3D (int (*)(struct pmc_dev *))cpu_id->driver_data; =20 + /* Primary PMC */ + primary_pmc =3D devm_kzalloc(&pdev->dev, sizeof(*primary_pmc), GFP_KERNEL= ); + if (!primary_pmc) + return -ENOMEM; + pmcdev->pmcs[PMC_IDX_MAIN] =3D primary_pmc; + /* * Coffee Lake has CPU ID of Kaby Lake and Cannon Lake PCH. So here * Sunrisepoint PCH regmap can't be used. Use Cannon Lake PCH regmap @@ -1152,13 +1175,13 @@ static int pmc_core_probe(struct platform_device *p= dev) return ret; } =20 - pmcdev->pmc_xram_read_bit =3D pmc_core_check_read_lock_bit(pmcdev); + pmcdev->pmc_xram_read_bit =3D pmc_core_check_read_lock_bit(primary_pmc); pmc_core_get_low_power_modes(pdev); - pmc_core_do_dmi_quirks(pmcdev); + pmc_core_do_dmi_quirks(primary_pmc); =20 pmc_core_dbgfs_register(pmcdev); pm_report_max_hw_sleep(FIELD_MAX(SLP_S0_RES_COUNTER_MASK) * - pmc_core_adjust_slp_s0_step(pmcdev, 1)); + pmc_core_adjust_slp_s0_step(primary_pmc, 1)); =20 device_initialized =3D true; dev_info(&pdev->dev, " initialized\n"); @@ -1169,11 +1192,18 @@ static int pmc_core_probe(struct platform_device *p= dev) static void pmc_core_remove(struct platform_device *pdev) { struct pmc_dev *pmcdev =3D platform_get_drvdata(pdev); + int i; + + for (i =3D 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) { + struct pmc *pmc =3D pmcdev->pmcs[i]; + + if (pmc) + iounmap(pmc->regbase); + } =20 pmc_core_dbgfs_unregister(pmcdev); platform_set_drvdata(pdev, NULL); mutex_destroy(&pmcdev->lock); - iounmap(pmcdev->regbase); } =20 static bool warn_on_s0ix_failures; @@ -1183,6 +1213,7 @@ MODULE_PARM_DESC(warn_on_s0ix_failures, "Check and wa= rn for S0ix failures"); static __maybe_unused int pmc_core_suspend(struct device *dev) { struct pmc_dev *pmcdev =3D dev_get_drvdata(dev); + struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; =20 /* Check if the syspend will actually use S0ix */ if (pm_suspend_via_firmware()) @@ -1193,7 +1224,7 @@ static __maybe_unused int pmc_core_suspend(struct dev= ice *dev) return -EIO; =20 /* Save S0ix residency for checking later */ - if (pmc_core_dev_state_get(pmcdev, &pmcdev->s0ix_counter)) + if (pmc_core_dev_state_get(pmc, &pmcdev->s0ix_counter)) return -EIO; =20 return 0; @@ -1216,7 +1247,7 @@ static inline bool pmc_core_is_s0ix_failed(struct pmc= _dev *pmcdev) { u64 s0ix_counter; =20 - if (pmc_core_dev_state_get(pmcdev, &s0ix_counter)) + if (pmc_core_dev_state_get(pmcdev->pmcs[PMC_IDX_MAIN], &s0ix_counter)) return false; =20 pm_report_hw_sleep_time((u32)(s0ix_counter - pmcdev->s0ix_counter)); @@ -1229,9 +1260,10 @@ static inline bool pmc_core_is_s0ix_failed(struct pm= c_dev *pmcdev) =20 int pmc_core_resume_common(struct pmc_dev *pmcdev) { - const struct pmc_bit_map **maps =3D pmcdev->map->lpm_sts; - int offset =3D pmcdev->map->lpm_status_offset; struct device *dev =3D &pmcdev->pdev->dev; + struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; + const struct pmc_bit_map **maps =3D pmc->map->lpm_sts; + int offset =3D pmc->map->lpm_status_offset; =20 /* Check if the syspend used S0ix */ if (pm_suspend_via_firmware()) @@ -1253,10 +1285,10 @@ int pmc_core_resume_common(struct pmc_dev *pmcdev) /* The real interesting case - S0ix failed - lets ask PMC why. */ dev_warn(dev, "CPU did not enter SLP_S0!!! (S0ix cnt=3D%llu)\n", pmcdev->s0ix_counter); - if (pmcdev->map->slps0_dbg_maps) - pmc_core_slps0_display(pmcdev, dev, NULL); - if (pmcdev->map->lpm_sts) - pmc_core_lpm_display(pmcdev, dev, NULL, offset, "STATUS", maps); + if (pmc->map->slps0_dbg_maps) + pmc_core_slps0_display(pmc, dev, NULL); + if (pmc->map->lpm_sts) + pmc_core_lpm_display(pmc, dev, NULL, offset, "STATUS", maps); =20 return 0; } diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/i= ntel/pmc/core.h index a672659b8659..4f21d452a033 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/drivers/platform/x86/intel/pmc/core.h @@ -19,6 +19,7 @@ #define SLP_S0_RES_COUNTER_MASK GENMASK(31, 0) =20 #define PMC_BASE_ADDR_DEFAULT 0xFE000000 +#define MAX_NUM_PMC 3 =20 /* Sunrise Point Power Management Controller PCI Device ID */ #define SPT_PMC_PCI_DEVICE_ID 0x9d21 @@ -319,11 +320,25 @@ struct pmc_reg_map { }; =20 /** - * struct pmc_dev - pmc device structure + * struct pmc - pmc private info structure * @base_addr: contains pmc base address * @regbase: pointer to io-remapped memory location * @map: pointer to pmc_reg_map struct that contains platform * specific attributes + * @lpm_req_regs: List of substate requirements + * + * pmc contains info about one power management controller device. + */ +struct pmc { + u64 base_addr; + void __iomem *regbase; + const struct pmc_reg_map *map; + u32 *lpm_req_regs; +}; + +/** + * struct pmc_dev - pmc device structure + * @devs: pointer to an array of pmc pointers * @pdev: pointer to platform_device struct * @dbgfs_dir: path to debugfs interface * @pmc_xram_read_bit: flag to indicate whether PMC XRAM shadow registers @@ -333,15 +348,12 @@ struct pmc_reg_map { * @s0ix_counter: S0ix residency (step adjusted) * @num_lpm_modes: Count of enabled modes * @lpm_en_modes: Array of enabled modes from lowest to highest priority - * @lpm_req_regs: List of substate requirements * @resume: Function to perform platform specific resume * * pmc_dev contains info about power management controller device. */ struct pmc_dev { - u32 base_addr; - void __iomem *regbase; - const struct pmc_reg_map *map; + struct pmc *pmcs[MAX_NUM_PMC]; struct dentry *dbgfs_dir; struct platform_device *pdev; int pmc_xram_read_bit; @@ -351,8 +363,19 @@ struct pmc_dev { u64 s0ix_counter; int num_lpm_modes; int lpm_en_modes[LPM_MAX_NUM_MODES]; - u32 *lpm_req_regs; int (*resume)(struct pmc_dev *pmcdev); + + bool has_die_c6; + u32 die_c6_offset; + struct telem_endpoint *punit_ep; +}; + +enum pmc_index { + PMC_IDX_MAIN, + PMC_IDX_SOC =3D PMC_IDX_MAIN, + PMC_IDX_IOE, + PMC_IDX_PCH, + PMC_IDX_MAX }; =20 extern const struct pmc_bit_map msr_map[]; @@ -425,7 +448,7 @@ extern void pmc_core_get_tgl_lpm_reqs(struct platform_d= evice *pdev); extern int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value); =20 int pmc_core_resume_common(struct pmc_dev *pmcdev); -int get_primary_reg_base(struct pmc_dev *pmcdev); +int get_primary_reg_base(struct pmc *pmc); =20 int spt_core_init(struct pmc_dev *pmcdev); int cnp_core_init(struct pmc_dev *pmcdev); diff --git a/drivers/platform/x86/intel/pmc/icl.c b/drivers/platform/x86/in= tel/pmc/icl.c index a671d7e86431..d08e3174230d 100644 --- a/drivers/platform/x86/intel/pmc/icl.c +++ b/drivers/platform/x86/intel/pmc/icl.c @@ -52,6 +52,8 @@ const struct pmc_reg_map icl_reg_map =3D { =20 int icl_core_init(struct pmc_dev *pmcdev) { - pmcdev->map =3D &icl_reg_map; - return get_primary_reg_base(pmcdev); + struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; + + pmc->map =3D &icl_reg_map; + return get_primary_reg_base(pmc); } diff --git a/drivers/platform/x86/intel/pmc/mtl.c b/drivers/platform/x86/in= tel/pmc/mtl.c index a2fc96f9ef11..69df6d7fee56 100644 --- a/drivers/platform/x86/intel/pmc/mtl.c +++ b/drivers/platform/x86/intel/pmc/mtl.c @@ -508,15 +508,16 @@ static int mtl_resume(struct pmc_dev *pmcdev) =20 int mtl_core_init(struct pmc_dev *pmcdev) { + struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_SOC]; int ret; =20 - pmcdev->map =3D &mtl_socm_reg_map; + pmc->map =3D &mtl_socm_reg_map; =20 mtl_d3_fixup(); =20 pmcdev->resume =3D mtl_resume; =20 - ret =3D get_primary_reg_base(pmcdev); + ret =3D get_primary_reg_base(pmc); if (ret) return ret; =20 diff --git a/drivers/platform/x86/intel/pmc/spt.c b/drivers/platform/x86/in= tel/pmc/spt.c index f34015692bb8..4b6f5cbda16c 100644 --- a/drivers/platform/x86/intel/pmc/spt.c +++ b/drivers/platform/x86/intel/pmc/spt.c @@ -136,6 +136,8 @@ const struct pmc_reg_map spt_reg_map =3D { =20 int spt_core_init(struct pmc_dev *pmcdev) { - pmcdev->map =3D &spt_reg_map; - return get_primary_reg_base(pmcdev); + struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; + + pmc->map =3D &spt_reg_map; + return get_primary_reg_base(pmc); } diff --git a/drivers/platform/x86/intel/pmc/tgl.c b/drivers/platform/x86/in= tel/pmc/tgl.c index 90807bd947ed..2449940102db 100644 --- a/drivers/platform/x86/intel/pmc/tgl.c +++ b/drivers/platform/x86/intel/pmc/tgl.c @@ -208,7 +208,8 @@ const struct pmc_reg_map tgl_reg_map =3D { void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev) { struct pmc_dev *pmcdev =3D platform_get_drvdata(pdev); - const int num_maps =3D pmcdev->map->lpm_num_maps; + struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; + const int num_maps =3D pmc->map->lpm_num_maps; u32 lpm_size =3D LPM_MAX_NUM_MODES * num_maps * 4; union acpi_object *out_obj; struct acpi_device *adev; @@ -246,7 +247,7 @@ void pmc_core_get_tgl_lpm_reqs(struct platform_device *= pdev) goto free_acpi_obj; =20 memcpy(lpm_req_regs, addr, lpm_size); - pmcdev->lpm_req_regs =3D lpm_req_regs; + pmc->lpm_req_regs =3D lpm_req_regs; =20 free_acpi_obj: ACPI_FREE(out_obj); @@ -254,10 +255,11 @@ void pmc_core_get_tgl_lpm_reqs(struct platform_device= *pdev) =20 int tgl_core_init(struct pmc_dev *pmcdev) { + struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; int ret; =20 - pmcdev->map =3D &tgl_reg_map; - ret =3D get_primary_reg_base(pmcdev); + pmc->map =3D &tgl_reg_map; + ret =3D get_primary_reg_base(pmc); if (ret) return ret; =20 --=20 2.25.1 From nobody Sat Feb 7 18:21:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CD1EEB64D7 for ; Tue, 13 Jun 2023 22:51:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241182AbjFMWvv (ORCPT ); Tue, 13 Jun 2023 18:51:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45184 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232084AbjFMWvk (ORCPT ); Tue, 13 Jun 2023 18:51:40 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A6521739; Tue, 13 Jun 2023 15:51:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686696698; x=1718232698; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=g6fzUoNwXKYDIUEJeBOFu4PTHp6SiilU8h6006HIQgo=; b=nAgmXLbcFrZgB6z9E0T6XlLnkEaX1mcrLQngo3t8Oyod5cD7liZzG+hh Kw/3PMj0P/V4nhIDKvao+G83rkgGUt33K7sZ7SdNF72s9oje+cY1MCp+c uTuWaUOMkrQDRJ0FSKKRjwX8a3aNxJSYbxaZA41HGy+QwDlFL68utXCdX KlQPCnH8kVM9Mi0wCF+ek6jzJaSOwGBK/bxt1C4oNgbfbUhDwl+JX28XH jekguV55/RIaYsleH04QlI71aUH4o61MQpcXqkMuX0eYGd0pwHmSHYpJy Ms0PYwD3heBSDWBX0plqfWg3FCVifBv9Qr3cfKu2aKwEUfu23uN/zRKd5 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10740"; a="444842190" X-IronPort-AV: E=Sophos;i="6.00,241,1681196400"; d="scan'208";a="444842190" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jun 2023 15:51:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10740"; a="824589642" X-IronPort-AV: E=Sophos;i="6.00,241,1681196400"; d="scan'208";a="824589642" Received: from linux.intel.com ([10.54.29.200]) by fmsmga002.fm.intel.com with ESMTP; 13 Jun 2023 15:51:36 -0700 Received: from rjingar-desk5.amr.corp.intel.com (hciettox-mobl.amr.corp.intel.com [10.212.23.107]) by linux.intel.com (Postfix) with ESMTP id 942CB580D61; Tue, 13 Jun 2023 15:51:36 -0700 (PDT) From: Rajvi Jingar To: david.e.box@linux.intel.com, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, hdegoede@redhat.com Cc: xi.pardee@intel.com, Rajvi Jingar Subject: [PATCH 4/8] platform/x86:intel/pmc: Enable debugfs multiple PMC support Date: Tue, 13 Jun 2023 15:53:43 -0700 Message-Id: <20230613225347.2720665-5-rajvi.jingar@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613225347.2720665-1-rajvi.jingar@linux.intel.com> References: <20230613225347.2720665-1-rajvi.jingar@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xi Pardee Enable debugfs support for multiple PMC. These debugfs attributes show information for all enabled PMCs. pch_ip_power_gating_status substate_status_registers substate_live_status_registers ltr_show ltr_ignore Signed-off-by: Xi Pardee Signed-off-by: Rajvi Jingar Reviewed-by: Ilpo J=C3=A4rvinen --- drivers/platform/x86/intel/pmc/core.c | 195 +++++++++++++++++--------- 1 file changed, 129 insertions(+), 66 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/i= ntel/pmc/core.c index 8d774461dd29..5864d2e85706 100644 --- a/drivers/platform/x86/intel/pmc/core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -252,7 +252,7 @@ static int pmc_core_lpm_get_arr_size(const struct pmc_b= it_map **maps) } =20 static void pmc_core_lpm_display(struct pmc *pmc, struct device *dev, - struct seq_file *s, u32 offset, + struct seq_file *s, u32 offset, int pmc_index, const char *str, const struct pmc_bit_map **maps) { @@ -271,19 +271,19 @@ static void pmc_core_lpm_display(struct pmc *pmc, str= uct device *dev, =20 for (idx =3D 0; idx < arr_size; idx++) { if (dev) - dev_info(dev, "\nLPM_%s_%d:\t0x%x\n", str, idx, + dev_info(dev, "\nPMC%d:LPM_%s_%d:\t0x%x\n", pmc_index, str, idx, lpm_regs[idx]); if (s) - seq_printf(s, "\nLPM_%s_%d:\t0x%x\n", str, idx, + seq_printf(s, "\nPMC%d:LPM_%s_%d:\t0x%x\n", pmc_index, str, idx, lpm_regs[idx]); for (index =3D 0; maps[idx][index].name && index < len; index++) { bit_mask =3D maps[idx][index].bit_mask; if (dev) - dev_info(dev, "%-30s %-30d\n", + dev_info(dev, "PMC%d:%-30s %-30d\n", pmc_index, maps[idx][index].name, lpm_regs[idx] & bit_mask ? 1 : 0); if (s) - seq_printf(s, "%-30s %-30d\n", + seq_printf(s, "PMC%d:%-30s %-30d\n", pmc_index, maps[idx][index].name, lpm_regs[idx] & bit_mask ? 1 : 0); } @@ -300,32 +300,40 @@ static inline u8 pmc_core_reg_read_byte(struct pmc *p= mc, int offset) } =20 static void pmc_core_display_map(struct seq_file *s, int index, int idx, i= nt ip, - u8 pf_reg, const struct pmc_bit_map **pf_map) + int pmc_index, u8 pf_reg, const struct pmc_bit_map **pf_map) { - seq_printf(s, "PCH IP: %-2d - %-32s\tState: %s\n", - ip, pf_map[idx][index].name, + seq_printf(s, "PMC%d:PCH IP: %-2d - %-32s\tState: %s\n", + pmc_index, ip, pf_map[idx][index].name, pf_map[idx][index].bit_mask & pf_reg ? "Off" : "On"); } =20 static int pmc_core_ppfear_show(struct seq_file *s, void *unused) { struct pmc_dev *pmcdev =3D s->private; - struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; - const struct pmc_bit_map **maps =3D pmc->map->pfear_sts; - u8 pf_regs[PPFEAR_MAX_NUM_ENTRIES]; - int index, iter, idx, ip =3D 0; + int i; + + for (i =3D 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) { + struct pmc *pmc =3D pmcdev->pmcs[i]; + const struct pmc_bit_map **maps; + u8 pf_regs[PPFEAR_MAX_NUM_ENTRIES]; + int index, iter, idx, ip =3D 0; + + if (!pmc) + continue; =20 - iter =3D pmc->map->ppfear0_offset; + maps =3D pmc->map->pfear_sts; + iter =3D pmc->map->ppfear0_offset; =20 - for (index =3D 0; index < pmc->map->ppfear_buckets && - index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++) - pf_regs[index] =3D pmc_core_reg_read_byte(pmc, iter); + for (index =3D 0; index < pmc->map->ppfear_buckets && + index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++) + pf_regs[index] =3D pmc_core_reg_read_byte(pmc, iter); =20 - for (idx =3D 0; maps[idx]; idx++) { - for (index =3D 0; maps[idx][index].name && - index < pmc->map->ppfear_buckets * 8; ip++, index++) - pmc_core_display_map(s, index, idx, ip, - pf_regs[index / 8], maps); + for (idx =3D 0; maps[idx]; idx++) { + for (index =3D 0; maps[idx][index].name && + index < pmc->map->ppfear_buckets * 8; ip++, index++) + pmc_core_display_map(s, index, idx, ip, i, + pf_regs[index / 8], maps); + } } =20 return 0; @@ -454,26 +462,48 @@ DEFINE_SHOW_ATTRIBUTE(pmc_core_pll); =20 int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value) { - struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; - const struct pmc_reg_map *map =3D pmc->map; + struct pmc *pmc; + const struct pmc_reg_map *map; u32 reg; - int err =3D 0; + int pmc_index, ltr_index; =20 - mutex_lock(&pmcdev->lock); + ltr_index =3D value; + /* For platforms with multiple pmcs, ltr index value given by user + * is based on the contiguous indexes from ltr_show output. + * pmc index and ltr index needs to be calculated from it. + */ + for (pmc_index =3D 0; pmc_index < ARRAY_SIZE(pmcdev->pmcs) && ltr_index >= 0; pmc_index++) { + pmc =3D pmcdev->pmcs[pmc_index]; =20 - if (value > map->ltr_ignore_max) { - err =3D -EINVAL; - goto out_unlock; + if (!pmc) + continue; + + map =3D pmc->map; + if (ltr_index <=3D map->ltr_ignore_max) + break; + + /* Along with IP names, ltr_show map includes CURRENT_PLATFORM + * and AGGREGATED_SYSTEM values per PMC. Take these two index + * values into account in ltr_index calculation. Also, to start + * ltr index from zero for next pmc, subtract it by 1. + */ + ltr_index =3D ltr_index - (map->ltr_ignore_max + 2) - 1; } =20 + if (pmc_index >=3D ARRAY_SIZE(pmcdev->pmcs) || ltr_index < 0) + return -EINVAL; + + pr_debug("ltr_ignore for pmc%d: ltr_index:%d\n", pmc_index, ltr_index); + + mutex_lock(&pmcdev->lock); + reg =3D pmc_core_reg_read(pmc, map->ltr_ignore_offset); - reg |=3D BIT(value); + reg |=3D BIT(ltr_index); pmc_core_reg_write(pmc, map->ltr_ignore_offset, reg); =20 -out_unlock: mutex_unlock(&pmcdev->lock); =20 - return err; + return 0; } =20 static ssize_t pmc_core_ltr_ignore_write(struct file *file, @@ -586,36 +616,44 @@ static u32 convert_ltr_scale(u32 val) =20 static int pmc_core_ltr_show(struct seq_file *s, void *unused) { - struct pmc *pmc =3D s->private; - const struct pmc_bit_map *map =3D pmc->map->ltr_show_sts; + struct pmc_dev *pmcdev =3D s->private; u64 decoded_snoop_ltr, decoded_non_snoop_ltr; u32 ltr_raw_data, scale, val; u16 snoop_ltr, nonsnoop_ltr; - int index; + int i, index, ltr_index =3D 0; =20 - for (index =3D 0; map[index].name ; index++) { - decoded_snoop_ltr =3D decoded_non_snoop_ltr =3D 0; - ltr_raw_data =3D pmc_core_reg_read(pmc, - map[index].bit_mask); - snoop_ltr =3D ltr_raw_data & ~MTPMC_MASK; - nonsnoop_ltr =3D (ltr_raw_data >> 0x10) & ~MTPMC_MASK; - - if (FIELD_GET(LTR_REQ_NONSNOOP, ltr_raw_data)) { - scale =3D FIELD_GET(LTR_DECODED_SCALE, nonsnoop_ltr); - val =3D FIELD_GET(LTR_DECODED_VAL, nonsnoop_ltr); - decoded_non_snoop_ltr =3D val * convert_ltr_scale(scale); - } + for (i =3D 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) { + struct pmc *pmc =3D pmcdev->pmcs[i]; + const struct pmc_bit_map *map; =20 - if (FIELD_GET(LTR_REQ_SNOOP, ltr_raw_data)) { - scale =3D FIELD_GET(LTR_DECODED_SCALE, snoop_ltr); - val =3D FIELD_GET(LTR_DECODED_VAL, snoop_ltr); - decoded_snoop_ltr =3D val * convert_ltr_scale(scale); - } + if (!pmc) + continue; + + map =3D pmc->map->ltr_show_sts; + for (index =3D 0; map[index].name; index++) { + decoded_snoop_ltr =3D decoded_non_snoop_ltr =3D 0; + ltr_raw_data =3D pmc_core_reg_read(pmc, + map[index].bit_mask); + snoop_ltr =3D ltr_raw_data & ~MTPMC_MASK; + nonsnoop_ltr =3D (ltr_raw_data >> 0x10) & ~MTPMC_MASK; + + if (FIELD_GET(LTR_REQ_NONSNOOP, ltr_raw_data)) { + scale =3D FIELD_GET(LTR_DECODED_SCALE, nonsnoop_ltr); + val =3D FIELD_GET(LTR_DECODED_VAL, nonsnoop_ltr); + decoded_non_snoop_ltr =3D val * convert_ltr_scale(scale); + } + if (FIELD_GET(LTR_REQ_SNOOP, ltr_raw_data)) { + scale =3D FIELD_GET(LTR_DECODED_SCALE, snoop_ltr); + val =3D FIELD_GET(LTR_DECODED_VAL, snoop_ltr); + decoded_snoop_ltr =3D val * convert_ltr_scale(scale); + } =20 - seq_printf(s, "%-32s\tLTR: RAW: 0x%-16x\tNon-Snoop(ns): %-16llu\tSnoop(n= s): %-16llu\n", - map[index].name, ltr_raw_data, - decoded_non_snoop_ltr, - decoded_snoop_ltr); + seq_printf(s, "%d\tPMC%d:%-32s\tLTR: RAW: 0x%-16x\tNon-Snoop(ns): %-16l= lu\tSnoop(ns): %-16llu\n", + ltr_index, i, map[index].name, ltr_raw_data, + decoded_non_snoop_ltr, + decoded_snoop_ltr); + ltr_index++; + } } return 0; } @@ -651,11 +689,19 @@ DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_res); static int pmc_core_substate_sts_regs_show(struct seq_file *s, void *unuse= d) { struct pmc_dev *pmcdev =3D s->private; - struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; - const struct pmc_bit_map **maps =3D pmc->map->lpm_sts; - u32 offset =3D pmc->map->lpm_status_offset; + int i; + + for (i =3D 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) { + struct pmc *pmc =3D pmcdev->pmcs[i]; + const struct pmc_bit_map **maps; + u32 offset; =20 - pmc_core_lpm_display(pmc, NULL, s, offset, "STATUS", maps); + if (!pmc) + continue; + maps =3D pmc->map->lpm_sts; + offset =3D pmc->map->lpm_status_offset; + pmc_core_lpm_display(pmc, NULL, s, offset, i, "STATUS", maps); + } =20 return 0; } @@ -664,11 +710,19 @@ DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_sts_regs); static int pmc_core_substate_l_sts_regs_show(struct seq_file *s, void *unu= sed) { struct pmc_dev *pmcdev =3D s->private; - struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; - const struct pmc_bit_map **maps =3D pmc->map->lpm_sts; - u32 offset =3D pmc->map->lpm_live_status_offset; + int i; + + for (i =3D 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) { + struct pmc *pmc =3D pmcdev->pmcs[i]; + const struct pmc_bit_map **maps; + u32 offset; =20 - pmc_core_lpm_display(pmc, NULL, s, offset, "LIVE_STATUS", maps); + if (!pmc) + continue; + maps =3D pmc->map->lpm_sts; + offset =3D pmc->map->lpm_live_status_offset; + pmc_core_lpm_display(pmc, NULL, s, offset, i, "LIVE_STATUS", maps); + } =20 return 0; } @@ -1005,7 +1059,7 @@ static void pmc_core_dbgfs_register(struct pmc_dev *p= mcdev) debugfs_create_file("ltr_ignore", 0644, dir, pmcdev, &pmc_core_ltr_ignore_ops); =20 - debugfs_create_file("ltr_show", 0444, dir, primary_pmc, &pmc_core_ltr_fop= s); + debugfs_create_file("ltr_show", 0444, dir, pmcdev, &pmc_core_ltr_fops); =20 debugfs_create_file("package_cstate_show", 0444, dir, primary_pmc, &pmc_core_pkgc_fops); @@ -1264,6 +1318,7 @@ int pmc_core_resume_common(struct pmc_dev *pmcdev) struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; const struct pmc_bit_map **maps =3D pmc->map->lpm_sts; int offset =3D pmc->map->lpm_status_offset; + int i; =20 /* Check if the syspend used S0ix */ if (pm_suspend_via_firmware()) @@ -1285,10 +1340,18 @@ int pmc_core_resume_common(struct pmc_dev *pmcdev) /* The real interesting case - S0ix failed - lets ask PMC why. */ dev_warn(dev, "CPU did not enter SLP_S0!!! (S0ix cnt=3D%llu)\n", pmcdev->s0ix_counter); + if (pmc->map->slps0_dbg_maps) pmc_core_slps0_display(pmc, dev, NULL); - if (pmc->map->lpm_sts) - pmc_core_lpm_display(pmc, dev, NULL, offset, "STATUS", maps); + + for (i =3D 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) { + struct pmc *pmc =3D pmcdev->pmcs[i]; + + if (!pmc) + continue; + if (pmc->map->lpm_sts) + pmc_core_lpm_display(pmc, dev, NULL, offset, i, "STATUS", maps); + } =20 return 0; } --=20 2.25.1 From nobody Sat Feb 7 18:21:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20ACFEB64DA for ; Tue, 13 Jun 2023 22:52:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241386AbjFMWwH (ORCPT ); Tue, 13 Jun 2023 18:52:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231745AbjFMWvk (ORCPT ); Tue, 13 Jun 2023 18:51:40 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F5E11BEB; Tue, 13 Jun 2023 15:51:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686696698; x=1718232698; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MRcCSIse+0pgqd/VymmgSYUU5N49FGDLwpSbyMLrtOc=; b=ZajnNqy7Plie6LmVlTNYLzSLs2/i6heVBenLrh9cWquxQ6Mvq/df/+kh S8CuReH9ATQyzJM+oufWGQono5ofpGG44o6QrqDEUHnruKoZY0kI0dOAb k+hHS8lyBMofgAtVFYrBp7EmUpnD7MUWNGNAmcVgBZCtC2lKYNtMTRgK0 kWRgxTmsZLNkri0V0/ewi0UnLNz9cyvNyIKUTo8kRCCaTU72oRkgxhWhN 7nDF350KZFlkjT5kLruRmmIUuJ0OVPLnYaCvgQ0bmR2z7dex2ClHpGQJp pUZTrBdWqFY6UODI1I7tfxs2N3S3y1h9pLb9a96gltuEs2y4vd+O3652Y Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10740"; a="444842193" X-IronPort-AV: E=Sophos;i="6.00,241,1681196400"; d="scan'208";a="444842193" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jun 2023 15:51:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10740"; a="824589645" X-IronPort-AV: E=Sophos;i="6.00,241,1681196400"; d="scan'208";a="824589645" Received: from linux.intel.com ([10.54.29.200]) by fmsmga002.fm.intel.com with ESMTP; 13 Jun 2023 15:51:37 -0700 Received: from rjingar-desk5.amr.corp.intel.com (hciettox-mobl.amr.corp.intel.com [10.212.23.107]) by linux.intel.com (Postfix) with ESMTP id 50C83580BEE; Tue, 13 Jun 2023 15:51:37 -0700 (PDT) From: Rajvi Jingar To: david.e.box@linux.intel.com, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, hdegoede@redhat.com Cc: xi.pardee@intel.com, Rajvi Jingar Subject: [PATCH 5/8] platform/x86:intel/pmc: Discover PMC devices Date: Tue, 13 Jun 2023 15:53:44 -0700 Message-Id: <20230613225347.2720665-6-rajvi.jingar@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613225347.2720665-1-rajvi.jingar@linux.intel.com> References: <20230613225347.2720665-1-rajvi.jingar@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: "David E. Box" On platforms with multiple PMCs, additional PMC devices are discovered in the SSRAM device associated with the primary PMC. Add support for discovering PMC devices from SSRAM. Use PMC devid to assign the corresponding register map. Signed-off-by: Xi Pardee Signed-off-by: David E. Box Signed-off-by: Rajvi Jingar Reviewed-by: Ilpo J=C3=A4rvinen --- drivers/platform/x86/intel/pmc/Makefile | 4 +- drivers/platform/x86/intel/pmc/core.c | 34 +++-- drivers/platform/x86/intel/pmc/core.h | 16 +++ drivers/platform/x86/intel/pmc/core_ssram.c | 133 ++++++++++++++++++++ drivers/platform/x86/intel/pmc/mtl.c | 7 ++ 5 files changed, 180 insertions(+), 14 deletions(-) create mode 100644 drivers/platform/x86/intel/pmc/core_ssram.c diff --git a/drivers/platform/x86/intel/pmc/Makefile b/drivers/platform/x86= /intel/pmc/Makefile index f96bc2e19503..3a4cf1cbc1ca 100644 --- a/drivers/platform/x86/intel/pmc/Makefile +++ b/drivers/platform/x86/intel/pmc/Makefile @@ -3,8 +3,8 @@ # Intel x86 Platform-Specific Drivers # =20 -intel_pmc_core-y :=3D core.o spt.o cnp.o icl.o tgl.o \ - adl.o mtl.o +intel_pmc_core-y :=3D core.o core_ssram.o spt.o cnp.o \ + icl.o tgl.o adl.o mtl.o obj-$(CONFIG_INTEL_PMC_CORE) +=3D intel_pmc_core.o intel_pmc_core_pltdrv-y :=3D pltdrv.o obj-$(CONFIG_INTEL_PMC_CORE) +=3D intel_pmc_core_pltdrv.o diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/i= ntel/pmc/core.c index 5864d2e85706..5a36b3f77bc5 100644 --- a/drivers/platform/x86/intel/pmc/core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -1183,6 +1183,26 @@ static void pmc_core_do_dmi_quirks(struct pmc *pmc) pmc_core_xtal_ignore(pmc); } =20 +static void pmc_core_clean_structure(struct platform_device *pdev) +{ + struct pmc_dev *pmcdev =3D platform_get_drvdata(pdev); + int i; + + for (i =3D 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) { + struct pmc *pmc =3D pmcdev->pmcs[i]; + + if (pmc) + iounmap(pmc->regbase); + } + + if (pmcdev->ssram_pcidev) { + pci_dev_put(pmcdev->ssram_pcidev); + pci_disable_device(pmcdev->ssram_pcidev); + } + platform_set_drvdata(pdev, NULL); + mutex_destroy(&pmcdev->lock); +} + static int pmc_core_probe(struct platform_device *pdev) { static bool device_initialized; @@ -1225,7 +1245,7 @@ static int pmc_core_probe(struct platform_device *pde= v) mutex_init(&pmcdev->lock); ret =3D core_init(pmcdev); if (ret) { - mutex_destroy(&pmcdev->lock); + pmc_core_clean_structure(pdev); return ret; } =20 @@ -1246,18 +1266,8 @@ static int pmc_core_probe(struct platform_device *pd= ev) static void pmc_core_remove(struct platform_device *pdev) { struct pmc_dev *pmcdev =3D platform_get_drvdata(pdev); - int i; - - for (i =3D 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) { - struct pmc *pmc =3D pmcdev->pmcs[i]; - - if (pmc) - iounmap(pmc->regbase); - } - pmc_core_dbgfs_unregister(pmcdev); - platform_set_drvdata(pdev, NULL); - mutex_destroy(&pmcdev->lock); + pmc_core_clean_structure(pdev); } =20 static bool warn_on_s0ix_failures; diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/i= ntel/pmc/core.h index 4f21d452a033..06c444917a16 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/drivers/platform/x86/intel/pmc/core.h @@ -319,6 +319,17 @@ struct pmc_reg_map { const u32 etr3_offset; }; =20 +/** + * struct pmc_info - Structure to keep pmc info + * @devid: device id of the pmc device + * @map: pointer to a pmc_reg_map struct that contains platform + * specific attributes + */ +struct pmc_info { + u16 devid; + const struct pmc_reg_map *map; +}; + /** * struct pmc - pmc private info structure * @base_addr: contains pmc base address @@ -340,6 +351,7 @@ struct pmc { * struct pmc_dev - pmc device structure * @devs: pointer to an array of pmc pointers * @pdev: pointer to platform_device struct + * @ssram_pcidev: pointer to pci device struct for the PMC SSRAM * @dbgfs_dir: path to debugfs interface * @pmc_xram_read_bit: flag to indicate whether PMC XRAM shadow registers * used to read MPHY PG and PLL status are available @@ -356,6 +368,7 @@ struct pmc_dev { struct pmc *pmcs[MAX_NUM_PMC]; struct dentry *dbgfs_dir; struct platform_device *pdev; + struct pci_dev *ssram_pcidev; int pmc_xram_read_bit; struct mutex lock; /* generic mutex lock for PMC Core */ =20 @@ -368,6 +381,7 @@ struct pmc_dev { bool has_die_c6; u32 die_c6_offset; struct telem_endpoint *punit_ep; + struct pmc_info *regmap_list; }; =20 enum pmc_index { @@ -450,6 +464,8 @@ extern int pmc_core_send_ltr_ignore(struct pmc_dev *pmc= dev, u32 value); int pmc_core_resume_common(struct pmc_dev *pmcdev); int get_primary_reg_base(struct pmc *pmc); =20 +extern void pmc_core_ssram_init(struct pmc_dev *pmcdev); + int spt_core_init(struct pmc_dev *pmcdev); int cnp_core_init(struct pmc_dev *pmcdev); int icl_core_init(struct pmc_dev *pmcdev); diff --git a/drivers/platform/x86/intel/pmc/core_ssram.c b/drivers/platform= /x86/intel/pmc/core_ssram.c new file mode 100644 index 000000000000..13fa16f0d52e --- /dev/null +++ b/drivers/platform/x86/intel/pmc/core_ssram.c @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * This file contains functions to handle discovery of PMC metrics located + * in the PMC SSRAM PCI device. + * + * Copyright (c) 2023, Intel Corporation. + * All Rights Reserved. + * + */ + +#include +#include + +#include "core.h" + +#define SSRAM_HDR_SIZE 0x100 +#define SSRAM_PWRM_OFFSET 0x14 +#define SSRAM_DVSEC_OFFSET 0x1C +#define SSRAM_DVSEC_SIZE 0x10 +#define SSRAM_PCH_OFFSET 0x60 +#define SSRAM_IOE_OFFSET 0x68 +#define SSRAM_DEVID_OFFSET 0x70 + +static const struct pmc_reg_map *pmc_core_find_regmap(struct pmc_info *lis= t, u16 devid) +{ + for (; list->map; ++list) + if (devid =3D=3D list->devid) + return list->map; + + return NULL; +} + +static inline u64 get_base(void __iomem *addr, u32 offset) +{ + return lo_hi_readq(addr + offset) & GENMASK_ULL(63, 3); +} + +static void +pmc_core_pmc_add(struct pmc_dev *pmcdev, u64 pwrm_base, + const struct pmc_reg_map *reg_map, int pmc_index) +{ + struct pmc *pmc =3D pmcdev->pmcs[pmc_index]; + + if (!pwrm_base) + return; + + /* Memory for primary PMC has been allocated in core.c */ + if (!pmc) { + pmc =3D devm_kzalloc(&pmcdev->pdev->dev, sizeof(*pmc), GFP_KERNEL); + if (!pmc) + return; + } + + pmc->map =3D reg_map; + pmc->base_addr =3D pwrm_base; + pmc->regbase =3D ioremap(pmc->base_addr, pmc->map->regmap_length); + + if (!pmc->regbase) { + devm_kfree(&pmcdev->pdev->dev, pmc); + return; + } + + pmcdev->pmcs[pmc_index] =3D pmc; +} + +static void +pmc_core_ssram_get_pmc(struct pmc_dev *pmcdev, void __iomem *ssram, u32 of= fset, + int pmc_idx) +{ + u64 pwrm_base; + u16 devid; + + if (pmc_idx !=3D PMC_IDX_SOC) { + u64 ssram_base =3D get_base(ssram, offset); + + if (!ssram_base) + return; + + ssram =3D ioremap(ssram_base, SSRAM_HDR_SIZE); + if (!ssram) + return; + } + + pwrm_base =3D get_base(ssram, SSRAM_PWRM_OFFSET); + devid =3D readw(ssram + SSRAM_DEVID_OFFSET); + + if (pmcdev->regmap_list) { + const struct pmc_reg_map *map; + + map =3D pmc_core_find_regmap(pmcdev->regmap_list, devid); + if (map) + pmc_core_pmc_add(pmcdev, pwrm_base, map, pmc_idx); + } + + if (pmc_idx !=3D PMC_IDX_SOC) + iounmap(ssram); +} + +void pmc_core_ssram_init(struct pmc_dev *pmcdev) +{ + void __iomem *ssram; + struct pci_dev *pcidev; + u64 ssram_base; + int ret; + + pcidev =3D pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(20, 2)); + if (!pcidev) + goto out; + + ret =3D pcim_enable_device(pcidev); + if (ret) + goto release_dev; + + ssram_base =3D pcidev->resource[0].start; + ssram =3D ioremap(ssram_base, SSRAM_HDR_SIZE); + if (!ssram) + goto disable_dev; + + pmcdev->ssram_pcidev =3D pcidev; + + pmc_core_ssram_get_pmc(pmcdev, ssram, 0, PMC_IDX_SOC); + pmc_core_ssram_get_pmc(pmcdev, ssram, SSRAM_IOE_OFFSET, PMC_IDX_IOE); + pmc_core_ssram_get_pmc(pmcdev, ssram, SSRAM_PCH_OFFSET, PMC_IDX_PCH); + + iounmap(ssram); +out: + return; + +disable_dev: + pci_disable_device(pcidev); +release_dev: + pci_dev_put(pcidev); +} diff --git a/drivers/platform/x86/intel/pmc/mtl.c b/drivers/platform/x86/in= tel/pmc/mtl.c index 69df6d7fee56..e53dc7900dbf 100644 --- a/drivers/platform/x86/intel/pmc/mtl.c +++ b/drivers/platform/x86/intel/pmc/mtl.c @@ -467,6 +467,10 @@ const struct pmc_reg_map mtl_socm_reg_map =3D { .lpm_live_status_offset =3D MTL_LPM_LIVE_STATUS_OFFSET, }; =20 +static struct pmc_info mtl_pmc_info_list[] =3D { + {} +}; + #define MTL_GNA_PCI_DEV 0x7e4c #define MTL_IPU_PCI_DEV 0x7d19 #define MTL_VPU_PCI_DEV 0x7d1d @@ -517,6 +521,9 @@ int mtl_core_init(struct pmc_dev *pmcdev) =20 pmcdev->resume =3D mtl_resume; =20 + pmcdev->regmap_list =3D mtl_pmc_info_list; + pmc_core_ssram_init(pmcdev); + ret =3D get_primary_reg_base(pmc); if (ret) return ret; --=20 2.25.1 From nobody Sat Feb 7 18:21:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70DA7EB64D8 for ; Tue, 13 Jun 2023 22:51:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241329AbjFMWv6 (ORCPT ); Tue, 13 Jun 2023 18:51:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240280AbjFMWvl (ORCPT ); Tue, 13 Jun 2023 18:51:41 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 10B16EC; Tue, 13 Jun 2023 15:51:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686696700; x=1718232700; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bZY3z6BjCSOhZSStN0QmqBrpo5tpcryq8FmwLtwtVP8=; b=cgFOQryoxKRpU35W7qVLdwE2IoDMKdz2v/GpzSMgG1gZpTJzV9wTfQIF YdrLb80LmOPubCWPXyLOb+WnRDeSn+MrmOS+yKBWjqo+GZWtk/NPCwwMD l+lwu6TWHkd0xRi8WBbH4kVCyUPmXkMd3t8G+CnUb3A9fj47Ugb3LMCjd CXe+B+KtbtcaVNoFHwgpCgLiAiiMD+nV+k0wdDrvs09x/9f4OQ+J7LVQt UIqGcNcI721tVnVvvhzp1wIgycwTfhL6V+0+PEA+YZDHxb0p5pjpVEyD2 IFWdpy+OW49MgItUAQughUqlloyITWvT83gA3nxRHGy/JwVuxJhI7+N1f A==; X-IronPort-AV: E=McAfee;i="6600,9927,10740"; a="444842197" X-IronPort-AV: E=Sophos;i="6.00,241,1681196400"; d="scan'208";a="444842197" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jun 2023 15:51:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10740"; a="824589648" X-IronPort-AV: E=Sophos;i="6.00,241,1681196400"; d="scan'208";a="824589648" Received: from linux.intel.com ([10.54.29.200]) by fmsmga002.fm.intel.com with ESMTP; 13 Jun 2023 15:51:38 -0700 Received: from rjingar-desk5.amr.corp.intel.com (hciettox-mobl.amr.corp.intel.com [10.212.23.107]) by linux.intel.com (Postfix) with ESMTP id EE068580BF8; Tue, 13 Jun 2023 15:51:37 -0700 (PDT) From: Rajvi Jingar To: david.e.box@linux.intel.com, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, hdegoede@redhat.com Cc: xi.pardee@intel.com Subject: [PATCH 6/8] platform/x86:intel/pmc: Use SSRAM to discover pwrm base address of primary PMC Date: Tue, 13 Jun 2023 15:53:45 -0700 Message-Id: <20230613225347.2720665-7-rajvi.jingar@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613225347.2720665-1-rajvi.jingar@linux.intel.com> References: <20230613225347.2720665-1-rajvi.jingar@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xi Pardee On older platforms, the base address for PMC was hardcoded in the driver. Newer platforms can now retrieve the base address from SSRAM. Use SSRAM to discover pwrm base address on Meteor Lake platform. If this method fails, it will fall back to the hardcoded value. Signed-off-by: Xi Pardee Reviewed-by: Ilpo J=C3=A4rvinen --- drivers/platform/x86/intel/pmc/mtl.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/mtl.c b/drivers/platform/x86/in= tel/pmc/mtl.c index e53dc7900dbf..b5552bb146c9 100644 --- a/drivers/platform/x86/intel/pmc/mtl.c +++ b/drivers/platform/x86/intel/pmc/mtl.c @@ -467,7 +467,12 @@ const struct pmc_reg_map mtl_socm_reg_map =3D { .lpm_live_status_offset =3D MTL_LPM_LIVE_STATUS_OFFSET, }; =20 +#define PMC_DEVID_SOCM 0x7e7f static struct pmc_info mtl_pmc_info_list[] =3D { + { + .devid =3D PMC_DEVID_SOCM, + .map =3D &mtl_socm_reg_map, + }, {} }; =20 @@ -513,9 +518,7 @@ static int mtl_resume(struct pmc_dev *pmcdev) int mtl_core_init(struct pmc_dev *pmcdev) { struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_SOC]; - int ret; - - pmc->map =3D &mtl_socm_reg_map; + int ret =3D 0; =20 mtl_d3_fixup(); =20 @@ -524,9 +527,13 @@ int mtl_core_init(struct pmc_dev *pmcdev) pmcdev->regmap_list =3D mtl_pmc_info_list; pmc_core_ssram_init(pmcdev); =20 - ret =3D get_primary_reg_base(pmc); - if (ret) - return ret; + /* If regbase not assigned, set map and discover using legacy method */ + if (!pmc->regbase) { + pmc->map =3D &mtl_socm_reg_map; + ret =3D get_primary_reg_base(pmc); + if (ret) + return ret; + } =20 /* Due to a hardware limitation, the GBE LTR blocks PC10 * when a cable is attached. Tell the PMC to ignore it. --=20 2.25.1 From nobody Sat Feb 7 18:21:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AAA6EB64D8 for ; Tue, 13 Jun 2023 22:52:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241387AbjFMWwB (ORCPT ); Tue, 13 Jun 2023 18:52:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45270 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240605AbjFMWvm (ORCPT ); Tue, 13 Jun 2023 18:51:42 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14F881981; Tue, 13 Jun 2023 15:51:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686696700; x=1718232700; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=b3rA9w7nxlEXttQBni+aWxEahEOqFvGpDV4OWlGNayM=; b=mPY2Fa6rIFljQ0k/FcQ1WP0z2P08HCnpTOxkXGmupGAW0QCQKCOnYEC1 VrmPJ95VrNVoJ+cQK0l2nthe8UuESy6ZTvANTxrRrYg+HEbWbHzCqH+Pb LHTAuHbl6xERgmIzoFS27K6jdKDwjYrVLdCQhEOnw+A1KKFMnbgeUmZ8W IhlfYD9IVG4ABQzeSUedJB9xXiGGbeGFfE4SmWKGSwqSSCgw9dQzQI322 jEsEfTNdkG7SZM9aGA25T8SKzT7mKZn0yJ/lKl63UOnZfMf/wdhwuzRAk hsnXH8/uuGJetBcqQ0ot8mDNK06gVnn3b94t4pXBx923v6MjxlsyEvK8L A==; X-IronPort-AV: E=McAfee;i="6600,9927,10740"; a="444842200" X-IronPort-AV: E=Sophos;i="6.00,241,1681196400"; d="scan'208";a="444842200" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jun 2023 15:51:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10740"; a="824589651" X-IronPort-AV: E=Sophos;i="6.00,241,1681196400"; d="scan'208";a="824589651" Received: from linux.intel.com ([10.54.29.200]) by fmsmga002.fm.intel.com with ESMTP; 13 Jun 2023 15:51:38 -0700 Received: from rjingar-desk5.amr.corp.intel.com (hciettox-mobl.amr.corp.intel.com [10.212.23.107]) by linux.intel.com (Postfix) with ESMTP id 8F6CD580D61; Tue, 13 Jun 2023 15:51:38 -0700 (PDT) From: Rajvi Jingar To: david.e.box@linux.intel.com, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, hdegoede@redhat.com Cc: xi.pardee@intel.com, Rajvi Jingar Subject: [PATCH 7/8] platform/x86:intel/pmc: Add Meteor Lake IOE-P PMC related maps Date: Tue, 13 Jun 2023 15:53:46 -0700 Message-Id: <20230613225347.2720665-8-rajvi.jingar@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613225347.2720665-1-rajvi.jingar@linux.intel.com> References: <20230613225347.2720665-1-rajvi.jingar@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xi Pardee Add device ID and register maps for the PMC in IO expansion die P in Meteor Lake. Signed-off-by: Xi Pardee Signed-off-by: Rajvi Jingar Reviewed-by: Ilpo J=C3=A4rvinen --- drivers/platform/x86/intel/pmc/core.h | 21 ++ drivers/platform/x86/intel/pmc/mtl.c | 322 ++++++++++++++++++++++++++ 2 files changed, 343 insertions(+) diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/i= ntel/pmc/core.h index 06c444917a16..0c899efaa206 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/drivers/platform/x86/intel/pmc/core.h @@ -252,12 +252,15 @@ enum ppfear_regs { #define MTL_LPM_LIVE_STATUS_OFFSET 0x175C #define MTL_PMC_LTR_IOE_PMC 0x1C0C #define MTL_PMC_LTR_ESE 0x1BAC +#define MTL_PMC_LTR_RESERVED 0x1BA4 +#define MTL_IOE_PMC_MMIO_REG_LEN 0x23A4 #define MTL_SOCM_NUM_IP_IGN_ALLOWED 25 #define MTL_SOC_PMC_MMIO_REG_LEN 0x2708 #define MTL_PMC_LTR_SPG 0x1B74 =20 /* Meteor Lake PGD PFET Enable Ack Status */ #define MTL_SOCM_PPFEAR_NUM_ENTRIES 8 +#define MTL_IOE_PPFEAR_NUM_ENTRIES 10 =20 extern const char *pmc_lpm_modes[]; =20 @@ -457,6 +460,24 @@ extern const struct pmc_bit_map mtl_socm_vnn_misc_stat= us_map[]; extern const struct pmc_bit_map mtl_socm_signal_status_map[]; extern const struct pmc_bit_map *mtl_socm_lpm_maps[]; extern const struct pmc_reg_map mtl_socm_reg_map; +extern const struct pmc_bit_map mtl_ioep_pfear_map[]; +extern const struct pmc_bit_map *ext_mtl_ioep_pfear_map[]; +extern const struct pmc_bit_map mtl_ioep_ltr_show_map[]; +extern const struct pmc_bit_map mtl_ioep_clocksource_status_map[]; +extern const struct pmc_bit_map mtl_ioep_power_gating_status_0_map[]; +extern const struct pmc_bit_map mtl_ioep_power_gating_status_1_map[]; +extern const struct pmc_bit_map mtl_ioep_power_gating_status_2_map[]; +extern const struct pmc_bit_map mtl_ioep_d3_status_0_map[]; +extern const struct pmc_bit_map mtl_ioep_d3_status_1_map[]; +extern const struct pmc_bit_map mtl_ioep_d3_status_2_map[]; +extern const struct pmc_bit_map mtl_ioep_d3_status_3_map[]; +extern const struct pmc_bit_map mtl_ioep_vnn_req_status_0_map[]; +extern const struct pmc_bit_map mtl_ioep_vnn_req_status_1_map[]; +extern const struct pmc_bit_map mtl_ioep_vnn_req_status_2_map[]; +extern const struct pmc_bit_map mtl_ioep_vnn_req_status_3_map[]; +extern const struct pmc_bit_map mtl_ioep_vnn_misc_status_map[]; +extern const struct pmc_bit_map *mtl_ioep_lpm_maps[]; +extern const struct pmc_reg_map mtl_ioep_reg_map; =20 extern void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev); extern int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value); diff --git a/drivers/platform/x86/intel/pmc/mtl.c b/drivers/platform/x86/in= tel/pmc/mtl.c index b5552bb146c9..da3dba8c653b 100644 --- a/drivers/platform/x86/intel/pmc/mtl.c +++ b/drivers/platform/x86/intel/pmc/mtl.c @@ -467,12 +467,334 @@ const struct pmc_reg_map mtl_socm_reg_map =3D { .lpm_live_status_offset =3D MTL_LPM_LIVE_STATUS_OFFSET, }; =20 +const struct pmc_bit_map mtl_ioep_pfear_map[] =3D { + {"PMC_0", BIT(0)}, + {"OPI", BIT(1)}, + {"TCSS", BIT(2)}, + {"RSVD3", BIT(3)}, + {"SPA", BIT(4)}, + {"SPB", BIT(5)}, + {"SPC", BIT(6)}, + {"IOE_D2D_3", BIT(7)}, + + {"RSVD8", BIT(0)}, + {"RSVD9", BIT(1)}, + {"SPE", BIT(2)}, + {"RSVD11", BIT(3)}, + {"RSVD12", BIT(4)}, + {"SPD", BIT(5)}, + {"ACE_7", BIT(6)}, + {"RSVD15", BIT(7)}, + + {"ACE_0", BIT(0)}, + {"FIACPCB_P", BIT(1)}, + {"P2S", BIT(2)}, + {"RSVD19", BIT(3)}, + {"ACE_8", BIT(4)}, + {"IOE_D2D_0", BIT(5)}, + {"FUSE", BIT(6)}, + {"RSVD23", BIT(7)}, + + {"FIACPCB_P5", BIT(0)}, + {"ACE_3", BIT(1)}, + {"RSF5", BIT(2)}, + {"ACE_2", BIT(3)}, + {"ACE_4", BIT(4)}, + {"RSVD29", BIT(5)}, + {"RSF10", BIT(6)}, + {"MPFPW5", BIT(7)}, + + {"PSF9", BIT(0)}, + {"MPFPW4", BIT(1)}, + {"RSVD34", BIT(2)}, + {"RSVD35", BIT(3)}, + {"RSVD36", BIT(4)}, + {"RSVD37", BIT(5)}, + {"RSVD38", BIT(6)}, + {"RSVD39", BIT(7)}, + + {"SBR0", BIT(0)}, + {"SBR1", BIT(1)}, + {"SBR2", BIT(2)}, + {"SBR3", BIT(3)}, + {"SBR4", BIT(4)}, + {"SBR5", BIT(5)}, + {"RSVD46", BIT(6)}, + {"RSVD47", BIT(7)}, + + {"RSVD48", BIT(0)}, + {"FIA_P5", BIT(1)}, + {"RSVD50", BIT(2)}, + {"RSVD51", BIT(3)}, + {"RSVD52", BIT(4)}, + {"RSVD53", BIT(5)}, + {"RSVD54", BIT(6)}, + {"ACE_1", BIT(7)}, + + {"RSVD56", BIT(0)}, + {"ACE_5", BIT(1)}, + {"RSVD58", BIT(2)}, + {"G5FPW1", BIT(3)}, + {"RSVD60", BIT(4)}, + {"ACE_6", BIT(5)}, + {"RSVD62", BIT(6)}, + {"GBETSN1", BIT(7)}, + + {"RSVD64", BIT(0)}, + {"FIA", BIT(1)}, + {"RSVD66", BIT(2)}, + {"FIA_P", BIT(3)}, + {"TAM", BIT(4)}, + {"GBETSN", BIT(5)}, + {"IOE_D2D_2", BIT(6)}, + {"IOE_D2D_1", BIT(7)}, + + {"SPF", BIT(0)}, + {"PMC_1", BIT(1)}, + {} +}; + +const struct pmc_bit_map *ext_mtl_ioep_pfear_map[] =3D { + mtl_ioep_pfear_map, + NULL +}; + +const struct pmc_bit_map mtl_ioep_ltr_show_map[] =3D { + {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, + {"SOUTHPORT_B", CNP_PMC_LTR_SPB}, + {"SATA", CNP_PMC_LTR_SATA}, + {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE}, + {"XHCI", CNP_PMC_LTR_XHCI}, + {"SOUTHPORT_F", ADL_PMC_LTR_SPF}, + {"ME", CNP_PMC_LTR_ME}, + {"SATA1", CNP_PMC_LTR_EVA}, + {"SOUTHPORT_C", CNP_PMC_LTR_SPC}, + {"HD_AUDIO", CNP_PMC_LTR_AZ}, + {"CNV", CNP_PMC_LTR_CNV}, + {"LPSS", CNP_PMC_LTR_LPSS}, + {"SOUTHPORT_D", CNP_PMC_LTR_SPD}, + {"SOUTHPORT_E", CNP_PMC_LTR_SPE}, + {"SATA2", CNP_PMC_LTR_CAM}, + {"ESPI", CNP_PMC_LTR_ESPI}, + {"SCC", CNP_PMC_LTR_SCC}, + {"Reserved", MTL_PMC_LTR_RESERVED}, + {"UFSX2", CNP_PMC_LTR_UFSX2}, + {"EMMC", CNP_PMC_LTR_EMMC}, + {"WIGIG", ICL_PMC_LTR_WIGIG}, + {"THC0", TGL_PMC_LTR_THC0}, + {"THC1", TGL_PMC_LTR_THC1}, + {"SOUTHPORT_G", MTL_PMC_LTR_SPG}, + + /* Below two cannot be used for LTR_IGNORE */ + {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT}, + {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT}, + {} +}; + +const struct pmc_bit_map mtl_ioep_clocksource_status_map[] =3D { + {"AON2_OFF_STS", BIT(0)}, + {"AON3_OFF_STS", BIT(1)}, + {"AON4_OFF_STS", BIT(2)}, + {"AON5_OFF_STS", BIT(3)}, + {"AON1_OFF_STS", BIT(4)}, + {"TBT_PLL_OFF_STS", BIT(5)}, + {"TMU_PLL_OFF_STS", BIT(6)}, + {"BCLK_PLL_OFF_STS", BIT(7)}, + {"D2D_PLL_OFF_STS", BIT(8)}, + {"AON3_SPL_OFF_STS", BIT(9)}, + {"MPFPW4_0_PLL_OFF_STS", BIT(12)}, + {"MPFPW5_0_PLL_OFF_STS", BIT(13)}, + {"G5FPW_0_PLL_OFF_STS", BIT(14)}, + {"G5FPW_1_PLL_OFF_STS", BIT(15)}, + {"XTAL_AGGR_OFF_STS", BIT(17)}, + {"FABRIC_PLL_OFF_STS", BIT(25)}, + {"SOC_PLL_OFF_STS", BIT(26)}, + {"REF_PLL_OFF_STS", BIT(28)}, + {"RTC_PLL_OFF_STS", BIT(31)}, + {} +}; + +const struct pmc_bit_map mtl_ioep_power_gating_status_0_map[] =3D { + {"PMC_PGD0_PG_STS", BIT(0)}, + {"DMI_PGD0_PG_STS", BIT(1)}, + {"TCSS_PGD0_PG_STS", BIT(2)}, + {"SPA_PGD0_PG_STS", BIT(4)}, + {"SPB_PGD0_PG_STS", BIT(5)}, + {"SPC_PGD0_PG_STS", BIT(6)}, + {"IOE_D2D_PGD3_PG_STS", BIT(7)}, + {"SPE_PGD0_PG_STS", BIT(10)}, + {"SPD_PGD0_PG_STS", BIT(13)}, + {"ACE_PGD7_PG_STS", BIT(14)}, + {"ACE_PGD0_PG_STS", BIT(16)}, + {"FIACPCB_P_PGD0_PG_STS", BIT(17)}, + {"P2S_PGD0_PG_STS", BIT(18)}, + {"ACE_PGD8_PG_STS", BIT(20)}, + {"IOE_D2D_PGD0_PG_STS", BIT(21)}, + {"FUSE_PGD0_PG_STS", BIT(22)}, + {"FIACPCB_P5_PGD0_PG_STS", BIT(24)}, + {"ACE_PGD3_PG_STS", BIT(25)}, + {"PSF5_PGD0_PG_STS", BIT(26)}, + {"ACE_PGD2_PG_STS", BIT(27)}, + {"ACE_PGD4_PG_STS", BIT(28)}, + {"PSF10_PGD0_PG_STS", BIT(30)}, + {"MPFPW5_PGD0_PG_STS", BIT(31)}, + {} +}; + +const struct pmc_bit_map mtl_ioep_power_gating_status_1_map[] =3D { + {"PSF9_PGD0_PG_STS", BIT(0)}, + {"MPFPW4_PGD0_PG_STS", BIT(1)}, + {"SBR0_PGD0_PG_STS", BIT(8)}, + {"SBR1_PGD0_PG_STS", BIT(9)}, + {"SBR2_PGD0_PG_STS", BIT(10)}, + {"SBR3_PGD0_PG_STS", BIT(11)}, + {"SBR4_PGD0_PG_STS", BIT(12)}, + {"SBR5_PGD0_PG_STS", BIT(13)}, + {"FIA_P5_PGD0_PG_STS", BIT(17)}, + {"ACE_PGD1_PGD0_PG_STS", BIT(23)}, + {"ACE_PGD5_PGD1_PG_STS", BIT(25)}, + {"G5FPW1_PGD0_PG_STS", BIT(27)}, + {"ACE_PGD6_PG_STS", BIT(29)}, + {"GBETSN1_PGD0_PG_STS", BIT(31)}, + {} +}; + +const struct pmc_bit_map mtl_ioep_power_gating_status_2_map[] =3D { + {"FIA_PGD0_PG_STS", BIT(1)}, + {"FIA_P_PGD0_PG_STS", BIT(3)}, + {"TAM_PGD0_PG_STS", BIT(4)}, + {"GBETSN_PGD0_PG_STS", BIT(5)}, + {"IOE_D2D_PGD2_PG_STS", BIT(6)}, + {"IOE_D2D_PGD1_PG_STS", BIT(7)}, + {"SPF_PGD0_PG_STS", BIT(8)}, + {"PMC_PGD1_PG_STS", BIT(9)}, + {} +}; + +const struct pmc_bit_map mtl_ioep_d3_status_0_map[] =3D { + {"SPF_D3_STS", BIT(0)}, + {"SPA_D3_STS", BIT(12)}, + {"SPB_D3_STS", BIT(13)}, + {"SPC_D3_STS", BIT(14)}, + {"SPD_D3_STS", BIT(15)}, + {"SPE_D3_STS", BIT(16)}, + {"DMI_D3_STS", BIT(22)}, + {} +}; + +const struct pmc_bit_map mtl_ioep_d3_status_1_map[] =3D { + {"GBETSN1_D3_STS", BIT(14)}, + {"P2S_D3_STS", BIT(24)}, + {} +}; + +const struct pmc_bit_map mtl_ioep_d3_status_2_map[] =3D { + {} +}; + +const struct pmc_bit_map mtl_ioep_d3_status_3_map[] =3D { + {"GBETSN_D3_STS", BIT(13)}, + {"ACE_D3_STS", BIT(23)}, + {} +}; + +const struct pmc_bit_map mtl_ioep_vnn_req_status_0_map[] =3D { + {"FIA_VNN_REQ_STS", BIT(17)}, + {} +}; + +const struct pmc_bit_map mtl_ioep_vnn_req_status_1_map[] =3D { + {"DFXAGG_VNN_REQ_STS", BIT(8)}, + {} +}; + +const struct pmc_bit_map mtl_ioep_vnn_req_status_2_map[] =3D { + {} +}; + +const struct pmc_bit_map mtl_ioep_vnn_req_status_3_map[] =3D { + {"DTS0_VNN_REQ_STS", BIT(7)}, + {"DISP_VNN_REQ_STS", BIT(19)}, + {} +}; + +const struct pmc_bit_map mtl_ioep_vnn_misc_status_map[] =3D { + {"CPU_C10_REQ_STS", BIT(0)}, + {"TS_OFF_REQ_STS", BIT(1)}, + {"PNDE_MET_REQ_STS", BIT(2)}, + {"PCIE_DEEP_PM_REQ_STS", BIT(3)}, + {"PMC_CLK_THROTTLE_EN_REQ_STS", BIT(4)}, + {"NPK_VNNAON_REQ_STS", BIT(5)}, + {"VNN_SOC_REQ_STS", BIT(6)}, + {"USB_DEVICE_ATTACHED_REQ_STS", BIT(8)}, + {"FIA_EXIT_REQ_STS", BIT(9)}, + {"USB2_SUS_PG_REQ_STS", BIT(10)}, + {"PLT_GREATER_REQ_STS", BIT(11)}, + {"PCIE_CLKREQ_REQ_STS", BIT(12)}, + {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13)}, + {"PM_SYNC_STATES_REQ_STS", BIT(14)}, + {"EA_REQ_STS", BIT(15)}, + {"MPHY_CORE_OFF_REQ_STS", BIT(16)}, + {"BRK_EV_EN_REQ_STS", BIT(17)}, + {"AUTO_DEMO_EN_REQ_STS", BIT(18)}, + {"ITSS_CLK_SRC_REQ_STS", BIT(19)}, + {"LPC_CLK_SRC_REQ_STS", BIT(20)}, + {"ARC_IDLE_REQ_STS", BIT(21)}, + {"MPHY_SUS_REQ_STS", BIT(22)}, + {"FIA_DEEP_PM_REQ_STS", BIT(23)}, + {"UXD_CONNECTED_REQ_STS", BIT(24)}, + {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25)}, + {"USB2_VNNAON_ACT_REQ_STS", BIT(26)}, + {"PRE_WAKE0_REQ_STS", BIT(27)}, + {"PRE_WAKE1_REQ_STS", BIT(28)}, + {"PRE_WAKE2_EN_REQ_STS", BIT(29)}, + {"WOV_REQ_STS", BIT(30)}, + {"CNVI_V1P05_REQ_STS", BIT(31)}, + {} +}; + +const struct pmc_bit_map *mtl_ioep_lpm_maps[] =3D { + mtl_ioep_clocksource_status_map, + mtl_ioep_power_gating_status_0_map, + mtl_ioep_power_gating_status_1_map, + mtl_ioep_power_gating_status_2_map, + mtl_ioep_d3_status_0_map, + mtl_ioep_d3_status_1_map, + mtl_ioep_d3_status_2_map, + mtl_ioep_d3_status_3_map, + mtl_ioep_vnn_req_status_0_map, + mtl_ioep_vnn_req_status_1_map, + mtl_ioep_vnn_req_status_2_map, + mtl_ioep_vnn_req_status_3_map, + mtl_ioep_vnn_misc_status_map, + mtl_socm_signal_status_map, + NULL +}; + +const struct pmc_reg_map mtl_ioep_reg_map =3D { + .regmap_length =3D MTL_IOE_PMC_MMIO_REG_LEN, + .pfear_sts =3D ext_mtl_ioep_pfear_map, + .ppfear0_offset =3D CNP_PMC_HOST_PPFEAR0A, + .ppfear_buckets =3D MTL_IOE_PPFEAR_NUM_ENTRIES, + .lpm_status_offset =3D MTL_LPM_STATUS_OFFSET, + .lpm_live_status_offset =3D MTL_LPM_LIVE_STATUS_OFFSET, + .lpm_sts =3D mtl_ioep_lpm_maps, + .ltr_show_sts =3D mtl_ioep_ltr_show_map, + .ltr_ignore_offset =3D CNP_PMC_LTR_IGNORE_OFFSET, + .ltr_ignore_max =3D ADL_NUM_IP_IGN_ALLOWED, +}; + #define PMC_DEVID_SOCM 0x7e7f +#define PMC_DEVID_IOEP 0x7ecf static struct pmc_info mtl_pmc_info_list[] =3D { { .devid =3D PMC_DEVID_SOCM, .map =3D &mtl_socm_reg_map, }, + { + .devid =3D PMC_DEVID_IOEP, + .map =3D &mtl_ioep_reg_map, + }, {} }; =20 --=20 2.25.1 From nobody Sat Feb 7 18:21:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69783EB64D8 for ; Tue, 13 Jun 2023 22:51:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241314AbjFMWvx (ORCPT ); Tue, 13 Jun 2023 18:51:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45286 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240428AbjFMWvm (ORCPT ); Tue, 13 Jun 2023 18:51:42 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C0107107; Tue, 13 Jun 2023 15:51:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686696700; x=1718232700; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0y2SXSYUlk74dD53z2Wh46+0OJbeHYYcJ6sfyOXUXL8=; b=mkCkTyNFULv+VrYm5sm25awZkKyN1Z/Zb8mFU7nJ005Gl+fJ1E/n7vxT /vXSrE5NpAjazGGeI5oxrKajaKqtXArjkzUp0sGfqjXEGO1GAVUUpYo+R DzHrDtunt+QeT4zk8uZp1hg7HnCHJJbI2ac74q9oNs5RSGd5EuZIbU6T4 tV/OhTUbLCpx04RPNhwmO4oeV4kLIZit8l1IJIBxdSS3EKlQ7Vv0q+8HX X+9y4r9AIbcX+c3meRYGU7QdXlWAOqjCX8Lv0tCoscSEWfi8nVxsDaybS MHzlXmQ7QWqbhrRJVrcokkV39AeA/C43PoawDFXkRFRJcXW/Xrp3oxPm+ g==; X-IronPort-AV: E=McAfee;i="6600,9927,10740"; a="444842204" X-IronPort-AV: E=Sophos;i="6.00,241,1681196400"; d="scan'208";a="444842204" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jun 2023 15:51:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10740"; a="824589655" X-IronPort-AV: E=Sophos;i="6.00,241,1681196400"; d="scan'208";a="824589655" Received: from linux.intel.com ([10.54.29.200]) by fmsmga002.fm.intel.com with ESMTP; 13 Jun 2023 15:51:39 -0700 Received: from rjingar-desk5.amr.corp.intel.com (hciettox-mobl.amr.corp.intel.com [10.212.23.107]) by linux.intel.com (Postfix) with ESMTP id 40262580BF8; Tue, 13 Jun 2023 15:51:39 -0700 (PDT) From: Rajvi Jingar To: david.e.box@linux.intel.com, ilpo.jarvinen@linux.intel.com, irenic.rajneesh@gmail.com, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, hdegoede@redhat.com Cc: xi.pardee@intel.com, Rajvi Jingar Subject: [PATCH 8/8] platform/x86:intel/pmc: Add Meteor Lake IOE-M PMC related maps Date: Tue, 13 Jun 2023 15:53:47 -0700 Message-Id: <20230613225347.2720665-9-rajvi.jingar@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613225347.2720665-1-rajvi.jingar@linux.intel.com> References: <20230613225347.2720665-1-rajvi.jingar@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xi Pardee Add device ID and register maps for the PMC in IO expansion die M in Meteor Lake. Signed-off-by: Xi Pardee Signed-off-by: Rajvi Jingar Reviewed-by: Ilpo J=C3=A4rvinen --- drivers/platform/x86/intel/pmc/core.h | 6 ++ drivers/platform/x86/intel/pmc/mtl.c | 145 ++++++++++++++++++++++++++ 2 files changed, 151 insertions(+) diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/i= ntel/pmc/core.h index 0c899efaa206..0729f593c6a7 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/drivers/platform/x86/intel/pmc/core.h @@ -478,6 +478,12 @@ extern const struct pmc_bit_map mtl_ioep_vnn_req_statu= s_3_map[]; extern const struct pmc_bit_map mtl_ioep_vnn_misc_status_map[]; extern const struct pmc_bit_map *mtl_ioep_lpm_maps[]; extern const struct pmc_reg_map mtl_ioep_reg_map; +extern const struct pmc_bit_map mtl_ioem_pfear_map[]; +extern const struct pmc_bit_map *ext_mtl_ioem_pfear_map[]; +extern const struct pmc_bit_map mtl_ioem_power_gating_status_1_map[]; +extern const struct pmc_bit_map mtl_ioem_vnn_req_status_1_map[]; +extern const struct pmc_bit_map *mtl_ioem_lpm_maps[]; +extern const struct pmc_reg_map mtl_ioem_reg_map; =20 extern void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev); extern int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value); diff --git a/drivers/platform/x86/intel/pmc/mtl.c b/drivers/platform/x86/in= tel/pmc/mtl.c index da3dba8c653b..2204bc666980 100644 --- a/drivers/platform/x86/intel/pmc/mtl.c +++ b/drivers/platform/x86/intel/pmc/mtl.c @@ -784,8 +784,149 @@ const struct pmc_reg_map mtl_ioep_reg_map =3D { .ltr_ignore_max =3D ADL_NUM_IP_IGN_ALLOWED, }; =20 +const struct pmc_bit_map mtl_ioem_pfear_map[] =3D { + {"PMC_0", BIT(0)}, + {"OPI", BIT(1)}, + {"TCSS", BIT(2)}, + {"RSVD3", BIT(3)}, + {"SPA", BIT(4)}, + {"SPB", BIT(5)}, + {"SPC", BIT(6)}, + {"IOE_D2D_3", BIT(7)}, + + {"RSVD8", BIT(0)}, + {"RSVD9", BIT(1)}, + {"SPE", BIT(2)}, + {"RSVD11", BIT(3)}, + {"RSVD12", BIT(4)}, + {"SPD", BIT(5)}, + {"ACE_7", BIT(6)}, + {"RSVD15", BIT(7)}, + + {"ACE_0", BIT(0)}, + {"FIACPCB_P", BIT(1)}, + {"P2S", BIT(2)}, + {"RSVD19", BIT(3)}, + {"ACE_8", BIT(4)}, + {"IOE_D2D_0", BIT(5)}, + {"FUSE", BIT(6)}, + {"RSVD23", BIT(7)}, + + {"FIACPCB_P5", BIT(0)}, + {"ACE_3", BIT(1)}, + {"RSF5", BIT(2)}, + {"ACE_2", BIT(3)}, + {"ACE_4", BIT(4)}, + {"RSVD29", BIT(5)}, + {"RSF10", BIT(6)}, + {"MPFPW5", BIT(7)}, + + {"PSF9", BIT(0)}, + {"MPFPW4", BIT(1)}, + {"RSVD34", BIT(2)}, + {"RSVD35", BIT(3)}, + {"RSVD36", BIT(4)}, + {"RSVD37", BIT(5)}, + {"RSVD38", BIT(6)}, + {"RSVD39", BIT(7)}, + + {"SBR0", BIT(0)}, + {"SBR1", BIT(1)}, + {"SBR2", BIT(2)}, + {"SBR3", BIT(3)}, + {"SBR4", BIT(4)}, + {"RSVD45", BIT(5)}, + {"RSVD46", BIT(6)}, + {"RSVD47", BIT(7)}, + + {"RSVD48", BIT(0)}, + {"FIA_P5", BIT(1)}, + {"RSVD50", BIT(2)}, + {"RSVD51", BIT(3)}, + {"RSVD52", BIT(4)}, + {"RSVD53", BIT(5)}, + {"RSVD54", BIT(6)}, + {"ACE_1", BIT(7)}, + + {"RSVD56", BIT(0)}, + {"ACE_5", BIT(1)}, + {"RSVD58", BIT(2)}, + {"G5FPW1", BIT(3)}, + {"RSVD60", BIT(4)}, + {"ACE_6", BIT(5)}, + {"RSVD62", BIT(6)}, + {"GBETSN1", BIT(7)}, + + {"RSVD64", BIT(0)}, + {"FIA", BIT(1)}, + {"RSVD66", BIT(2)}, + {"FIA_P", BIT(3)}, + {"TAM", BIT(4)}, + {"GBETSN", BIT(5)}, + {"IOE_D2D_2", BIT(6)}, + {"IOE_D2D_1", BIT(7)}, + + {"SPF", BIT(0)}, + {"PMC_1", BIT(1)}, + {} +}; + +const struct pmc_bit_map *ext_mtl_ioem_pfear_map[] =3D { + mtl_ioem_pfear_map, + NULL +}; + +const struct pmc_bit_map mtl_ioem_power_gating_status_1_map[] =3D { + {"PSF9_PGD0_PG_STS", BIT(0)}, + {"MPFPW4_PGD0_PG_STS", BIT(1)}, + {"SBR0_PGD0_PG_STS", BIT(8)}, + {"SBR1_PGD0_PG_STS", BIT(9)}, + {"SBR2_PGD0_PG_STS", BIT(10)}, + {"SBR3_PGD0_PG_STS", BIT(11)}, + {"SBR4_PGD0_PG_STS", BIT(12)}, + {"FIA_P5_PGD0_PG_STS", BIT(17)}, + {"ACE_PGD1_PGD0_PG_STS", BIT(23)}, + {"ACE_PGD5_PGD1_PG_STS", BIT(25)}, + {"G5FPW1_PGD0_PG_STS", BIT(27)}, + {"ACE_PGD6_PG_STS", BIT(29)}, + {"GBETSN1_PGD0_PG_STS", BIT(31)}, + {} +}; + +const struct pmc_bit_map *mtl_ioem_lpm_maps[] =3D { + mtl_ioep_clocksource_status_map, + mtl_ioep_power_gating_status_0_map, + mtl_ioem_power_gating_status_1_map, + mtl_ioep_power_gating_status_2_map, + mtl_ioep_d3_status_0_map, + mtl_ioep_d3_status_1_map, + mtl_ioep_d3_status_2_map, + mtl_ioep_d3_status_3_map, + mtl_ioep_vnn_req_status_0_map, + mtl_ioep_vnn_req_status_1_map, + mtl_ioep_vnn_req_status_2_map, + mtl_ioep_vnn_req_status_3_map, + mtl_ioep_vnn_misc_status_map, + mtl_socm_signal_status_map, + NULL +}; + +const struct pmc_reg_map mtl_ioem_reg_map =3D { + .regmap_length =3D MTL_IOE_PMC_MMIO_REG_LEN, + .pfear_sts =3D ext_mtl_ioem_pfear_map, + .ppfear0_offset =3D CNP_PMC_HOST_PPFEAR0A, + .ppfear_buckets =3D MTL_IOE_PPFEAR_NUM_ENTRIES, + .lpm_status_offset =3D MTL_LPM_STATUS_OFFSET, + .lpm_live_status_offset =3D MTL_LPM_LIVE_STATUS_OFFSET, + .lpm_sts =3D mtl_ioem_lpm_maps, + .ltr_show_sts =3D mtl_ioep_ltr_show_map, + .ltr_ignore_offset =3D CNP_PMC_LTR_IGNORE_OFFSET, + .ltr_ignore_max =3D ADL_NUM_IP_IGN_ALLOWED, +}; + #define PMC_DEVID_SOCM 0x7e7f #define PMC_DEVID_IOEP 0x7ecf +#define PMC_DEVID_IOEM 0x7ebf static struct pmc_info mtl_pmc_info_list[] =3D { { .devid =3D PMC_DEVID_SOCM, @@ -795,6 +936,10 @@ static struct pmc_info mtl_pmc_info_list[] =3D { .devid =3D PMC_DEVID_IOEP, .map =3D &mtl_ioep_reg_map, }, + { + .devid =3D PMC_DEVID_IOEM, + .map =3D &mtl_ioem_reg_map + }, {} }; =20 --=20 2.25.1