From nobody Tue Feb 10 03:00:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24D93EB64D7 for ; Tue, 13 Jun 2023 15:35:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242659AbjFMPfU (ORCPT ); Tue, 13 Jun 2023 11:35:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51120 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243030AbjFMPe7 (ORCPT ); Tue, 13 Jun 2023 11:34:59 -0400 Received: from mail-ot1-x32a.google.com (mail-ot1-x32a.google.com [IPv6:2607:f8b0:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BA6971BF5 for ; Tue, 13 Jun 2023 08:34:57 -0700 (PDT) Received: by mail-ot1-x32a.google.com with SMTP id 46e09a7af769-6b2d356530eso2527625a34.0 for ; Tue, 13 Jun 2023 08:34:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1686670497; x=1689262497; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZOjDepVi55uZJQ1rIBBnqb1diEnF/zfemFV4q9wl2F4=; b=U5BTnUgsTyY025LPTSIEtoOzq7Q5o4OaIfC8F2Cp2IROKg2fRfgHDM4sZ4TvWZ5Veg 4PJ5oydrNtKpPWusb4NoyM/So2Jll85MZcKY7Vsy5rFWcEls/V0dxd9Tew9sIIUFFSKt xEwCseQQ5euG9gDwbuVb3ufZf9zX6eAE+4GoYL9dODsw6QTs1RNd+dF8OmQW2vgSRqEJ cn6CrVgS9jx5QarEWuD+HvhHRgv7OVIEgH0MYqsHHWlQRaDvLA/qs3zrG3TSDO3CMJI1 +mMxnxnp8wk2Oqs1XngO0t3lXFYPqPVh1gpGqRHs7kMQWZUTfFSIfpGIS2UspVEFiNVq syKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686670497; x=1689262497; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZOjDepVi55uZJQ1rIBBnqb1diEnF/zfemFV4q9wl2F4=; b=Y4SKusbXE4jBRAapFJp4SQhvU5rYwochPrUVPVF5Q6aJmok+LHLG/3gwR2K8yoruOH z5Oxv6LWD3Kje0b3AoJif3Q1q6o+zBdkjNOPF57WwmaiQFUqMDD3HM5AI0qwXA+jruB6 sAZiVq/WKHCw5vMZBlGTbwLlrHkFCoc9CWUJyUZCdTUIv2lUV1rO2A4fHYJkC5dpQ5nR mzWRkOR07MWj0wono6h4BDHu7lM6KjbDQ/gBZs/9FA25omTlBoIaPz1MZuMxpIZ1KkjS HcegdOL3FhbuWsYFea3x6PmGstZzGy/sYaOmkptcyKFraQ2mPqV5UsFmRZ2xHpTQWhPf qfHg== X-Gm-Message-State: AC+VfDzYQPuOD3NtcoMKDgfxsncwbShF/Ng67zO4ifc5Oc7xlnJQDBKw 8Rf1ueD+Mp+go8q5Ld4saOlNTg== X-Google-Smtp-Source: ACHHUZ6eEEH2tZGnWyfL2JM6W9G1jWDPuHoKWDYlu23+MeGJOg+ZOhZIVTB6M16ZPNTFpEhRqJToXQ== X-Received: by 2002:a05:6808:87:b0:398:f48:eb4 with SMTP id s7-20020a056808008700b003980f480eb4mr6987321oic.36.1686670496674; Tue, 13 Jun 2023 08:34:56 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id n2-20020acabd02000000b0039ce305ea4fsm1630807oif.14.2023.06.13.08.34.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jun 2023 08:34:56 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Robin Murphy , Joerg Roedel , Will Deacon , Frank Rowand Cc: Atish Patra , Andrew Jones , Conor Dooley , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, iommu@lists.linux.dev, Anup Patel , Conor Dooley , Krzysztof Kozlowski Subject: [PATCH v4 03/10] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Date: Tue, 13 Jun 2023 21:04:08 +0530 Message-Id: <20230613153415.350528-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230613153415.350528-1-apatel@ventanamicro.com> References: <20230613153415.350528-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We add DT bindings document for the RISC-V incoming MSI controller (IMSIC) defined by the RISC-V advanced interrupt architecture (AIA) specification. Signed-off-by: Anup Patel Reviewed-by: Conor Dooley Acked-by: Krzysztof Kozlowski --- .../interrupt-controller/riscv,imsics.yaml | 172 ++++++++++++++++++ 1 file changed, 172 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= riscv,imsics.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,i= msics.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,i= msics.yaml new file mode 100644 index 000000000000..84976f17a4a1 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.y= aml @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V Incoming MSI Controller (IMSIC) + +maintainers: + - Anup Patel + +description: | + The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incom= ing + MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V + AIA specification can be found at https://github.com/riscv/riscv-aia. + + The IMSIC is a per-CPU (or per-HART) device with separate interrupt file + for each privilege level (machine or supervisor). The configuration of + a IMSIC interrupt file is done using AIA CSRs and it also has a 4KB MMIO + space to receive MSIs from devices. Each IMSIC interrupt file supports a + fixed number of interrupt identities (to distinguish MSIs from devices) + which is same for given privilege level across CPUs (or HARTs). + + The device tree of a RISC-V platform will have one IMSIC device tree node + for each privilege level (machine or supervisor) which collectively desc= ribe + IMSIC interrupt files at that privilege level across CPUs (or HARTs). + + The arrangement of IMSIC interrupt files in MMIO space of a RISC-V platf= orm + follows a particular scheme defined by the RISC-V AIA specification. A I= MSIC + group is a set of IMSIC interrupt files co-located in MMIO space and we = can + have multiple IMSIC groups (i.e. clusters, sockets, chiplets, etc) in a + RISC-V platform. The MSI target address of a IMSIC interrupt file at giv= en + privilege level (machine or supervisor) encodes group index, HART index, + and guest index (shown below). + + XLEN-1 > (HART Index MSB) 12 0 + | | | | + ------------------------------------------------------------- + |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 | + ------------------------------------------------------------- + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + items: + - enum: + - qemu,imsics + - const: riscv,imsics + + reg: + minItems: 1 + maxItems: 16384 + description: + Base address of each IMSIC group. + + interrupt-controller: true + + "#interrupt-cells": + const: 0 + + msi-controller: true + + "#msi-cells": + const: 0 + + interrupts-extended: + minItems: 1 + maxItems: 16384 + description: + This property represents the set of CPUs (or HARTs) for which given + device tree node describes the IMSIC interrupt files. Each node poin= ted + to should be a riscv,cpu-intc node, which has a CPU node (i.e. RISC-V + HART) as parent. + + riscv,num-ids: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 63 + maximum: 2047 + description: + Number of interrupt identities supported by IMSIC interrupt file. + + riscv,num-guest-ids: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 63 + maximum: 2047 + description: + Number of interrupt identities are supported by IMSIC guest interrupt + file. When not specified it is assumed to be same as specified by the + riscv,num-ids property. + + riscv,guest-index-bits: + minimum: 0 + maximum: 7 + default: 0 + description: + Number of guest index bits in the MSI target address. + + riscv,hart-index-bits: + minimum: 0 + maximum: 15 + description: + Number of HART index bits in the MSI target address. When not + specified it is calculated based on the interrupts-extended property. + + riscv,group-index-bits: + minimum: 0 + maximum: 7 + default: 0 + description: + Number of group index bits in the MSI target address. + + riscv,group-index-shift: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 55 + default: 24 + description: + The least significant bit position of the group index bits in the + MSI target address. + +required: + - compatible + - reg + - interrupt-controller + - msi-controller + - "#msi-cells" + - interrupts-extended + - riscv,num-ids + +unevaluatedProperties: false + +examples: + - | + // Example 1 (Machine-level IMSIC files with just one group): + + interrupt-controller@24000000 { + compatible =3D "qemu,imsics", "riscv,imsics"; + interrupts-extended =3D <&cpu1_intc 11>, + <&cpu2_intc 11>, + <&cpu3_intc 11>, + <&cpu4_intc 11>; + reg =3D <0x28000000 0x4000>; + interrupt-controller; + #interrupt-cells =3D <0>; + msi-controller; + #msi-cells =3D <0>; + riscv,num-ids =3D <127>; + }; + + - | + // Example 2 (Supervisor-level IMSIC files with two groups): + + interrupt-controller@28000000 { + compatible =3D "qemu,imsics", "riscv,imsics"; + interrupts-extended =3D <&cpu1_intc 9>, + <&cpu2_intc 9>, + <&cpu3_intc 9>, + <&cpu4_intc 9>; + reg =3D <0x28000000 0x2000>, /* Group0 IMSICs */ + <0x29000000 0x2000>; /* Group1 IMSICs */ + interrupt-controller; + #interrupt-cells =3D <0>; + msi-controller; + #msi-cells =3D <0>; + riscv,num-ids =3D <127>; + riscv,group-index-bits =3D <1>; + riscv,group-index-shift =3D <24>; + }; +... --=20 2.34.1