From nobody Fri Sep 20 16:48:19 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E621C7EE25 for ; Mon, 12 Jun 2023 09:05:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232866AbjFLJF5 (ORCPT ); Mon, 12 Jun 2023 05:05:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60208 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232029AbjFLJFX (ORCPT ); Mon, 12 Jun 2023 05:05:23 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 45E313C03 for ; Mon, 12 Jun 2023 02:02:04 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (unknown [IPv6:2001:b07:2ed:14ed:c5f8:7372:f042:90a2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id A694D66058B2; Mon, 12 Jun 2023 10:02:02 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1686560523; bh=fWabP2S9MKC6+Yi0YWqUcPZxSafl399il5KPixyXdlw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=M+g8uCwRld+dEIgLpeT51k38xPkIwZ517PJ1IwwI3HjXA3biUFFsqhVM+0kXSOsCY jp3sGEQStYgWLdwzB7UW5gQ+rxTyrVOHH/Hp1XRl6rPCA6msNG8ogbCYBfT5lWc449 R4LthY1KY1lfj+mxQXwex2ZMYO7nkTc84SQeSCH3NzK0Xebo+7m9P9zL19Itu+UVFa LE5A3bREWcVtq/4J8lBhB+mnpIQ+lUO6rjeNZ0XdUlxQ/2R3VzYboeht2lKeov3EIn OnZTH5RSnTyQbEtEFb8kgZEeSAel0eqLCctjeEY9ujefARO55cl2u80ybpU096VNIo mOHxluPFzqXPQ== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, "Jason-JH.Lin" Subject: [PATCH v6 01/11] drm/mediatek: gamma: Adjust mtk_drm_gamma_set_common parameters Date: Mon, 12 Jun 2023 11:01:47 +0200 Message-Id: <20230612090157.68205-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230612090157.68205-1-angelogioacchino.delregno@collabora.com> References: <20230612090157.68205-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: "Jason-JH.Lin" Adjust the parameters in mtk_drm_gamma_set_common() - add (struct device *dev) to get lut_diff from gamma's driver data - remove (bool lut_diff) and use false as default value in the function Signed-off-by: Jason-JH.Lin Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 2 +- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 2 +- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 15 +++++++++------ 3 files changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/medi= atek/mtk_disp_aal.c index 434e8a9ce8ab..8ddf7a97e583 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -67,7 +67,7 @@ void mtk_aal_gamma_set(struct device *dev, struct drm_crt= c_state *state) struct mtk_disp_aal *aal =3D dev_get_drvdata(dev); =20 if (aal->data && aal->data->has_gamma) - mtk_gamma_set_common(aal->regs, state, false); + mtk_gamma_set_common(NULL, aal->regs, state); } =20 void mtk_aal_start(struct device *dev) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/medi= atek/mtk_disp_drv.h index 2254038519e1..75045932353e 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -54,7 +54,7 @@ void mtk_gamma_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state); -void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state= , bool lut_diff); +void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct d= rm_crtc_state *state); void mtk_gamma_start(struct device *dev); void mtk_gamma_stop(struct device *dev); =20 diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index c844942603f7..99be515a941b 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -55,14 +55,21 @@ void mtk_gamma_clk_disable(struct device *dev) clk_disable_unprepare(gamma->clk); } =20 -void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state= , bool lut_diff) +void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct d= rm_crtc_state *state) { + struct mtk_disp_gamma *gamma =3D dev_get_drvdata(dev); unsigned int i, reg; struct drm_color_lut *lut; void __iomem *lut_base; + bool lut_diff; u32 word; u32 diff[3] =3D {0}; =20 + if (gamma && gamma->data) + lut_diff =3D gamma->data->lut_diff; + else + lut_diff =3D false; + if (state->gamma_lut) { reg =3D readl(regs + DISP_GAMMA_CFG); reg =3D reg | GAMMA_LUT_EN; @@ -92,12 +99,8 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm= _crtc_state *state, bool void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) { struct mtk_disp_gamma *gamma =3D dev_get_drvdata(dev); - bool lut_diff =3D false; - - if (gamma->data) - lut_diff =3D gamma->data->lut_diff; =20 - mtk_gamma_set_common(gamma->regs, state, lut_diff); + mtk_gamma_set_common(dev, gamma->regs, state); } =20 void mtk_gamma_config(struct device *dev, unsigned int w, --=20 2.40.1 From nobody Fri Sep 20 16:48:19 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4273C7EE23 for ; Mon, 12 Jun 2023 09:06:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230156AbjFLJGA (ORCPT ); Mon, 12 Jun 2023 05:06:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60244 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232978AbjFLJFZ (ORCPT ); Mon, 12 Jun 2023 05:05:25 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A791E3C0E for ; Mon, 12 Jun 2023 02:02:05 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (unknown [IPv6:2001:b07:2ed:14ed:c5f8:7372:f042:90a2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 9DC226606E98; Mon, 12 Jun 2023 10:02:03 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1686560524; bh=H1IjE6ks2/tQ62I5k+mdDy0LWtBtFX34NVlBCrVhdQQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aY658Q+0Pi1xzDSNlEuUHVLmbLxgSQzTuQ1rn4R9okTSDsKzZcjtMgyKxKNrxIBmb SeL9adZxHbCIHp4YIplc2SBlGGUSJrIF4vWoHTBwD7XpoSyNJSShL/byRlgLFwFCJt q/1HHD8rdCMbbGAWSw2PVb835Nf2G1J4s1L+sgz0iEZm8XMUEksUod6dUo+JwI3kVL eKIEbITYzKrz3e7D3LOPTXOcQEVGtoBSrTaFBG9mpf+W33lMs4A5ZPS1c13lpFK/EH X3VRzfq6ly881hcHDyemwEXJadguxj2ONDcOIpHSdlOu5iSp9i2r5bT3xPWKR/kzJL KvqSS5oVCJLOw== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, "Jason-JH . Lin" Subject: [PATCH v6 02/11] drm/mediatek: gamma: Reduce indentation in mtk_gamma_set_common() Date: Mon, 12 Jun 2023 11:01:48 +0200 Message-Id: <20230612090157.68205-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230612090157.68205-1-angelogioacchino.delregno@collabora.com> References: <20230612090157.68205-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Invert the check for state->gamma_lut and move it at the beginning of the function to reduce indentation: this prepares the code for keeping readability on later additions. This commit brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 45 ++++++++++++----------- 1 file changed, 23 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index 99be515a941b..ce6f2499b891 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -65,34 +65,35 @@ void mtk_gamma_set_common(struct device *dev, void __io= mem *regs, struct drm_crt u32 word; u32 diff[3] =3D {0}; =20 + /* If there's no gamma lut there's nothing to do here. */ + if (!state->gamma_lut) + return; + if (gamma && gamma->data) lut_diff =3D gamma->data->lut_diff; else lut_diff =3D false; =20 - if (state->gamma_lut) { - reg =3D readl(regs + DISP_GAMMA_CFG); - reg =3D reg | GAMMA_LUT_EN; - writel(reg, regs + DISP_GAMMA_CFG); - lut_base =3D regs + DISP_GAMMA_LUT; - lut =3D (struct drm_color_lut *)state->gamma_lut->data; - for (i =3D 0; i < MTK_LUT_SIZE; i++) { - - if (!lut_diff || (i % 2 =3D=3D 0)) { - word =3D (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + - (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + - ((lut[i].blue >> 6) & LUT_10BIT_MASK); - } else { - diff[0] =3D (lut[i].red >> 6) - (lut[i - 1].red >> 6); - diff[1] =3D (lut[i].green >> 6) - (lut[i - 1].green >> 6); - diff[2] =3D (lut[i].blue >> 6) - (lut[i - 1].blue >> 6); - - word =3D ((diff[0] & LUT_10BIT_MASK) << 20) + - ((diff[1] & LUT_10BIT_MASK) << 10) + - (diff[2] & LUT_10BIT_MASK); - } - writel(word, (lut_base + i * 4)); + reg =3D readl(regs + DISP_GAMMA_CFG); + reg =3D reg | GAMMA_LUT_EN; + writel(reg, regs + DISP_GAMMA_CFG); + lut_base =3D regs + DISP_GAMMA_LUT; + lut =3D (struct drm_color_lut *)state->gamma_lut->data; + for (i =3D 0; i < MTK_LUT_SIZE; i++) { + if (!lut_diff || (i % 2 =3D=3D 0)) { + word =3D (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + + (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + + ((lut[i].blue >> 6) & LUT_10BIT_MASK); + } else { + diff[0] =3D (lut[i].red >> 6) - (lut[i - 1].red >> 6); + diff[1] =3D (lut[i].green >> 6) - (lut[i - 1].green >> 6); + diff[2] =3D (lut[i].blue >> 6) - (lut[i - 1].blue >> 6); + + word =3D ((diff[0] & LUT_10BIT_MASK) << 20) + + ((diff[1] & LUT_10BIT_MASK) << 10) + + (diff[2] & LUT_10BIT_MASK); } + writel(word, (lut_base + i * 4)); } } =20 --=20 2.40.1 From nobody Fri Sep 20 16:48:19 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68E10C7EE23 for ; Mon, 12 Jun 2023 09:06:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233634AbjFLJGF (ORCPT ); Mon, 12 Jun 2023 05:06:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60260 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233006AbjFLJFZ (ORCPT ); Mon, 12 Jun 2023 05:05:25 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8DC633C12 for ; Mon, 12 Jun 2023 02:02:06 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (unknown [IPv6:2001:b07:2ed:14ed:c5f8:7372:f042:90a2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 8F67F6606E8A; Mon, 12 Jun 2023 10:02:04 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1686560525; bh=uez5eoRMhsgOOXOBI1JFSa4MIzsNoJQ/JLxh/1eaBjc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Kf1in0PVgibpp6kMU+DotdjTYPuyGy1jnjIQCqtDyGf2mn4jBFeQNhGTrUfWCWYZA QBe0nCeoxwROcl1h2SDuK0v8g/ZMx3MgnmHR1xk1h2h0To8lSo3eOITSZOcbgGRUrO LYY+4v3Dn1KFs88zX34klHkU2qho4Jo/F7WlHljbfJnsEWMEi8tvnwxxWyZlE5bgww XfqJT7YSZng5DpMddJvlfYEy2QZTCBmP65n14tlf9lMF54j+FeQFjEz94kWkZEPTJo dFVm8y2kSPaEjPjLftlazocew7FAXFIyRERFMl5N7rG//arSbB3G8EdtTnGE/ZI2Mo RMM3yNmxquaQA== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, "Jason-JH . Lin" Subject: [PATCH v6 03/11] drm/mediatek: gamma: Support SoC specific LUT size Date: Mon, 12 Jun 2023 11:01:49 +0200 Message-Id: <20230612090157.68205-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230612090157.68205-1-angelogioacchino.delregno@collabora.com> References: <20230612090157.68205-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Newer SoCs support a bigger Gamma LUT table: wire up a callback to retrieve the correct LUT size for each different Gamma IP. Co-developed-by: Jason-JH.Lin Signed-off-by: Jason-JH.Lin [Angelo: Rewritten commit message/description + porting] Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin --- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 1 + drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 25 ++++++++++++++++++--- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 4 ++-- drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 1 - drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 ++++++++ 6 files changed, 35 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/medi= atek/mtk_disp_drv.h index 75045932353e..e554b19f4830 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -53,6 +53,7 @@ void mtk_gamma_clk_disable(struct device *dev); void mtk_gamma_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +unsigned int mtk_gamma_get_lut_size(struct device *dev); void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state); void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct d= rm_crtc_state *state); void mtk_gamma_start(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index ce6f2499b891..b25ba209e7a4 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -25,10 +25,12 @@ #define DISP_GAMMA_LUT 0x0700 =20 #define LUT_10BIT_MASK 0x03ff +#define LUT_SIZE_DEFAULT 512 =20 struct mtk_disp_gamma_data { bool has_dither; bool lut_diff; + u16 lut_size; }; =20 /* @@ -55,6 +57,17 @@ void mtk_gamma_clk_disable(struct device *dev) clk_disable_unprepare(gamma->clk); } =20 +unsigned int mtk_gamma_get_lut_size(struct device *dev) +{ + struct mtk_disp_gamma *gamma =3D dev_get_drvdata(dev); + unsigned int lut_size =3D LUT_SIZE_DEFAULT; + + if (gamma && gamma->data) + lut_size =3D gamma->data->lut_size; + + return lut_size; +} + void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct d= rm_crtc_state *state) { struct mtk_disp_gamma *gamma =3D dev_get_drvdata(dev); @@ -62,6 +75,7 @@ void mtk_gamma_set_common(struct device *dev, void __iome= m *regs, struct drm_crt struct drm_color_lut *lut; void __iomem *lut_base; bool lut_diff; + u16 lut_size; u32 word; u32 diff[3] =3D {0}; =20 @@ -69,17 +83,20 @@ void mtk_gamma_set_common(struct device *dev, void __io= mem *regs, struct drm_crt if (!state->gamma_lut) return; =20 - if (gamma && gamma->data) + if (gamma && gamma->data) { lut_diff =3D gamma->data->lut_diff; - else + lut_size =3D gamma->data->lut_size; + } else { lut_diff =3D false; + lut_size =3D LUT_SIZE_DEFAULT; + } =20 reg =3D readl(regs + DISP_GAMMA_CFG); reg =3D reg | GAMMA_LUT_EN; writel(reg, regs + DISP_GAMMA_CFG); lut_base =3D regs + DISP_GAMMA_LUT; lut =3D (struct drm_color_lut *)state->gamma_lut->data; - for (i =3D 0; i < MTK_LUT_SIZE; i++) { + for (i =3D 0; i < lut_size; i++) { if (!lut_diff || (i % 2 =3D=3D 0)) { word =3D (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + @@ -196,10 +213,12 @@ static int mtk_disp_gamma_remove(struct platform_devi= ce *pdev) =20 static const struct mtk_disp_gamma_data mt8173_gamma_driver_data =3D { .has_dither =3D true, + .lut_size =3D 512, }; =20 static const struct mtk_disp_gamma_data mt8183_gamma_driver_data =3D { .lut_diff =3D true, + .lut_size =3D 512, }; =20 static const struct of_device_id mtk_disp_gamma_driver_dt_match[] =3D { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/medi= atek/mtk_drm_crtc.c index d40142842f85..0df62b076f49 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -958,8 +958,8 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, mtk_crtc->ddp_comp[i] =3D comp; =20 if (comp->funcs) { - if (comp->funcs->gamma_set) - gamma_lut_size =3D MTK_LUT_SIZE; + if (comp->funcs->gamma_set && comp->funcs->gamma_get_lut_size) + gamma_lut_size =3D mtk_ddp_gamma_get_lut_size(comp); =20 if (comp->funcs->ctm_set) has_ctm =3D true; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/medi= atek/mtk_drm_crtc.h index 3e9046993d09..b2e50292e57d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h @@ -10,7 +10,6 @@ #include "mtk_drm_ddp_comp.h" #include "mtk_drm_plane.h" =20 -#define MTK_LUT_SIZE 512 #define MTK_MAX_BPC 10 #define MTK_MIN_BPC 3 =20 diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/= mediatek/mtk_drm_ddp_comp.c index f114da4d36a9..c77af2e4000f 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -322,6 +322,7 @@ static const struct mtk_ddp_comp_funcs ddp_dsi =3D { static const struct mtk_ddp_comp_funcs ddp_gamma =3D { .clk_enable =3D mtk_gamma_clk_enable, .clk_disable =3D mtk_gamma_clk_disable, + .gamma_get_lut_size =3D mtk_gamma_get_lut_size, .gamma_set =3D mtk_gamma_set, .config =3D mtk_gamma_config, .start =3D mtk_gamma_start, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/= mediatek/mtk_drm_ddp_comp.h index febcaeef16a1..c1355960e195 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -67,6 +67,7 @@ struct mtk_ddp_comp_funcs { void (*layer_config)(struct device *dev, unsigned int idx, struct mtk_plane_state *state, struct cmdq_pkt *cmdq_pkt); + unsigned int (*gamma_get_lut_size)(struct device *dev); void (*gamma_set)(struct device *dev, struct drm_crtc_state *state); void (*bgclr_in_on)(struct device *dev); @@ -186,6 +187,14 @@ static inline void mtk_ddp_comp_layer_config(struct mt= k_ddp_comp *comp, comp->funcs->layer_config(comp->dev, idx, state, cmdq_pkt); } =20 +static inline unsigned int mtk_ddp_gamma_get_lut_size(struct mtk_ddp_comp = *comp) +{ + if (comp->funcs && comp->funcs->gamma_get_lut_size) + return comp->funcs->gamma_get_lut_size(comp->dev); + + return 0; +} + static inline void mtk_ddp_gamma_set(struct mtk_ddp_comp *comp, struct drm_crtc_state *state) { --=20 2.40.1 From nobody Fri Sep 20 16:48:19 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1F05C7EE25 for ; Mon, 12 Jun 2023 09:06:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229610AbjFLJGI (ORCPT ); Mon, 12 Jun 2023 05:06:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60250 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233067AbjFLJFZ (ORCPT ); Mon, 12 Jun 2023 05:05:25 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 70D873C15 for ; Mon, 12 Jun 2023 02:02:07 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (unknown [IPv6:2001:b07:2ed:14ed:c5f8:7372:f042:90a2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 84B636605907; Mon, 12 Jun 2023 10:02:05 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1686560526; bh=JI4lc9a8QXR5NBTwDSozQ6dg2sDhEor4ZM5gg2fngeU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gKQFxjdnH+vl70AlE44leMWTR2HIoRGjg1Oz2C9D8tXWCbGNiKIHuwHjJP78Wpl3t zf9Wu4CR22LvV5JYJGtLuCcO7xqRI6s2nc+b3kdppAVZ20gHUOGSsC3Qtg3gj6do3c 6pciq9MW4DrH905coZp1e0GXtDCEqmR6xv98wfYZzgydVEpRXvBbij17X+1g5y3BMP CA9YLG8zm5Yy6XSps/c5+yzQCYU6Tfx4bhF4tgZ9EGV+t7mcvFp6Y/z4fjPL5+HuhM NMg4I7wxlKEFT9pC1eddEkdHzL+fQeBMmC9/Q5FJrvLM1juWtlKafTqgQ5KkcdECQG rT5xCXXiW/+3A== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, "Jason-JH . Lin" Subject: [PATCH v6 04/11] drm/mediatek: gamma: Improve and simplify HW LUT calculation Date: Mon, 12 Jun 2023 11:01:50 +0200 Message-Id: <20230612090157.68205-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230612090157.68205-1-angelogioacchino.delregno@collabora.com> References: <20230612090157.68205-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use drm_color_lut_extract() to avoid open-coding the bits reduction calculations for each color channel and use a struct drm_color_lut to temporarily store the information instead of an array of u32. Also, slightly improve the precision of the HW LUT calculation in the LUT DIFF case by performing the subtractions on the 16-bits values and doing the 10 bits conversion later. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 30 +++++++++++++++-------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index b25ba209e7a4..204a1aa7bfc9 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -77,7 +77,6 @@ void mtk_gamma_set_common(struct device *dev, void __iome= m *regs, struct drm_crt bool lut_diff; u16 lut_size; u32 word; - u32 diff[3] =3D {0}; =20 /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) @@ -97,18 +96,29 @@ void mtk_gamma_set_common(struct device *dev, void __io= mem *regs, struct drm_crt lut_base =3D regs + DISP_GAMMA_LUT; lut =3D (struct drm_color_lut *)state->gamma_lut->data; for (i =3D 0; i < lut_size; i++) { + struct drm_color_lut diff, hwlut; + + hwlut.red =3D drm_color_lut_extract(lut[i].red, 10); + hwlut.green =3D drm_color_lut_extract(lut[i].green, 10); + hwlut.blue =3D drm_color_lut_extract(lut[i].blue, 10); + if (!lut_diff || (i % 2 =3D=3D 0)) { - word =3D (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + - (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + - ((lut[i].blue >> 6) & LUT_10BIT_MASK); + word =3D hwlut.red << 20 + + hwlut.green << 10 + + hwlut.red; } else { - diff[0] =3D (lut[i].red >> 6) - (lut[i - 1].red >> 6); - diff[1] =3D (lut[i].green >> 6) - (lut[i - 1].green >> 6); - diff[2] =3D (lut[i].blue >> 6) - (lut[i - 1].blue >> 6); + diff.red =3D lut[i].red - lut[i - 1].red; + diff.red =3D drm_color_lut_extract(diff.red, 10); + + diff.green =3D lut[i].green - lut[i - 1].green; + diff.green =3D drm_color_lut_extract(diff.green, 10); + + diff.blue =3D lut[i].blue - lut[i - 1].blue; + diff.blue =3D drm_color_lut_extract(diff.blue, 10); =20 - word =3D ((diff[0] & LUT_10BIT_MASK) << 20) + - ((diff[1] & LUT_10BIT_MASK) << 10) + - (diff[2] & LUT_10BIT_MASK); + word =3D diff.blue << 20 + + diff.green << 10 + + diff.red; } writel(word, (lut_base + i * 4)); } --=20 2.40.1 From nobody Fri Sep 20 16:48:19 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14A8EC7EE23 for ; Mon, 12 Jun 2023 09:06:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234030AbjFLJGP (ORCPT ); Mon, 12 Jun 2023 05:06:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233303AbjFLJFb (ORCPT ); Mon, 12 Jun 2023 05:05:31 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6750146BF for ; Mon, 12 Jun 2023 02:02:11 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (unknown [IPv6:2001:b07:2ed:14ed:c5f8:7372:f042:90a2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 79CF36606E9D; Mon, 12 Jun 2023 10:02:06 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1686560527; bh=IbtbZnmCWfYYE0XVFaNK/WT77zqaqxGqnAMw0WmBnlE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fOZ+cMvlC7LPQw3IUHgrca2Y3UJFFHIarko5dKxkeZvwQluJ9V64iPkSJ12/fft+w fp2sC69cArZ4zyPdrMnAlu0b7QQZt+uwFICPBiuEJEzSjixccZgepcel6tgUUbvNv7 9tzJTLPZnDJ4zEa4uIb1eqlv3waE2CRqRt7tPFEH5ref61MAeWmfSgonA+QDijzzeB /YlCm/HD3jtN3Cr2GJ4ei0mQQZdGlpyJr+AdoPAM8SqU8zQ/QOz7SYSKR5v4p6Ek8n bQCkPMQguRwkA6vlvaEkvOsLo+S+JavwxiBg+A7oo0tnJCJA8C0EBlHgmaBT2niT6q 0EvVJV2W6vRGA== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, "Jason-JH . Lin" Subject: [PATCH v6 05/11] drm/mediatek: gamma: Enable the Gamma LUT table only after programming Date: Mon, 12 Jun 2023 11:01:51 +0200 Message-Id: <20230612090157.68205-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230612090157.68205-1-angelogioacchino.delregno@collabora.com> References: <20230612090157.68205-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Move the write to DISP_GAMMA_CFG to enable the Gamma LUT to after programming the actual table to avoid potential visual glitches during table modification. Note: GAMMA should get enabled in between vblanks, but this requires many efforts in order to make this happen, as that requires migrating all of the writes to make use of CMDQ instead of cpu writes and that's not trivial. For this reason, this patch only moves the LUT enable. The CMDQ rework will come at a later time. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index 204a1aa7bfc9..b75a77af5205 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -71,12 +71,12 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct d= rm_crtc_state *state) { struct mtk_disp_gamma *gamma =3D dev_get_drvdata(dev); - unsigned int i, reg; + unsigned int i; struct drm_color_lut *lut; void __iomem *lut_base; bool lut_diff; u16 lut_size; - u32 word; + u32 cfg_val, word; =20 /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) @@ -90,9 +90,7 @@ void mtk_gamma_set_common(struct device *dev, void __iome= m *regs, struct drm_crt lut_size =3D LUT_SIZE_DEFAULT; } =20 - reg =3D readl(regs + DISP_GAMMA_CFG); - reg =3D reg | GAMMA_LUT_EN; - writel(reg, regs + DISP_GAMMA_CFG); + cfg_val =3D readl(regs + DISP_GAMMA_CFG); lut_base =3D regs + DISP_GAMMA_LUT; lut =3D (struct drm_color_lut *)state->gamma_lut->data; for (i =3D 0; i < lut_size; i++) { @@ -122,6 +120,11 @@ void mtk_gamma_set_common(struct device *dev, void __i= omem *regs, struct drm_crt } writel(word, (lut_base + i * 4)); } + + /* Enable the gamma table */ + cfg_val =3D cfg_val | GAMMA_LUT_EN; + + writel(cfg_val, regs + DISP_GAMMA_CFG); } =20 void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) --=20 2.40.1 From nobody Fri Sep 20 16:48:19 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED1A0C7EE45 for ; Mon, 12 Jun 2023 09:06:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234055AbjFLJGR (ORCPT ); Mon, 12 Jun 2023 05:06:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231226AbjFLJFe (ORCPT ); Mon, 12 Jun 2023 05:05:34 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 67F2F49C0 for ; Mon, 12 Jun 2023 02:02:11 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (unknown [IPv6:2001:b07:2ed:14ed:c5f8:7372:f042:90a2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 700816606ED2; Mon, 12 Jun 2023 10:02:07 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1686560528; bh=3I8Rjj9QMcA+JJ4/+HINgDnaxJetoJetOg2mGldS5tI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Q1ZVmr4QWzTgS/c59kIyXplHTw+DXWxI6hFZzl41u2TZOGULyoJqszbwZsb8WQgOc hUb166ryYV7qjHj9yz2FJJGmhOwx8oCyfsGd/Bv23WU1JxRuVRDIWU8xrmJGcQz0Eq 0gFF6Qd/Z/Gu3jHNaTxQKS2e3m5/US0wnji/03VG6RVAN1YtZPlXX7JHUzKD94NM0Z xBXC1GXeXg4ZAGaT2bmzz1T1m12cEOyJ+EYd/61gZVdcTEZldP9jLE30pg26zJTDQi Op0ZSln2jr41EhXmv7H56TQSvdf7QEuUZwdjTPUzuSdYOqDXeEa0ZUa+BciqmZWzL8 jtsEvulcOAJOQ== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, "Jason-JH . Lin" Subject: [PATCH v6 06/11] drm/mediatek: gamma: Use bitfield macros Date: Mon, 12 Jun 2023 11:01:52 +0200 Message-Id: <20230612090157.68205-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230612090157.68205-1-angelogioacchino.delregno@collabora.com> References: <20230612090157.68205-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Make the code more robust and improve readability by using bitfield macros instead of open coding bit operations. While at it, also add a definition for LUT_BITS_DEFAULT. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 41 ++++++++++++++--------- 1 file changed, 26 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index b75a77af5205..f4bf5b37992c 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -3,6 +3,7 @@ * Copyright (c) 2021 MediaTek Inc. */ =20 +#include #include #include #include @@ -22,9 +23,16 @@ #define GAMMA_LUT_EN BIT(1) #define GAMMA_DITHERING BIT(2) #define DISP_GAMMA_SIZE 0x0030 +#define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16) +#define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) #define DISP_GAMMA_LUT 0x0700 =20 +#define DISP_GAMMA_LUT_10BIT_R GENMASK(29, 20) +#define DISP_GAMMA_LUT_10BIT_G GENMASK(19, 10) +#define DISP_GAMMA_LUT_10BIT_B GENMASK(9, 0) + #define LUT_10BIT_MASK 0x03ff +#define LUT_BITS_DEFAULT 10 #define LUT_SIZE_DEFAULT 512 =20 struct mtk_disp_gamma_data { @@ -96,33 +104,33 @@ void mtk_gamma_set_common(struct device *dev, void __i= omem *regs, struct drm_crt for (i =3D 0; i < lut_size; i++) { struct drm_color_lut diff, hwlut; =20 - hwlut.red =3D drm_color_lut_extract(lut[i].red, 10); - hwlut.green =3D drm_color_lut_extract(lut[i].green, 10); - hwlut.blue =3D drm_color_lut_extract(lut[i].blue, 10); + hwlut.red =3D drm_color_lut_extract(lut[i].red, LUT_BITS_DEFAULT); + hwlut.green =3D drm_color_lut_extract(lut[i].green, LUT_BITS_DEFAULT); + hwlut.blue =3D drm_color_lut_extract(lut[i].blue, LUT_BITS_DEFAULT); =20 if (!lut_diff || (i % 2 =3D=3D 0)) { - word =3D hwlut.red << 20 + - hwlut.green << 10 + - hwlut.red; + word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); + word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); + word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); } else { diff.red =3D lut[i].red - lut[i - 1].red; - diff.red =3D drm_color_lut_extract(diff.red, 10); + diff.red =3D drm_color_lut_extract(diff.red, LUT_BITS_DEFAULT); =20 diff.green =3D lut[i].green - lut[i - 1].green; - diff.green =3D drm_color_lut_extract(diff.green, 10); + diff.green =3D drm_color_lut_extract(diff.green, LUT_BITS_DEFAULT); =20 diff.blue =3D lut[i].blue - lut[i - 1].blue; - diff.blue =3D drm_color_lut_extract(diff.blue, 10); + diff.blue =3D drm_color_lut_extract(diff.blue, LUT_BITS_DEFAULT); =20 - word =3D diff.blue << 20 + - diff.green << 10 + - diff.red; + word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); + word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); + word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); } writel(word, (lut_base + i * 4)); } =20 /* Enable the gamma table */ - cfg_val =3D cfg_val | GAMMA_LUT_EN; + cfg_val |=3D FIELD_PREP(GAMMA_LUT_EN, 1); =20 writel(cfg_val, regs + DISP_GAMMA_CFG); } @@ -139,9 +147,12 @@ void mtk_gamma_config(struct device *dev, unsigned int= w, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { struct mtk_disp_gamma *gamma =3D dev_get_drvdata(dev); + u32 sz; + + sz =3D FIELD_PREP(DISP_GAMMA_SIZE_HSIZE, w); + sz |=3D FIELD_PREP(DISP_GAMMA_SIZE_VSIZE, h); =20 - mtk_ddp_write(cmdq_pkt, h << 16 | w, &gamma->cmdq_reg, gamma->regs, - DISP_GAMMA_SIZE); + mtk_ddp_write(cmdq_pkt, sz, &gamma->cmdq_reg, gamma->regs, DISP_GAMMA_SIZ= E); if (gamma->data && gamma->data->has_dither) mtk_dither_set_common(gamma->regs, &gamma->cmdq_reg, bpc, DISP_GAMMA_CFG, GAMMA_DITHERING, cmdq_pkt); --=20 2.40.1 From nobody Fri Sep 20 16:48:19 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2333FC7EE23 for ; Mon, 12 Jun 2023 09:06:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234062AbjFLJGa (ORCPT ); Mon, 12 Jun 2023 05:06:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60508 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232409AbjFLJFh (ORCPT ); Mon, 12 Jun 2023 05:05:37 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E141D49C4 for ; Mon, 12 Jun 2023 02:02:11 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (unknown [IPv6:2001:b07:2ed:14ed:c5f8:7372:f042:90a2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 655CB6606EE6; Mon, 12 Jun 2023 10:02:08 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1686560529; bh=wvL8C41awqGUjG6vSxsIBQRXHZy+wyE4bNAhpHhiqhc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JiZHDK5audELU5OV915FxpbKTQp+LEuX/+WPIiSMVvoHa2Joh+Wz9jNDdcVky5Hnw TwS+PLkD9A1SBtgpwI0KkE+bHE/r6aF178gJYMR4Gsd0arU7lPLiSQODgIp9xnegwf f8gdffORlZKBRYkh9mpT2UnIIcIsy2DfzxVMiE78wfUR9ZPfOWoWbvIsRgX0108UEW jp+e1XHupyDxBASZm/DOCmXKr8cOuJHoVRrbYOX3enq3V1EdOMOfJSuWo01A6FwbT8 k29JtLtlK23fGK2BzWhHPaw7VnSGLM7MTmn6gsAtnNnSeuCbh5lS533vCOGHZN9bCr 4VvxNpyfNButg== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, "Jason-JH . Lin" Subject: [PATCH v6 07/11] drm/mediatek: gamma: Support specifying number of bits per LUT component Date: Mon, 12 Jun 2023 11:01:53 +0200 Message-Id: <20230612090157.68205-8-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230612090157.68205-1-angelogioacchino.delregno@collabora.com> References: <20230612090157.68205-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" New SoCs, like MT8195, not only may support bigger lookup tables, but have got a different register layout to support bigger precision: support specifying the number of `lut_bits` for each SoC and use it in mtk_gamma_set_common() to perform the right calculation. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index f4bf5b37992c..407fb0264b80 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -39,6 +39,7 @@ struct mtk_disp_gamma_data { bool has_dither; bool lut_diff; u16 lut_size; + u8 lut_bits; }; =20 /* @@ -84,6 +85,7 @@ void mtk_gamma_set_common(struct device *dev, void __iome= m *regs, struct drm_crt void __iomem *lut_base; bool lut_diff; u16 lut_size; + u8 lut_bits; u32 cfg_val, word; =20 /* If there's no gamma lut there's nothing to do here. */ @@ -92,9 +94,11 @@ void mtk_gamma_set_common(struct device *dev, void __iom= em *regs, struct drm_crt =20 if (gamma && gamma->data) { lut_diff =3D gamma->data->lut_diff; + lut_bits =3D gamma->data->lut_bits; lut_size =3D gamma->data->lut_size; } else { lut_diff =3D false; + lut_bits =3D LUT_BITS_DEFAULT; lut_size =3D LUT_SIZE_DEFAULT; } =20 @@ -104,9 +108,9 @@ void mtk_gamma_set_common(struct device *dev, void __io= mem *regs, struct drm_crt for (i =3D 0; i < lut_size; i++) { struct drm_color_lut diff, hwlut; =20 - hwlut.red =3D drm_color_lut_extract(lut[i].red, LUT_BITS_DEFAULT); - hwlut.green =3D drm_color_lut_extract(lut[i].green, LUT_BITS_DEFAULT); - hwlut.blue =3D drm_color_lut_extract(lut[i].blue, LUT_BITS_DEFAULT); + hwlut.red =3D drm_color_lut_extract(lut[i].red, lut_bits); + hwlut.green =3D drm_color_lut_extract(lut[i].green, lut_bits); + hwlut.blue =3D drm_color_lut_extract(lut[i].blue, lut_bits); =20 if (!lut_diff || (i % 2 =3D=3D 0)) { word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); @@ -114,13 +118,13 @@ void mtk_gamma_set_common(struct device *dev, void __= iomem *regs, struct drm_crt word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); } else { diff.red =3D lut[i].red - lut[i - 1].red; - diff.red =3D drm_color_lut_extract(diff.red, LUT_BITS_DEFAULT); + diff.red =3D drm_color_lut_extract(diff.red, lut_bits); =20 diff.green =3D lut[i].green - lut[i - 1].green; - diff.green =3D drm_color_lut_extract(diff.green, LUT_BITS_DEFAULT); + diff.green =3D drm_color_lut_extract(diff.green, lut_bits); =20 diff.blue =3D lut[i].blue - lut[i - 1].blue; - diff.blue =3D drm_color_lut_extract(diff.blue, LUT_BITS_DEFAULT); + diff.blue =3D drm_color_lut_extract(diff.blue, lut_bits); =20 word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); @@ -237,10 +241,12 @@ static int mtk_disp_gamma_remove(struct platform_devi= ce *pdev) =20 static const struct mtk_disp_gamma_data mt8173_gamma_driver_data =3D { .has_dither =3D true, + .lut_bits =3D 10, .lut_size =3D 512, }; =20 static const struct mtk_disp_gamma_data mt8183_gamma_driver_data =3D { + .lut_bits =3D 10, .lut_diff =3D true, .lut_size =3D 512, }; --=20 2.40.1 From nobody Fri Sep 20 16:48:19 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23BEDC7EE25 for ; Mon, 12 Jun 2023 09:06:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229690AbjFLJGV (ORCPT ); Mon, 12 Jun 2023 05:06:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60480 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229735AbjFLJFg (ORCPT ); Mon, 12 Jun 2023 05:05:36 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E109249C3 for ; Mon, 12 Jun 2023 02:02:11 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (unknown [IPv6:2001:b07:2ed:14ed:c5f8:7372:f042:90a2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 50BF46606EF5; Mon, 12 Jun 2023 10:02:09 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1686560530; bh=jXr0wGpGehE+iesVyt9aBsjAnzI1CbtR4qvojrtKsGU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lStdLUtm4BayIHOLsZjjeC/LghAJ+jsTxVJYd98OD0cXJMhvJV3E0oR2mEP7KJnoo 59JqDmjDebS9cClrzNKRuH/4g9n+4co3nbJQogoDDNlgbdKTGaWHfrVf3CIF/7XNd8 TQpgiCzz5aUM2A13d/gOPsExcTirIR6plzLJsN3Ex0PWUzAtTuTZOvwkv/YRk/azaR IFVKhPeS5ypHBzn9KofbrW4jQF9SFVd5HHtHjmZ4lrZB+z8WJaGz8V8COCVyrFooOb d2hpodGORfTi6tFEYQL26tK58TfO9ddJeiqyWohcHm3BBIZnatI+K8Hz6fJ+c71P1t 4No80H6qegK2Q== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, "Jason-JH . Lin" Subject: [PATCH v6 08/11] drm/mediatek: gamma: Support multi-bank gamma LUT Date: Mon, 12 Jun 2023 11:01:54 +0200 Message-Id: <20230612090157.68205-9-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230612090157.68205-1-angelogioacchino.delregno@collabora.com> References: <20230612090157.68205-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Newer Gamma IP have got multiple LUT banks: support specifying the size of the LUT banks and handle bank-switching before programming the LUT in mtk_gamma_set_common() in preparation for adding support for MT8195 and newer SoCs. Suggested-by: Jason-JH.Lin [Angelo: Refactored original commit] Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 74 ++++++++++++++--------- 1 file changed, 47 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index 407fb0264b80..f1a0b18b6c1a 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -25,6 +25,8 @@ #define DISP_GAMMA_SIZE 0x0030 #define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16) #define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) +#define DISP_GAMMA_BANK 0x0100 +#define DISP_GAMMA_BANK_BANK GENMASK(1, 0) #define DISP_GAMMA_LUT 0x0700 =20 #define DISP_GAMMA_LUT_10BIT_R GENMASK(29, 20) @@ -38,6 +40,7 @@ struct mtk_disp_gamma_data { bool has_dither; bool lut_diff; + u16 lut_bank_size; u16 lut_size; u8 lut_bits; }; @@ -84,9 +87,10 @@ void mtk_gamma_set_common(struct device *dev, void __iom= em *regs, struct drm_crt struct drm_color_lut *lut; void __iomem *lut_base; bool lut_diff; - u16 lut_size; + u16 lut_bank_size, lut_size; u8 lut_bits; - u32 cfg_val, word; + u32 cfg_val, lbank_val, word; + int cur_bank, num_lut_banks; =20 /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) @@ -94,43 +98,57 @@ void mtk_gamma_set_common(struct device *dev, void __io= mem *regs, struct drm_crt =20 if (gamma && gamma->data) { lut_diff =3D gamma->data->lut_diff; + lut_bank_size =3D gamma->data->lut_bank_size; lut_bits =3D gamma->data->lut_bits; lut_size =3D gamma->data->lut_size; } else { lut_diff =3D false; + lut_bank_size =3D LUT_SIZE_DEFAULT; lut_bits =3D LUT_BITS_DEFAULT; lut_size =3D LUT_SIZE_DEFAULT; } + num_lut_banks =3D lut_size / lut_bank_size; =20 cfg_val =3D readl(regs + DISP_GAMMA_CFG); lut_base =3D regs + DISP_GAMMA_LUT; lut =3D (struct drm_color_lut *)state->gamma_lut->data; - for (i =3D 0; i < lut_size; i++) { - struct drm_color_lut diff, hwlut; - - hwlut.red =3D drm_color_lut_extract(lut[i].red, lut_bits); - hwlut.green =3D drm_color_lut_extract(lut[i].green, lut_bits); - hwlut.blue =3D drm_color_lut_extract(lut[i].blue, lut_bits); - - if (!lut_diff || (i % 2 =3D=3D 0)) { - word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); - } else { - diff.red =3D lut[i].red - lut[i - 1].red; - diff.red =3D drm_color_lut_extract(diff.red, lut_bits); - - diff.green =3D lut[i].green - lut[i - 1].green; - diff.green =3D drm_color_lut_extract(diff.green, lut_bits); - - diff.blue =3D lut[i].blue - lut[i - 1].blue; - diff.blue =3D drm_color_lut_extract(diff.blue, lut_bits); - - word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + + for (cur_bank =3D 0; cur_bank < num_lut_banks; cur_bank++) { + + /* Switch gamma bank and set data mode before writing LUT */ + if (num_lut_banks > 1) { + lbank_val =3D FIELD_PREP(DISP_GAMMA_BANK_BANK, cur_bank); + writel(lbank_val, regs + DISP_GAMMA_BANK); + } + + for (i =3D 0; i < lut_bank_size; i++) { + int n =3D (cur_bank * lut_bank_size) + i; + struct drm_color_lut diff, hwlut; + + hwlut.red =3D drm_color_lut_extract(lut[n].red, lut_bits); + hwlut.green =3D drm_color_lut_extract(lut[n].green, lut_bits); + hwlut.blue =3D drm_color_lut_extract(lut[n].blue, lut_bits); + + if (!lut_diff || (i % 2 =3D=3D 0)) { + word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); + word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); + word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); + } else { + diff.red =3D lut[n].red - lut[n - 1].red; + diff.red =3D drm_color_lut_extract(diff.red, lut_bits); + + diff.green =3D lut[n].green - lut[n - 1].green; + diff.green =3D drm_color_lut_extract(diff.green, lut_bits); + + diff.blue =3D lut[n].blue - lut[n - 1].blue; + diff.blue =3D drm_color_lut_extract(diff.blue, lut_bits); + + word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); + word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); + word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + } + writel(word, (lut_base + i * 4)); } - writel(word, (lut_base + i * 4)); } =20 /* Enable the gamma table */ @@ -241,11 +259,13 @@ static int mtk_disp_gamma_remove(struct platform_devi= ce *pdev) =20 static const struct mtk_disp_gamma_data mt8173_gamma_driver_data =3D { .has_dither =3D true, + .lut_bank_size =3D 512, .lut_bits =3D 10, .lut_size =3D 512, }; =20 static const struct mtk_disp_gamma_data mt8183_gamma_driver_data =3D { + .lut_bank_size =3D 512, .lut_bits =3D 10, .lut_diff =3D true, .lut_size =3D 512, --=20 2.40.1 From nobody Fri Sep 20 16:48:19 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0820C7EE25 for ; Mon, 12 Jun 2023 09:06:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229879AbjFLJGh (ORCPT ); Mon, 12 Jun 2023 05:06:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60560 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233614AbjFLJFi (ORCPT ); Mon, 12 Jun 2023 05:05:38 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09DD649C8 for ; Mon, 12 Jun 2023 02:02:12 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (unknown [IPv6:2001:b07:2ed:14ed:c5f8:7372:f042:90a2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 4340D6606E9A; Mon, 12 Jun 2023 10:02:10 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1686560531; bh=LhMeyPcFgIwAH9sbt0vvYI5UK8ayi4irA8hzAUP7wm0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oPPAmp1rJJ/vKwjWFh0Rh07j+YqqmYWGrOSGiSSByBqhUTuVsY4OqdbM6vIrNy4IC zLKLw0ZAyhJim6uLIeOFSRlWKHaCDMTruLOb/5Oa56Kp4smOXilrPZLch2evevFAAX 3VNew/cnRp2aP8tepYRxtKaQzrtPwfgpm2g0fgi7fie4Kuz79KA+GUBGl88gEA8LB8 +NoAFTA6Zuzl0jghePpqRSVk8P+EwwlyAsvngZbtf2YJifXkkqPHrlmh8NZCcgF0g5 5hAMbgKJWm+hwZo5Ra2pywma5hmQgVn9Ta5utre+a+JrdMJwngNDsdHjWVHKsl/lDr WnCBbcD7q7vwA== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, "Jason-JH . Lin" Subject: [PATCH v6 09/11] drm/mediatek: gamma: Add support for 12-bit LUT and MT8195 Date: Mon, 12 Jun 2023 11:01:55 +0200 Message-Id: <20230612090157.68205-10-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230612090157.68205-1-angelogioacchino.delregno@collabora.com> References: <20230612090157.68205-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for 12-bit gamma lookup tables and introduce the first user for it: MT8195. While at it, also reorder the variables in mtk_gamma_set_common() and rename `lut_base` to `lut0_base` to improve readability. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 61 ++++++++++++++++++----- 1 file changed, 48 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index f1a0b18b6c1a..e0e2d2bdbf59 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -27,12 +27,20 @@ #define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) #define DISP_GAMMA_BANK 0x0100 #define DISP_GAMMA_BANK_BANK GENMASK(1, 0) +#define DISP_GAMMA_BANK_DATA_MODE BIT(2) #define DISP_GAMMA_LUT 0x0700 +#define DISP_GAMMA_LUT1 0x0b00 =20 +/* For 10 bit LUT layout, R/G/B are in the same register */ #define DISP_GAMMA_LUT_10BIT_R GENMASK(29, 20) #define DISP_GAMMA_LUT_10BIT_G GENMASK(19, 10) #define DISP_GAMMA_LUT_10BIT_B GENMASK(9, 0) =20 +/* For 12 bit LUT layout, R/G are in LUT, B is in LUT1 */ +#define DISP_GAMMA_LUT_12BIT_R GENMASK(11, 0) +#define DISP_GAMMA_LUT_12BIT_G GENMASK(23, 12) +#define DISP_GAMMA_LUT_12BIT_B GENMASK(11, 0) + #define LUT_10BIT_MASK 0x03ff #define LUT_BITS_DEFAULT 10 #define LUT_SIZE_DEFAULT 512 @@ -83,14 +91,15 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct d= rm_crtc_state *state) { struct mtk_disp_gamma *gamma =3D dev_get_drvdata(dev); - unsigned int i; + void __iomem *lut0_base =3D regs + DISP_GAMMA_LUT; + void __iomem *lut1_base =3D regs + DISP_GAMMA_LUT1; + u32 cfg_val, data_mode, lbank_val, word[2]; + int cur_bank, num_lut_banks; + u16 lut_bank_size, lut_size; struct drm_color_lut *lut; - void __iomem *lut_base; + unsigned int i; bool lut_diff; - u16 lut_bank_size, lut_size; u8 lut_bits; - u32 cfg_val, lbank_val, word; - int cur_bank, num_lut_banks; =20 /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) @@ -110,14 +119,17 @@ void mtk_gamma_set_common(struct device *dev, void __= iomem *regs, struct drm_crt num_lut_banks =3D lut_size / lut_bank_size; =20 cfg_val =3D readl(regs + DISP_GAMMA_CFG); - lut_base =3D regs + DISP_GAMMA_LUT; lut =3D (struct drm_color_lut *)state->gamma_lut->data; =20 + /* Switch to 12 bits data mode if supported */ + data_mode =3D FIELD_PREP(DISP_GAMMA_BANK_DATA_MODE, !!(lut_bits =3D=3D 12= )); + for (cur_bank =3D 0; cur_bank < num_lut_banks; cur_bank++) { =20 /* Switch gamma bank and set data mode before writing LUT */ if (num_lut_banks > 1) { lbank_val =3D FIELD_PREP(DISP_GAMMA_BANK_BANK, cur_bank); + lbank_val |=3D data_mode; writel(lbank_val, regs + DISP_GAMMA_BANK); } =20 @@ -130,9 +142,15 @@ void mtk_gamma_set_common(struct device *dev, void __i= omem *regs, struct drm_crt hwlut.blue =3D drm_color_lut_extract(lut[n].blue, lut_bits); =20 if (!lut_diff || (i % 2 =3D=3D 0)) { - word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); + if (lut_bits =3D=3D 12) { + word[0] =3D FIELD_PREP(DISP_GAMMA_LUT_12BIT_R, hwlut.red); + word[0] |=3D FIELD_PREP(DISP_GAMMA_LUT_12BIT_G, hwlut.green); + word[1] =3D FIELD_PREP(DISP_GAMMA_LUT_12BIT_B, hwlut.blue); + } else { + word[0] =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); + word[0] |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); + word[0] |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); + } } else { diff.red =3D lut[n].red - lut[n - 1].red; diff.red =3D drm_color_lut_extract(diff.red, lut_bits); @@ -143,11 +161,19 @@ void mtk_gamma_set_common(struct device *dev, void __= iomem *regs, struct drm_crt diff.blue =3D lut[n].blue - lut[n - 1].blue; diff.blue =3D drm_color_lut_extract(diff.blue, lut_bits); =20 - word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + if (lut_bits =3D=3D 12) { + word[0] =3D FIELD_PREP(DISP_GAMMA_LUT_12BIT_R, diff.red); + word[0] |=3D FIELD_PREP(DISP_GAMMA_LUT_12BIT_G, diff.green); + word[1] =3D FIELD_PREP(DISP_GAMMA_LUT_12BIT_B, diff.blue); + } else { + word[0] =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); + word[0] |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); + word[0] |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + } } - writel(word, (lut_base + i * 4)); + writel(word[0], (lut0_base + i * 4)); + if (lut_bits =3D=3D 12) + writel(word[1], (lut1_base + i * 4)); } } =20 @@ -271,11 +297,20 @@ static const struct mtk_disp_gamma_data mt8183_gamma_= driver_data =3D { .lut_size =3D 512, }; =20 +static const struct mtk_disp_gamma_data mt8195_gamma_driver_data =3D { + .lut_bank_size =3D 256, + .lut_bits =3D 12, + .lut_diff =3D true, + .lut_size =3D 1024, +}; + static const struct of_device_id mtk_disp_gamma_driver_dt_match[] =3D { { .compatible =3D "mediatek,mt8173-disp-gamma", .data =3D &mt8173_gamma_driver_data}, { .compatible =3D "mediatek,mt8183-disp-gamma", .data =3D &mt8183_gamma_driver_data}, + { .compatible =3D "mediatek,mt8195-disp-gamma", + .data =3D &mt8195_gamma_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_gamma_driver_dt_match); --=20 2.40.1 From nobody Fri Sep 20 16:48:19 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C64C0C7EE23 for ; Mon, 12 Jun 2023 09:06:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232069AbjFLJGe (ORCPT ); Mon, 12 Jun 2023 05:06:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60536 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233630AbjFLJFi (ORCPT ); Mon, 12 Jun 2023 05:05:38 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 30E8B49CB for ; Mon, 12 Jun 2023 02:02:13 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (unknown [IPv6:2001:b07:2ed:14ed:c5f8:7372:f042:90a2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 3360F66056AA; Mon, 12 Jun 2023 10:02:11 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1686560531; bh=h6f7psRee+vgHmJfxJWJCr98AHCwupGoqyn4DcinahM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=n2IiMBIxHLe63zm/clp9XFbDlNVwIDlgISj+BAW3ggFcAS700c9b+WwgifPTQVQJK 3dBAFBTf+8PBDoK8zAVCggsElh1qfxs/Z/fu5VtzY3cwplaW+OZxrmkSgalVpn4QSc 27dwhOrJTq8gschHWvEB9W/SD4GgahR3+ctvMF2wESmXGwm3SsHXGZVJzlZ4rX/Qeg LJYpJvbElaR0A2Pitk09q2kB4e5UJH03+W0H+Mi0E9MwkwgD5PpWCDuCC5hMdfxNWt Nqnl9TWBsFoU7DDLA7LhSTfpedPUAh/LRBvTv1KniW+7WrO6WSALUNsw9Lc5O4cbJR +LccmSfM94puA== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, "Jason-JH . Lin" Subject: [PATCH v6 10/11] drm/mediatek: gamma: Make sure relay mode is disabled Date: Mon, 12 Jun 2023 11:01:56 +0200 Message-Id: <20230612090157.68205-11-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230612090157.68205-1-angelogioacchino.delregno@collabora.com> References: <20230612090157.68205-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Disable relay mode at the end of LUT programming to make sure that the processed image goes through. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index e0e2d2bdbf59..e9655b661364 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -20,6 +20,7 @@ #define DISP_GAMMA_EN 0x0000 #define GAMMA_EN BIT(0) #define DISP_GAMMA_CFG 0x0020 +#define GAMMA_RELAY_MODE BIT(0) #define GAMMA_LUT_EN BIT(1) #define GAMMA_DITHERING BIT(2) #define DISP_GAMMA_SIZE 0x0030 @@ -180,6 +181,9 @@ void mtk_gamma_set_common(struct device *dev, void __io= mem *regs, struct drm_crt /* Enable the gamma table */ cfg_val |=3D FIELD_PREP(GAMMA_LUT_EN, 1); =20 + /* Disable RELAY mode to pass the processed image */ + cfg_val &=3D ~GAMMA_RELAY_MODE; + writel(cfg_val, regs + DISP_GAMMA_CFG); } =20 --=20 2.40.1 From nobody Fri Sep 20 16:48:19 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2C69C7EE25 for ; Mon, 12 Jun 2023 09:06:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232160AbjFLJGm (ORCPT ); Mon, 12 Jun 2023 05:06:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229513AbjFLJFi (ORCPT ); Mon, 12 Jun 2023 05:05:38 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 180BF49CF for ; Mon, 12 Jun 2023 02:02:14 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (unknown [IPv6:2001:b07:2ed:14ed:c5f8:7372:f042:90a2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 2334166058B2; Mon, 12 Jun 2023 10:02:12 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1686560532; bh=0Iha/JOTYyfiitNl2/tF672JZIUVhHcbx0vgBiZKTc4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XxN0owsxdLvnbN1JSRZbDE/V3atzoEBxyKuBTOte+rVkDAZ6E0v5rAaXs2a2xErnt YiU0ebC7R1m5vtyyZirzCmyyRB5m08HS+eL1r+xJmBQsgs2UL/ZGb9Ubbk7WZZc8Dh VyAlC40CxKfG36v5tnlqSIKcoXf/HWub0JLU6CBQP6M8nbhVkEpAchFG1WZetLsMrj w3DlAoYnviYpV+l51EbTKR00cXoHotVohu86ASwa08PemA9lZHjsEMRBf2D1K/qt8E OASxi1Bnp7Pinr7c3mX9fDK15Wr3kKDMzLiARWQTvF0zYgvifs/tZwxEHiFgHnJvmU YVfUSfOZsOrTQ== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, "Jason-JH . Lin" Subject: [PATCH v6 11/11] drm/mediatek: gamma: Program gamma LUT type for descending or rising Date: Mon, 12 Jun 2023 11:01:57 +0200 Message-Id: <20230612090157.68205-12-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230612090157.68205-1-angelogioacchino.delregno@collabora.com> References: <20230612090157.68205-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All of the SoCs that don't have dithering control in the gamma IP have got a GAMMA_LUT_TYPE bit that tells to the IP if the LUT is "descending" (bit set) or "rising" (bit cleared): make sure to set it correctly after programming the LUT. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index e9655b661364..020755ae0ec0 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -23,6 +23,7 @@ #define GAMMA_RELAY_MODE BIT(0) #define GAMMA_LUT_EN BIT(1) #define GAMMA_DITHERING BIT(2) +#define GAMMA_LUT_TYPE BIT(2) #define DISP_GAMMA_SIZE 0x0030 #define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16) #define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) @@ -89,6 +90,16 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) return lut_size; } =20 +static bool mtk_gamma_lut_is_descending(struct drm_color_lut *lut, u32 lut= _size) +{ + u64 first, last; + + first =3D lut[0].red + lut[0].green + lut[0].blue; + last =3D lut[lut_size].red + lut[lut_size].green + lut[lut_size].blue; + + return !!(first > last); +} + void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct d= rm_crtc_state *state) { struct mtk_disp_gamma *gamma =3D dev_get_drvdata(dev); @@ -178,6 +189,14 @@ void mtk_gamma_set_common(struct device *dev, void __i= omem *regs, struct drm_crt } } =20 + if (gamma && gamma->data && !gamma->data->has_dither) { + /* Descending or Rising LUT */ + if (mtk_gamma_lut_is_descending(lut, lut_size)) + cfg_val |=3D FIELD_PREP(GAMMA_LUT_TYPE, 1); + else + cfg_val &=3D ~GAMMA_LUT_TYPE; + } + /* Enable the gamma table */ cfg_val |=3D FIELD_PREP(GAMMA_LUT_EN, 1); =20 --=20 2.40.1