From nobody Thu Nov 14 05:50:42 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD1CEC7EE45 for ; Mon, 12 Jun 2023 09:02:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231303AbjFLJCf (ORCPT ); Mon, 12 Jun 2023 05:02:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57522 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232462AbjFLJBk (ORCPT ); Mon, 12 Jun 2023 05:01:40 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8307DE77; Mon, 12 Jun 2023 01:58:27 -0700 (PDT) X-UUID: 4881b72c08ff11ee9cb5633481061a41-20230612 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=l+ctUZaiR/2JgRiWlTIsz979BCfM3huwLMiHk8mzwGg=; b=Ox3cw6ljR8CRwqHgsDPiGSoI03Q5+xPIidFrlNHsTap8I61PEr+QL2keEzEDX4rZXBBPWP0Y43AnPIFm5Rh7XVoshHiFB2Ey46UCT3Wz/w/BNumDLN7mjDVBdcB1ha+7zMKaaoyMfN1JuDdmE269dd3+9VjlM/T8Q+dAWpB/NA4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.26,REQID:dd3d5157-4b63-405f-9a65-aaff7edda675,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:cb9a4e1,CLOUDID:cff8253e-de1e-4348-bc35-c96f92f1dcbb,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 4881b72c08ff11ee9cb5633481061a41-20230612 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 76957621; Mon, 12 Jun 2023 16:58:22 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 12 Jun 2023 16:58:20 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 12 Jun 2023 16:58:20 +0800 From: Po-Wen Kao To: , , , , Alim Akhtar , Avri Altman , Bart Van Assche , "James E.J. Bottomley" , "Martin K. Petersen" , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , , , , , Subject: [PATCH v1 1/4] scsi: ufs: core: Add host quirk UFSHCD_QUIRK_MCQ_BROKEN_INTR Date: Mon, 12 Jun 2023 16:58:09 +0800 Message-ID: <20230612085817.12275-2-powen.kao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230612085817.12275-1-powen.kao@mediatek.com> References: <20230612085817.12275-1-powen.kao@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Quirk UFSHCD_QUIRK_MCQ_BROKEN_INTR is introduced for host that implement different interrupt topology from UFSHCI 4.0 spec. Some host raise per hw queue interrupt in addition to CQES (traditional) when ESI is disabled. Enable this quirk will disable CQES and use only per hw queue interrupt. Signed-off-by: Po-Wen Kao Reviewed-by: Stanley Chu --- drivers/ufs/core/ufshcd.c | 6 +++++- include/ufs/ufshcd.h | 7 +++++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index 5da62248ebc4..5e093eba897b 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -8608,11 +8608,15 @@ static int ufshcd_alloc_mcq(struct ufs_hba *hba) static void ufshcd_config_mcq(struct ufs_hba *hba) { int ret; + u32 intrs; =20 ret =3D ufshcd_mcq_vops_config_esi(hba); dev_info(hba->dev, "ESI %sconfigured\n", ret ? "is not " : ""); =20 - ufshcd_enable_intr(hba, UFSHCD_ENABLE_MCQ_INTRS); + intrs =3D UFSHCD_ENABLE_MCQ_INTRS; + if (hba->quirks & UFSHCD_QUIRK_MCQ_BROKEN_INTR) + intrs &=3D ~MCQ_CQ_EVENT_STATUS; + ufshcd_enable_intr(hba, intrs); ufshcd_mcq_make_queues_operational(hba); ufshcd_mcq_config_mac(hba, hba->nutrs); =20 diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index 9b2d1859f885..ea43ceaf881c 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -611,6 +611,13 @@ enum ufshcd_quirks { * to reinit the device after switching to maximum gear. */ UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH =3D 1 << 19, + + /* + * Some host raises interrupt (per queue) in addition to + * CQES (traditional) when ESI is disabled. + * Enable this quirk will disable CQES and use per queue interrupt. + */ + UFSHCD_QUIRK_MCQ_BROKEN_INTR =3D 1 << 20, }; =20 enum ufshcd_caps { --=20 2.18.0