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[178.147.169.233]) by smtp.gmail.com with ESMTPSA id y22-20020a7bcd96000000b003f7f2a1484csm10552195wmj.5.2023.06.12.00.59.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jun 2023 00:59:56 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Landen Chao , Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net v4 1/7] net: dsa: mt7530: fix trapping frames with multiple CPU ports on MT7531 Date: Mon, 12 Jun 2023 10:59:39 +0300 Message-Id: <20230612075945.16330-2-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612075945.16330-1-arinc.unal@arinc9.com> References: <20230612075945.16330-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Every bit of the CPU port bitmap for MT7531 and the switch on the MT7988 SoC represents a CPU port to trap frames to. These switches trap frames received from a user port to the CPU port that is affine to the user port from which the frames are received. Currently, only the bit that corresponds to the first found CPU port is set on the bitmap. When multiple CPU ports are being used, the trapped frames from the user ports not affine to the first CPU port will be dropped as the other CPU port is not set on the bitmap. The switch on the MT7988 SoC is not affected as there's only one port to be used as a CPU port. To fix this, introduce the MT7531_CPU_PMAP macro to individually set the bits of the CPU port bitmap. Set the CPU port bitmap for MT7531 and the switch on the MT7988 SoC on mt753x_cpu_port_enable() which runs on a loop for each CPU port. Add a comment to explain frame trapping for these switches. According to the document MT7531 Reference Manual for Development Board v1.0, the MT7531_CPU_PMAP bits are unset after reset so no need to clear it beforehand. Since there's currently no public document for the switch on the MT7988 SoC, I assume this is also the case for this switch. Fixes: c288575f7810 ("net: dsa: mt7530: Add the support of MT7531 switch") Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 16 +++++++++------- drivers/net/dsa/mt7530.h | 1 + 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 9bc54e1348cb..b1657679e69d 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -1010,6 +1010,14 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int po= rt) if (priv->id =3D=3D ID_MT7621) mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); =20 + /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on + * the MT7988 SoC. Frames received from a user port which are set for + * trapping to CPU port will be trapped to the CPU port that is affine + * to the user port from which the frames are received. + */ + if (priv->id =3D=3D ID_MT7531 || priv->id =3D=3D ID_MT7988) + mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port))); + /* CPU port gets connected to all user ports of * the switch. */ @@ -2352,15 +2360,9 @@ static int mt7531_setup_common(struct dsa_switch *ds) { struct mt7530_priv *priv =3D ds->priv; - struct dsa_port *cpu_dp; int ret, i; =20 - /* BPDU to CPU port */ - dsa_switch_for_each_cpu_port(cpu_dp, ds) { - mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, - BIT(cpu_dp->index)); - break; - } + /* Trap BPDUs to the CPU port(s) */ mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, MT753X_BPDU_CPU_ONLY); =20 diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 5084f48a8869..e590cf43f3ae 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -54,6 +54,7 @@ enum mt753x_id { #define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK) #define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16) #define MT7531_CPU_PMAP_MASK GENMASK(7, 0) +#define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x) =20 #define MT753X_MIRROR_REG(id) ((((id) =3D=3D ID_MT7531) || ((id) =3D=3D I= D_MT7988)) ? \ MT7531_CFC : MT7530_MFC) --=20 2.39.2