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[178.147.169.233]) by smtp.gmail.com with ESMTPSA id y22-20020a7bcd96000000b003f7f2a1484csm10552195wmj.5.2023.06.12.00.59.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jun 2023 00:59:56 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Landen Chao , Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net v4 1/7] net: dsa: mt7530: fix trapping frames with multiple CPU ports on MT7531 Date: Mon, 12 Jun 2023 10:59:39 +0300 Message-Id: <20230612075945.16330-2-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612075945.16330-1-arinc.unal@arinc9.com> References: <20230612075945.16330-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Every bit of the CPU port bitmap for MT7531 and the switch on the MT7988 SoC represents a CPU port to trap frames to. These switches trap frames received from a user port to the CPU port that is affine to the user port from which the frames are received. Currently, only the bit that corresponds to the first found CPU port is set on the bitmap. When multiple CPU ports are being used, the trapped frames from the user ports not affine to the first CPU port will be dropped as the other CPU port is not set on the bitmap. The switch on the MT7988 SoC is not affected as there's only one port to be used as a CPU port. To fix this, introduce the MT7531_CPU_PMAP macro to individually set the bits of the CPU port bitmap. Set the CPU port bitmap for MT7531 and the switch on the MT7988 SoC on mt753x_cpu_port_enable() which runs on a loop for each CPU port. Add a comment to explain frame trapping for these switches. According to the document MT7531 Reference Manual for Development Board v1.0, the MT7531_CPU_PMAP bits are unset after reset so no need to clear it beforehand. Since there's currently no public document for the switch on the MT7988 SoC, I assume this is also the case for this switch. Fixes: c288575f7810 ("net: dsa: mt7530: Add the support of MT7531 switch") Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 16 +++++++++------- drivers/net/dsa/mt7530.h | 1 + 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 9bc54e1348cb..b1657679e69d 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -1010,6 +1010,14 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int po= rt) if (priv->id =3D=3D ID_MT7621) mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); =20 + /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on + * the MT7988 SoC. Frames received from a user port which are set for + * trapping to CPU port will be trapped to the CPU port that is affine + * to the user port from which the frames are received. + */ + if (priv->id =3D=3D ID_MT7531 || priv->id =3D=3D ID_MT7988) + mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port))); + /* CPU port gets connected to all user ports of * the switch. */ @@ -2352,15 +2360,9 @@ static int mt7531_setup_common(struct dsa_switch *ds) { struct mt7530_priv *priv =3D ds->priv; - struct dsa_port *cpu_dp; int ret, i; =20 - /* BPDU to CPU port */ - dsa_switch_for_each_cpu_port(cpu_dp, ds) { - mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, - BIT(cpu_dp->index)); - break; - } + /* Trap BPDUs to the CPU port(s) */ mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, MT753X_BPDU_CPU_ONLY); =20 diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 5084f48a8869..e590cf43f3ae 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -54,6 +54,7 @@ enum mt753x_id { #define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK) #define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16) #define MT7531_CPU_PMAP_MASK GENMASK(7, 0) +#define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x) =20 #define MT753X_MIRROR_REG(id) ((((id) =3D=3D ID_MT7531) || ((id) =3D=3D I= D_MT7988)) ? \ MT7531_CFC : MT7530_MFC) --=20 2.39.2 From nobody Fri Sep 20 17:35:47 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5D58C7EE25 for ; Mon, 12 Jun 2023 08:01:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229962AbjFLIBK (ORCPT ); Mon, 12 Jun 2023 04:01:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229456AbjFLIAk (ORCPT ); Mon, 12 Jun 2023 04:00:40 -0400 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4546B2127; Mon, 12 Jun 2023 01:00:02 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-3f6e1393f13so29075305e9.0; Mon, 12 Jun 2023 01:00:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686556800; x=1689148800; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AXYm2hz4kTxElsLw4X9ny+JM0G1qOYMFtL4G8lKVhQM=; b=lyoz+qj3DjC6mSttnlFKGyFtZPlMrL34MoqEv0ofoVqEUCNY1tOVgvitKJAsDLI+f6 4ZY6ASXRe/ClSVw+VyOcIg8fiDZOMZ7NBqF8GsBaW8Tl0dGzFNzz7BAmX4OB19q4UEb5 vvoc1HDwFthTiF4cr1Mai6bvKet1yeImUnLRU5i3pxI/I7CyTWDEGWMLYYPXlX7C+VUa YuDKBnetuJtREytacpWZsyK3X5+weChm5kQQxLINcSu53yALZVCnPS40cwf1OCMKxGNs qBnbHdSDKlxACNOmvM94WhY+caPNv5a+VjbML3oeg2/xVNuvpdzcOD0f+HG9aWcAmCoi f/qQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686556800; x=1689148800; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AXYm2hz4kTxElsLw4X9ny+JM0G1qOYMFtL4G8lKVhQM=; b=RSjiZWnQlSniturUXfwA+dKdvs1jmz9WsvwjPWEZMOQcFvJnT4w2c3kzE6zhhNwmN0 hXH2LS+o85EbDRa03hA8+TXbMpnpm1NOyT3cOaOJatdiDGyPkXYl1kCxQ0wlB4loqbK+ DXuBbdAxp9rui+ZPd22eWzPtLCcICiLXkZpucqSZIyPr9RvGgiwKjvgqbgAvMdYTVEWY R/MkN9MBdopeQOFD46Lr71OGYk1uI9sCIiHHnDpkRqVNoe0S+B8EsXOsW6nIXsKZ7LbQ AFldGh1QdSVnuq4kUUffAssMguYRi6chV2sVQG7iPjVzvShU4QNBHCPM6Qs1cy2jrI+Y cSiA== X-Gm-Message-State: AC+VfDzFLER4D0P/UDZp18jyfcJG1w7KUuZoE8YIIiKcP11vRYGa3YSZ sXPzlbFTRYVue/4zC4TsLF4= X-Google-Smtp-Source: ACHHUZ6W+NhXelu4c0LZFp0zNLt2oI3Q7Ebek7+5IhRWbZtZQWSFum6bcEQOeDKUD7OB7vxmL1bvaQ== X-Received: by 2002:a7b:cd97:0:b0:3f7:678a:cf24 with SMTP id y23-20020a7bcd97000000b003f7678acf24mr5445926wmj.39.1686556799953; Mon, 12 Jun 2023 00:59:59 -0700 (PDT) Received: from arinc9-Xeront.lan (178-147-169-233.haap.dm.cosmote.net. [178.147.169.233]) by smtp.gmail.com with ESMTPSA id y22-20020a7bcd96000000b003f7f2a1484csm10552195wmj.5.2023.06.12.00.59.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jun 2023 00:59:59 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Landen Chao , Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net v4 2/7] net: dsa: mt7530: fix trapping frames with multiple CPU ports on MT7530 Date: Mon, 12 Jun 2023 10:59:40 +0300 Message-Id: <20230612075945.16330-3-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612075945.16330-1-arinc.unal@arinc9.com> References: <20230612075945.16330-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL The CPU_PORT bits represent the CPU port to trap frames to for the MT7530 switch. This switch traps frames received from a user port to the CPU port set on the CPU_PORT bits, regardless of the affinity of the user port from which the frames are received. When multiple CPU ports are being used, the trapped frames won't be received when the DSA conduit interface, which the frames are supposed to be trapped to, is down because it's not affine to any user port. This requires the DSA conduit interface to be manually set up for the trapped frames to be received. To fix this, implement ds->ops->master_state_change() on this subdriver and set the CPU_PORT bits to the CPU port which the DSA conduit interface its affine to is up. Introduce the active_cpu_ports field to store the information of the active CPU ports. Correct the macros, CPU_PORT is bits 4 through 6 of the register. Add a comment to explain frame trapping for this switch. Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 sw= itch") Suggested-by: Vladimir Oltean Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 32 ++++++++++++++++++++++++++++---- drivers/net/dsa/mt7530.h | 6 ++++-- 2 files changed, 32 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index b1657679e69d..ef8879087932 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -1006,10 +1006,6 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int po= rt) mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port))); =20 - /* Set CPU port number */ - if (priv->id =3D=3D ID_MT7621) - mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); - /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on * the MT7988 SoC. Frames received from a user port which are set for * trapping to CPU port will be trapped to the CPU port that is affine @@ -3063,6 +3059,33 @@ static int mt753x_set_mac_eee(struct dsa_switch *ds,= int port, return 0; } =20 +static void +mt753x_master_state_change(struct dsa_switch *ds, + const struct net_device *master, + bool operational) +{ + struct mt7530_priv *priv =3D ds->priv; + struct dsa_port *cpu_dp =3D master->dsa_ptr; + + /* Set the CPU port to trap frames to for MT7530. There can be only one + * CPU port due to CPU_PORT having only 3 bits. Frames received from a + * user port which are set for trapping to CPU port will be trapped to + * the numerically smallest CPU port which is affine to the DSA conduit + * interface that is up. + */ + if (priv->id !=3D ID_MT7621) + return; + + if (operational) + priv->active_cpu_ports |=3D BIT(cpu_dp->index); + else + priv->active_cpu_ports &=3D ~BIT(cpu_dp->index); + + if (priv->active_cpu_ports) + mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, CPU_EN | + CPU_PORT(__ffs(priv->active_cpu_ports))); +} + static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interfa= ce) { return 0; @@ -3117,6 +3140,7 @@ const struct dsa_switch_ops mt7530_switch_ops =3D { .phylink_mac_link_up =3D mt753x_phylink_mac_link_up, .get_mac_eee =3D mt753x_get_mac_eee, .set_mac_eee =3D mt753x_set_mac_eee, + .master_state_change =3D mt753x_master_state_change, }; EXPORT_SYMBOL_GPL(mt7530_switch_ops); =20 diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index e590cf43f3ae..28dbd131a535 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -41,8 +41,8 @@ enum mt753x_id { #define UNU_FFP(x) (((x) & 0xff) << 8) #define UNU_FFP_MASK UNU_FFP(~0) #define CPU_EN BIT(7) -#define CPU_PORT(x) ((x) << 4) -#define CPU_MASK (0xf << 4) +#define CPU_PORT_MASK GENMASK(6, 4) +#define CPU_PORT(x) FIELD_PREP(CPU_PORT_MASK, x) #define MIRROR_EN BIT(3) #define MIRROR_PORT(x) ((x) & 0x7) #define MIRROR_MASK 0x7 @@ -753,6 +753,7 @@ struct mt753x_info { * @irq_domain: IRQ domain of the switch irq_chip * @irq_enable: IRQ enable bits, synced to SYS_INT_EN * @create_sgmii: Pointer to function creating SGMII PCS instance(s) + * @active_cpu_ports: Holding the active CPU ports */ struct mt7530_priv { struct device *dev; @@ -779,6 +780,7 @@ struct mt7530_priv { struct irq_domain *irq_domain; u32 irq_enable; int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii); + unsigned long active_cpu_ports; }; =20 struct mt7530_hw_vlan_entry { --=20 2.39.2 From nobody Fri Sep 20 17:35:47 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2A51C7EE43 for ; Mon, 12 Jun 2023 08:01:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233143AbjFLIBV (ORCPT ); Mon, 12 Jun 2023 04:01:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231646AbjFLIAm (ORCPT ); Mon, 12 Jun 2023 04:00:42 -0400 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 83A2A270F; Mon, 12 Jun 2023 01:00:08 -0700 (PDT) Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-3f7f4819256so29112835e9.1; Mon, 12 Jun 2023 01:00:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686556805; x=1689148805; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vV/mTXh/P+HK/c016dPT2W6UYy5AOVr8uOiiran4liM=; b=iegb2sJEV3NxeCdapW3bJRcA1eMQwKPGmzwuDTZNSQfK5LD346pv98ahxHWsYQi5z5 8vQHXORB+U9t/y9OSzfIBADoE8m7k8Rt3lMUCqlPfcc3gYcJkkP+xtn24kVbPq+eQaeR x4aGnONQQiYSxxKmcABMILnaTJUIt2tDpkAPF4OyHS/pPQhuTy/BT4GfsDowD2bTbomC aLkNafaJC5nexOEDu2mKYbhp0nFv4AshOWODck7ACWkzkDzZXToMzVaIryaO+bjRA3gl w3msHvZhDcsPphd+OYLTQ/0aGruy0jekDhdqXCgmnJAgdD0ri1TjKUhMtuZclBFjdnQS CJQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686556805; x=1689148805; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vV/mTXh/P+HK/c016dPT2W6UYy5AOVr8uOiiran4liM=; b=C91aHbBKdUhtv4cX3eb+l1F6HbcBRLRZSH4BNSO45ssDifDtMup8wce2L4+Nd61ITS xz6K2FhynOGbdiqHKMdw3LzYFwrPOiCQzBAF9BsuXPeEGCgqe/KxU5bRs4iwK7ylbbVQ 2e0lfqp3/xUbR6rpHVksZdZGMIiHV9tAOSf8x59fc3Bu99J4Gg/4AHTbf/rDN4zaz63z 8Dj/oexSlNRllHRArvAhXefuUDw6GR+E3aOPim3CLVoef+77Cgo2MHeMOfUekQvKi4eo d73it2zSh16S03qWi0Xbf+AF+a4hAE4207OS55y7LrQwMJ/8zcL+TZsRcB+v29NBlQXr HxEA== X-Gm-Message-State: AC+VfDxk02Epl9u9aLAXlk6hriCzrMX1xU/Um197BcJIvJOZhSfgjlrG nOJXVsRFbiU6kWWGEzKlJvI= X-Google-Smtp-Source: ACHHUZ5N4JqPmARx5C1YV6jCq0GelWy/qhgBOWDGYmH4WNy2BrUQp8UewzQTisD53HoZe0Yuveq/3w== X-Received: by 2002:a05:600c:2212:b0:3f4:23b9:eed2 with SMTP id z18-20020a05600c221200b003f423b9eed2mr6563679wml.38.1686556804733; Mon, 12 Jun 2023 01:00:04 -0700 (PDT) Received: from arinc9-Xeront.lan (178-147-169-233.haap.dm.cosmote.net. [178.147.169.233]) by smtp.gmail.com with ESMTPSA id y22-20020a7bcd96000000b003f7f2a1484csm10552195wmj.5.2023.06.12.01.00.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jun 2023 01:00:04 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Landen Chao , Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net v4 3/7] net: dsa: mt7530: fix trapping frames on non-MT7621 SoC MT7530 switch Date: Mon, 12 Jun 2023 10:59:41 +0300 Message-Id: <20230612075945.16330-4-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612075945.16330-1-arinc.unal@arinc9.com> References: <20230612075945.16330-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL The check for setting the CPU_PORT bits must include the non-MT7621 SoC MT7530 switch variants to trap frames. Expand the check to include them. Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 sw= itch") Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index ef8879087932..2bde2fdb5fba 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -3073,7 +3073,7 @@ mt753x_master_state_change(struct dsa_switch *ds, * the numerically smallest CPU port which is affine to the DSA conduit * interface that is up. */ - if (priv->id !=3D ID_MT7621) + if (priv->id !=3D ID_MT7530 && priv->id !=3D ID_MT7621) return; =20 if (operational) --=20 2.39.2 From nobody Fri Sep 20 17:35:47 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6BF5C7EE25 for ; Mon, 12 Jun 2023 08:01:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232041AbjFLIB1 (ORCPT ); Mon, 12 Jun 2023 04:01:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38760 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231918AbjFLIAo (ORCPT ); Mon, 12 Jun 2023 04:00:44 -0400 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7E99B2718; Mon, 12 Jun 2023 01:00:11 -0700 (PDT) Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-3f6e1394060so27082295e9.3; Mon, 12 Jun 2023 01:00:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686556809; x=1689148809; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qqs6PYWxr6amVjehvnSXauf3IGKKl/o67YTmLBa8zfM=; b=g8HorBvM1wg+Ji9yD1iaXxMTCzu3O62g8IEei/WOCAk1IsVunXoaEDC93zw5FcMVjQ wTPO+ZTDs0wjLtMi/Pxj/5XimnMAyjsbI8tvY7dt3VvlUVsTtW00rtkzdscf4Ts6vsI1 Xl37VM5txiVUIB4Jr2OZxHQRqVgo0Iba5rt0uqvFqx/QaozD+/1ZdiNRBoLjAhFDGeqY R58mBBJ9wlW9zOhMbYHM8ALz47dnr9FLYaHIoTt1h1VXy8M6vwxmLisQVM4p+MdjxZY3 +3v6fL4BuZex1E1wHJIVEYiYRnV4U1Z8HICfIKqVisA01JiOLCkA6FrsUlGCm7NSojAu ONCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686556809; x=1689148809; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qqs6PYWxr6amVjehvnSXauf3IGKKl/o67YTmLBa8zfM=; b=FDB/bsqtLnrZhLVD5xowDnhG1tCJd+80yiAR4GlwH5exl/R0dku4E2CLFOXeeDcOOM HnQsJx3Ha7BsGpbapfv3Gi+M2giGQEfXPE0rWW39XgMoOYTrLAlvu9Iequ6onuTaqAvz ITIEU5SII/Mm5HD/NKaneoNpb4+Wee+1awt5lt89DZSD4Y2u1/HX4RdgDOxQxe/LaOO3 PNSHtR3Db4ZRTgllBi9ddqNS0JWaM9MWe7GERPJWdlzDyxa4DEJa7FLFojRiFpNbW1Uy ZA5Efpyk2BAg8R5qPiHgr3L8AboubwLMrTH8VwmqbFPeVtvCeSofL780cGbXpDkvkUyI tOaA== X-Gm-Message-State: AC+VfDy9PberNEe/5mGFcR1InWIbtFUj22HxAyd3FRwE7G+9/4ai9otP TwwxonWVB5acC41X3vst4IQ= X-Google-Smtp-Source: ACHHUZ5WWo5mumZUNHSMZNQhMahI8vGuVUxNK9aDqqjEC7z0u4he/ff4mw2n+jFIhEw7/PKQJ3rg4g== X-Received: by 2002:a1c:4b14:0:b0:3f7:f2d0:b8fc with SMTP id y20-20020a1c4b14000000b003f7f2d0b8fcmr5237120wma.34.1686556809458; Mon, 12 Jun 2023 01:00:09 -0700 (PDT) Received: from arinc9-Xeront.lan (178-147-169-233.haap.dm.cosmote.net. [178.147.169.233]) by smtp.gmail.com with ESMTPSA id y22-20020a7bcd96000000b003f7f2a1484csm10552195wmj.5.2023.06.12.01.00.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jun 2023 01:00:09 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Landen Chao , Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net v4 4/7] net: dsa: mt7530: fix handling of BPDUs on MT7530 switch Date: Mon, 12 Jun 2023 10:59:42 +0300 Message-Id: <20230612075945.16330-5-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612075945.16330-1-arinc.unal@arinc9.com> References: <20230612075945.16330-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL BPDUs are link-local frames, therefore they must be trapped to the CPU port. Currently, the MT7530 switch treats BPDUs as regular multicast frames, therefore flooding them to user ports. To fix this, set BPDUs to be trapped to the CPU port. BPDUs received from a user port will be trapped to the numerically smallest CPU port which is affine to the DSA conduit interface that is up. Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 sw= itch") Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 2bde2fdb5fba..e4c169843f2e 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2259,6 +2259,10 @@ mt7530_setup(struct dsa_switch *ds) =20 priv->p6_interface =3D PHY_INTERFACE_MODE_NA; =20 + /* Trap BPDUs to the CPU port */ + mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, + MT753X_BPDU_CPU_ONLY); + /* Enable and reset MIB counters */ mt7530_mib_reset(ds); =20 --=20 2.39.2 From nobody Fri Sep 20 17:35:47 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 311DAC7EE23 for ; Mon, 12 Jun 2023 08:01:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232212AbjFLIBb (ORCPT ); Mon, 12 Jun 2023 04:01:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230396AbjFLIAw (ORCPT ); Mon, 12 Jun 2023 04:00:52 -0400 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 871C430CA; Mon, 12 Jun 2023 01:00:15 -0700 (PDT) Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-3f7378a75c0so28734205e9.3; Mon, 12 Jun 2023 01:00:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686556813; x=1689148813; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mLW++ExiYAGpOz1SvoxKGSu8dCoNxeqmwP2JI3jkkqk=; b=TB5gK2LoPlad2fwaIMbNsaorwK4JMuQF4hEQz6lkF+6MfTMprD/hNo48ZK+rkVy803 IUQXBkZv2p36nvtg7DM2gIW/CYlR52uRA9UQYu/LizZ1ClbYWqO1M8tZhkj+DgQMmeKL Ixz0LTGVJO0XflWusap3fnAQS/0W4ihd5shyfctOPWQJTK+SMep9c3Yb5hsTcpeeW69a EFvoOQbMoS1Xoq8CBsVR0Daeckou8qvPBXsgKQew52g9gE9GIYV287H5Ejm+o281Hu0M Vvtz0tSr21n5pCy3h+21fiZV1g0hL82mUBPg4Z5yqml0VkcmHoyk+94T8qCWTs1d69oS HzIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686556813; x=1689148813; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mLW++ExiYAGpOz1SvoxKGSu8dCoNxeqmwP2JI3jkkqk=; b=NOmZ+W9PS7ETFnhS7kTEyVPyfDT6D300RpnziAgsRY/ckj5CDKnwy9HwCyp9KBV4fR JXq5RzFCu/hrlwCiA87JHWq4v/9lyfzp5YupU6b9fPMP+CONsIQu8vJrnkEfHVZ8BNk9 1o2bfm6gpahEy9ZVO4EfOynHk/fPO4ERSjXw3IXtEOL9AgmigNz94tIv2dWpKF1sOjw1 kdKyLI1CezHlhuS5AdU7a1webD8itazmUKaFLQEkeDuZOeQyKiWmV+UYTTkRcrECdD7R sAUxsXd/640mbyupIck5jkNtRPZ9cej3t5l1640D8TMDRJuMvID7m7mdpzx6M3Xz0w5h a55w== X-Gm-Message-State: AC+VfDyEwr6Sk7tVUYUzAq9bkACquQwp59kmRUpQMKkrYtskc1tb0pQY +bAjEDoMvDlubdGitHH+gwE= X-Google-Smtp-Source: ACHHUZ4l6TALNkEBoJCoecWyLHZ2LIBS6+pRHp+GOMFIS6KGwt6s8wmCcHTyPMswS5F64jta3/wmsg== X-Received: by 2002:a1c:7414:0:b0:3f6:d2f:27f7 with SMTP id p20-20020a1c7414000000b003f60d2f27f7mr5777447wmc.17.1686556813335; Mon, 12 Jun 2023 01:00:13 -0700 (PDT) Received: from arinc9-Xeront.lan (178-147-169-233.haap.dm.cosmote.net. [178.147.169.233]) by smtp.gmail.com with ESMTPSA id y22-20020a7bcd96000000b003f7f2a1484csm10552195wmj.5.2023.06.12.01.00.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jun 2023 01:00:13 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Landen Chao , Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net v4 5/7] net: dsa: mt7530: fix handling of LLDP frames Date: Mon, 12 Jun 2023 10:59:43 +0300 Message-Id: <20230612075945.16330-6-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612075945.16330-1-arinc.unal@arinc9.com> References: <20230612075945.16330-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL LLDP frames are link-local frames, therefore they must be trapped to the CPU port. Currently, the MT753X switches treat LLDP frames as regular multicast frames, therefore flooding them to user ports. To fix this, set LLDP frames to be trapped to the CPU port(s). The mt753x_bpdu_port_fw enum is universally used for trapping frames, therefore rename it and the values in it to mt753x_port_fw. For MT7530, LLDP frames received from a user port will be trapped to the numerically smallest CPU port which is affine to the DSA conduit interface that is up. For MT7531 and the switch on the MT7988 SoC, LLDP frames received from a user port will be trapped to the CPU port that is affine to the user port from which the frames are received. The bit for R0E_MANG_FR is 27. When set, the switch regards the frames with :0E MAC DA as management (LLDP) frames. This bit is set to 1 after reset on MT7530 and MT7531 according to the documents MT7620 Programming Guide v1.0 and MT7531 Reference Manual for Development Board v1.0, so there's no need to deal with this bit. Since there's currently no public document for the switch on the MT7988 SoC, I assume this is also the case for this switch. Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 sw= itch") Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL reviewed-bys to it because nothing here makes much sense to me. --- drivers/net/dsa/mt7530.c | 12 ++++++++++-- drivers/net/dsa/mt7530.h | 19 ++++++++++++------- 2 files changed, 22 insertions(+), 9 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index e4c169843f2e..8388b058fbe4 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2261,7 +2261,11 @@ mt7530_setup(struct dsa_switch *ds) =20 /* Trap BPDUs to the CPU port */ mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, - MT753X_BPDU_CPU_ONLY); + MT753X_PORT_FW_CPU_ONLY); + + /* Trap LLDP frames with :0E MAC DA to the CPU port */ + mt7530_rmw(priv, MT753X_RGAC2, MT753X_R0E_PORT_FW_MASK, + MT753X_R0E_PORT_FW(MT753X_PORT_FW_CPU_ONLY)); =20 /* Enable and reset MIB counters */ mt7530_mib_reset(ds); @@ -2364,7 +2368,11 @@ mt7531_setup_common(struct dsa_switch *ds) =20 /* Trap BPDUs to the CPU port(s) */ mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, - MT753X_BPDU_CPU_ONLY); + MT753X_PORT_FW_CPU_ONLY); + + /* Trap LLDP frames with :0E MAC DA to the CPU port(s) */ + mt7530_rmw(priv, MT753X_RGAC2, MT753X_R0E_PORT_FW_MASK, + MT753X_R0E_PORT_FW(MT753X_PORT_FW_CPU_ONLY)); =20 /* Enable and reset MIB counters */ mt7530_mib_reset(ds); diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 28dbd131a535..5f048af2d89f 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -63,16 +63,21 @@ enum mt753x_id { #define MT753X_MIRROR_MASK(id) ((((id) =3D=3D ID_MT7531) || ((id) =3D=3D = ID_MT7988)) ? \ MT7531_MIRROR_MASK : MIRROR_MASK) =20 -/* Registers for BPDU and PAE frame control*/ +/* Register for BPDU and PAE frame control */ #define MT753X_BPC 0x24 #define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0) =20 -enum mt753x_bpdu_port_fw { - MT753X_BPDU_FOLLOW_MFC, - MT753X_BPDU_CPU_EXCLUDE =3D 4, - MT753X_BPDU_CPU_INCLUDE =3D 5, - MT753X_BPDU_CPU_ONLY =3D 6, - MT753X_BPDU_DROP =3D 7, +/* Register for :03 and :0E MAC DA frame control */ +#define MT753X_RGAC2 0x2c +#define MT753X_R0E_PORT_FW_MASK GENMASK(18, 16) +#define MT753X_R0E_PORT_FW(x) FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x) + +enum mt753x_port_fw { + MT753X_PORT_FW_FOLLOW_MFC, + MT753X_PORT_FW_CPU_EXCLUDE =3D 4, + MT753X_PORT_FW_CPU_INCLUDE =3D 5, + MT753X_PORT_FW_CPU_ONLY =3D 6, + MT753X_PORT_FW_DROP =3D 7, }; =20 /* Registers for address table access */ --=20 2.39.2 From nobody Fri Sep 20 17:35:47 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5080BC7EE25 for ; Mon, 12 Jun 2023 08:01:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232575AbjFLIBl (ORCPT ); Mon, 12 Jun 2023 04:01:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232365AbjFLIAy (ORCPT ); Mon, 12 Jun 2023 04:00:54 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F16610D4; Mon, 12 Jun 2023 01:00:18 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id 2adb3069b0e04-4f642a24568so4571281e87.2; Mon, 12 Jun 2023 01:00:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686556816; x=1689148816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lvRcwdwKF23WlBw1GQDVWmiphaH9UUywqfX3Q4qWYTI=; b=h90xNNQDima1Afxzqwau5EjgZTBuL3HNXA9h4zI5Y+ZrBm5i6QfGtXw62sLjz0xZRU JP+H2R8aGaPyGedxjkqA0aE7MzWQOsIsn3WvdRIQwRWiydYho5gJ1HOTWhBL1LxmvANc VVxGEVLJMnEvPSquEsDb1heE8dwgWoIZx7GMkbCGBE/0o7TPJvV95xjug8xELKSzAJDa e0VPBX9XyuCMtmDIuNUwXo0E44eco7YfZIeQQGRJi137DB1r7MUXpaNrnXp05l1unjnI Yah5246xGZjakb1MU/vbeixuOENQ0JhTL9YyJ7j/jX3ME/wk2+eAGo0iRT2YOgjl/aSV k98w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686556816; x=1689148816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lvRcwdwKF23WlBw1GQDVWmiphaH9UUywqfX3Q4qWYTI=; b=VZe6dRz/IKitzt3T16qcYNZjutswME7iIe9ewpGuQFLsYBbPXOO86mstqECEXmm2os wjDzkuZJc/EV1WnXhYFiZCuHdAuKZNSFp6wRMS53nZw/ttJS7oHd9h0DMFD6Ipgyekii Hb8b7h8ToQxas5WvH6QNmZUIzL55nJPt5JUL4C1vPS6WiJfdOBw6oatzEJcrv50V8ZCq G5VCNI/k0hySWMAhUQdSLMW5s2u3yoNgF2dlIQ+gS3YCQHU0h6bvX8oRPUwXkSUWTO/M Ti53/8/MHKyf8ll9o31ZGc5mwXUU8vF7M0/hTcOxIJ3n7KeltqvHfBWSmHGA4PagmiF2 QL8A== X-Gm-Message-State: AC+VfDyRUAYZUiRebeJCfNDuZ1qO/ay88EAeD6jFcCxYc3aEXH7vKVZb TY09zblNUmyWGKGvpCv0C3b7aUhrPas= X-Google-Smtp-Source: ACHHUZ4ClpVZM0YENkqEyxPU2Tp9GT8Dlmin9l43fMlLsl9n8UMu2bRKCaQVTKrU/akFqfOSH3+Wgw== X-Received: by 2002:a19:e306:0:b0:4f6:2b21:ece1 with SMTP id a6-20020a19e306000000b004f62b21ece1mr3640826lfh.43.1686556816145; Mon, 12 Jun 2023 01:00:16 -0700 (PDT) Received: from arinc9-Xeront.lan (178-147-169-233.haap.dm.cosmote.net. [178.147.169.233]) by smtp.gmail.com with ESMTPSA id y22-20020a7bcd96000000b003f7f2a1484csm10552195wmj.5.2023.06.12.01.00.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jun 2023 01:00:15 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Landen Chao , Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net v4 6/7] net: dsa: introduce preferred_default_local_cpu_port and use on MT7530 Date: Mon, 12 Jun 2023 10:59:44 +0300 Message-Id: <20230612075945.16330-7-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612075945.16330-1-arinc.unal@arinc9.com> References: <20230612075945.16330-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Vladimir Oltean Since the introduction of the OF bindings, DSA has always had a policy that in case multiple CPU ports are present in the device tree, the numerically smallest one is always chosen. The MT7530 switch family, except the switch on the MT7988 SoC, has 2 CPU ports, 5 and 6, where port 6 is preferable on the MT7531BE switch because it has higher bandwidth. The MT7530 driver developers had 3 options: - to modify DSA when the MT7531 switch support was introduced, such as to prefer the better port - to declare both CPU ports in device trees as CPU ports, and live with the sub-optimal performance resulting from not preferring the better port - to declare just port 6 in the device tree as a CPU port Of course they chose the path of least resistance (3rd option), kicking the can down the road. The hardware description in the device tree is supposed to be stable - developers are not supposed to adopt the strategy of piecemeal hardware description, where the device tree is updated in lockstep with the features that the kernel currently supports. Now, as a result of the fact that they did that, any attempts to modify the device tree and describe both CPU ports as CPU ports would make DSA change its default selection from port 6 to 5, effectively resulting in a performance degradation visible to users with the MT7531BE switch as can be seen below. Without preferring port 6: [ ID][Role] Interval Transfer Bitrate Retr [ 5][TX-C] 0.00-20.00 sec 374 MBytes 157 Mbits/sec 734 sender [ 5][TX-C] 0.00-20.00 sec 373 MBytes 156 Mbits/sec receiver [ 7][RX-C] 0.00-20.00 sec 1.81 GBytes 778 Mbits/sec 0 sender [ 7][RX-C] 0.00-20.00 sec 1.81 GBytes 777 Mbits/sec receiver With preferring port 6: [ ID][Role] Interval Transfer Bitrate Retr [ 5][TX-C] 0.00-20.00 sec 1.99 GBytes 856 Mbits/sec 273 sender [ 5][TX-C] 0.00-20.00 sec 1.99 GBytes 855 Mbits/sec receiver [ 7][RX-C] 0.00-20.00 sec 1.72 GBytes 737 Mbits/sec 15 sender [ 7][RX-C] 0.00-20.00 sec 1.71 GBytes 736 Mbits/sec receiver Using one port for WAN and the other ports for LAN is a very popular use case which is what this test emulates. As such, this change proposes that we retroactively modify stable kernels to keep the mt7530 driver preferring port 6 even with device trees where the hardware is more fully described. Fixes: c288575f7810 ("net: dsa: mt7530: Add the support of MT7531 switch") Signed-off-by: Vladimir Oltean Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 15 +++++++++++++++ include/net/dsa.h | 8 ++++++++ net/dsa/dsa.c | 24 +++++++++++++++++++++++- 3 files changed, 46 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 8388b058fbe4..4c44fc664419 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -399,6 +399,20 @@ static void mt7530_pll_setup(struct mt7530_priv *priv) core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); } =20 +/* If port 6 is available as a CPU port, always prefer that as the default, + * otherwise don't care. + */ +static struct dsa_port * +mt753x_preferred_default_local_cpu_port(struct dsa_switch *ds) +{ + struct dsa_port *cpu_dp =3D dsa_to_port(ds, 6); + + if (dsa_port_is_cpu(cpu_dp)) + return cpu_dp; + + return NULL; +} + /* Setup port 6 interface mode and TRGMII TX circuit */ static int mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) @@ -3122,6 +3136,7 @@ static int mt7988_setup(struct dsa_switch *ds) const struct dsa_switch_ops mt7530_switch_ops =3D { .get_tag_protocol =3D mtk_get_tag_protocol, .setup =3D mt753x_setup, + .preferred_default_local_cpu_port =3D mt753x_preferred_default_local_cpu_= port, .get_strings =3D mt7530_get_strings, .get_ethtool_stats =3D mt7530_get_ethtool_stats, .get_sset_count =3D mt7530_get_sset_count, diff --git a/include/net/dsa.h b/include/net/dsa.h index 8903053fa5aa..ab0f0a5b0860 100644 --- a/include/net/dsa.h +++ b/include/net/dsa.h @@ -958,6 +958,14 @@ struct dsa_switch_ops { struct phy_device *phy); void (*port_disable)(struct dsa_switch *ds, int port); =20 + /* + * Compatibility between device trees defining multiple CPU ports and + * drivers which are not OK to use by default the numerically smallest + * CPU port of a switch for its local ports. This can return NULL, + * meaning "don't know/don't care". + */ + struct dsa_port *(*preferred_default_local_cpu_port)(struct dsa_switch *d= s); + /* * Port's MAC EEE settings */ diff --git a/net/dsa/dsa.c b/net/dsa/dsa.c index ab1afe67fd18..1afed89e03c0 100644 --- a/net/dsa/dsa.c +++ b/net/dsa/dsa.c @@ -403,6 +403,24 @@ static int dsa_tree_setup_default_cpu(struct dsa_switc= h_tree *dst) return 0; } =20 +static struct dsa_port * +dsa_switch_preferred_default_local_cpu_port(struct dsa_switch *ds) +{ + struct dsa_port *cpu_dp; + + if (!ds->ops->preferred_default_local_cpu_port) + return NULL; + + cpu_dp =3D ds->ops->preferred_default_local_cpu_port(ds); + if (!cpu_dp) + return NULL; + + if (WARN_ON(!dsa_port_is_cpu(cpu_dp) || cpu_dp->ds !=3D ds)) + return NULL; + + return cpu_dp; +} + /* Perform initial assignment of CPU ports to user ports and DSA links in = the * fabric, giving preference to CPU ports local to each switch. Default to * using the first CPU port in the switch tree if the port does not have a= CPU @@ -410,12 +428,16 @@ static int dsa_tree_setup_default_cpu(struct dsa_swit= ch_tree *dst) */ static int dsa_tree_setup_cpu_ports(struct dsa_switch_tree *dst) { - struct dsa_port *cpu_dp, *dp; + struct dsa_port *preferred_cpu_dp, *cpu_dp, *dp; =20 list_for_each_entry(cpu_dp, &dst->ports, list) { if (!dsa_port_is_cpu(cpu_dp)) continue; =20 + preferred_cpu_dp =3D dsa_switch_preferred_default_local_cpu_port(cpu_dp-= >ds); + if (preferred_cpu_dp && preferred_cpu_dp !=3D cpu_dp) + continue; + /* Prefer a local CPU port */ dsa_switch_for_each_port(dp, cpu_dp->ds) { /* Prefer the first local CPU port found */ --=20 2.39.2 From nobody Fri Sep 20 17:35:47 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33A20C7EE23 for ; Mon, 12 Jun 2023 08:01:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232787AbjFLIBo (ORCPT ); Mon, 12 Jun 2023 04:01:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39694 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232732AbjFLIA5 (ORCPT ); Mon, 12 Jun 2023 04:00:57 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3EFD410E0; Mon, 12 Jun 2023 01:00:22 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id 2adb3069b0e04-4f63006b4e3so4657799e87.1; Mon, 12 Jun 2023 01:00:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686556819; x=1689148819; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AIVXF0NWT+mxXgpNldoq9Ep8Ze5GWaI0IQCYTwDNGis=; b=DnTvzYh/fYzUzxkqBzhHKbj25ROthxEX6h0AV5AOLpd7J9tvQU+utodDahOTLwOZCu ZKBjB3YfRca0QVG3aSHP/IrXGjnrQC8Us5Cnb+AXXV9Hib5rANQWeyEcU/NpvW8RRz9n WrlqW5aaOwqtffCtPqA1Qb9OAtYLlfiSBzVbCshpTprHWhM2D2ZBvcqZ1nSrh+75J0H8 AuY+EVYKLSE9xJettCoideYcrrVkEfYQYElcVug8a6Cpdg1ukp4XDV0TXbW822w/LsJA KfXZLnBmCQoXiNZViYYZnkwJoebGw+C6tNgGdFzHFsxXDk7hwbXmlUhS7xiP++lJ3p86 0sTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686556819; x=1689148819; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AIVXF0NWT+mxXgpNldoq9Ep8Ze5GWaI0IQCYTwDNGis=; b=P/ZFjL9AXtvq1//CP9ekW6hFPnoP7XsYpXX73wRnGXECDVUegE7UjyRUo6b0gawXII WLqwBJG+uvkunuV2iIuZIf237A+yTTSTcOq3xlAVCQJJumdtJQF5kJn62WxHRvCa4+Ug kBbSNcacYTNomsed4ZrJP0OoR1bX8+DovtcsE2Me9aFqM2g68AlQC52eKLt+iFQ8x7PZ SdVc7QQGHTREYnVT2AS2bPh5wVG2ZnsxfpB5A3/96danG69rHyGCEZUUNS/niJ5Df7/q GMXYhFgS3NeFVQfO9GgYeRwZ/YXSRHBYpzXYLosyZt3MeP3+tOHninb21osKd/EA5VUF X4pQ== X-Gm-Message-State: AC+VfDwL2zPmwmc9ZarbFl985foevy8ed4uM8dum5mdPG9uFg0G+10DM 8JPZEOMg9ype0hu9RQO5yGE= X-Google-Smtp-Source: ACHHUZ7rH24bSvXH68grWUUGmZeBJyddzDfqq2bN6iaVfLMn/bSdgzwUU/lcR0jP8SVBmxzLrMFDsg== X-Received: by 2002:a19:6d08:0:b0:4f6:3000:4d4d with SMTP id i8-20020a196d08000000b004f630004d4dmr3267707lfc.38.1686556818709; Mon, 12 Jun 2023 01:00:18 -0700 (PDT) Received: from arinc9-Xeront.lan (178-147-169-233.haap.dm.cosmote.net. [178.147.169.233]) by smtp.gmail.com with ESMTPSA id y22-20020a7bcd96000000b003f7f2a1484csm10552195wmj.5.2023.06.12.01.00.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jun 2023 01:00:18 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Landen Chao , Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net v4 7/7] MAINTAINERS: add me as maintainer of MEDIATEK SWITCH DRIVER Date: Mon, 12 Jun 2023 10:59:45 +0300 Message-Id: <20230612075945.16330-8-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612075945.16330-1-arinc.unal@arinc9.com> References: <20230612075945.16330-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Add me as a maintainer of the MediaTek MT7530 DSA subdriver. List maintainers in alphabetical order by first name. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Vladimir Oltean --- MAINTAINERS | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index a73e5a98503a..c58d7fbb40ed 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13259,10 +13259,11 @@ F: drivers/memory/mtk-smi.c F: include/soc/mediatek/smi.h =20 MEDIATEK SWITCH DRIVER -M: Sean Wang +M: Ar=C4=B1n=C3=A7 =C3=9CNAL +M: Daniel Golle M: Landen Chao M: DENG Qingfang -M: Daniel Golle +M: Sean Wang L: netdev@vger.kernel.org S: Maintained F: drivers/net/dsa/mt7530-mdio.c --=20 2.39.2