From nobody Sat Feb 7 11:05:25 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E88C6C7EE2E for ; Sun, 11 Jun 2023 11:12:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233654AbjFKLMi (ORCPT ); Sun, 11 Jun 2023 07:12:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233517AbjFKLMW (ORCPT ); Sun, 11 Jun 2023 07:12:22 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD3DA123; Sun, 11 Jun 2023 04:12:18 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 35BBBpqh037592; Sun, 11 Jun 2023 06:11:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1686481911; bh=rcr8C+huYL/f7qEEYGut3a7XI8NR7IhSakaGDuF9odg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=O5xV2YOk/thf0tM9r+fuaUF8jGekUIuF3PQO6lWLhz43KXlVmUyE5U9i6luiOuEwQ KlWwE4Bj++uv2Wn+6nrh+Vv/x0TQ4uftCPe83dy36XXEsjXje3Sp/vKSqg4cJHEjkp Q9DZdaDNr6+2z/50DiUfwk4AgMz+3jjzCAFa35nE= Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 35BBBpcL002304 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sun, 11 Jun 2023 06:11:51 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sun, 11 Jun 2023 06:11:51 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sun, 11 Jun 2023 06:11:51 -0500 Received: from udit-HP-Z2-Tower-G9-Workstation-Desktop-PC.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 35BBBh0x010303; Sun, 11 Jun 2023 06:11:47 -0500 From: Udit Kumar To: , , , , , , , , , , CC: Udit Kumar , Tony Lindgren Subject: [v4 1/6] arm64: dts: ti: k3-j7200: Add general purpose timers Date: Sun, 11 Jun 2023 16:41:35 +0530 Message-ID: <20230611111140.3189111-2-u-kumar1@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611111140.3189111-1-u-kumar1@ti.com> References: <20230611111140.3189111-1-u-kumar1@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There are 20 general purpose timers on j721e that can be used for things like PWM using pwm-omap-dmtimer driver. There are also additional ten timers in the MCU domain which are meant for MCU firmware usage and hence marked reserved by default. The odd numbered timers have the option of being cascaded to even timers to create a 64 bit non-atomic counter which is racy in simple usage, hence the clock muxes are explicitly setup to individual 32 bit counters driven off system crystal (HFOSC) as default. Signed-off-by: Udit Kumar Reviewed-by: Tony Lindgren Reviewed-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 240 ++++++++++++++++++ .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 130 ++++++++++ 2 files changed, 370 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j7200-main.dtsi index ef352e32f19d..c6b15aceea82 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -971,6 +971,246 @@ watchdog1: watchdog@2210000 { assigned-clock-parents =3D <&k3_clks 253 5>; }; =20 + main_timer0: timer@2400000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x2400000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 49 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 49 1>; + assigned-clock-parents =3D <&k3_clks 49 2>; + power-domains =3D <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x2410000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 50 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 50 1>, <&k3_clks 313 0>; + assigned-clock-parents =3D <&k3_clks 50 2>, <&k3_clks 313 1>; + power-domains =3D <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x2420000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 51 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 51 1>; + assigned-clock-parents =3D <&k3_clks 51 2>; + power-domains =3D <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x2430000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 52 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 52 1>, <&k3_clks 314 0>; + assigned-clock-parents =3D <&k3_clks 52 2>, <&k3_clks 314 1>; + power-domains =3D <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x2440000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 53 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 53 1>; + assigned-clock-parents =3D <&k3_clks 53 2>; + power-domains =3D <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x2450000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 54 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 54 1>, <&k3_clks 315 0>; + assigned-clock-parents =3D <&k3_clks 54 2>, <&k3_clks 315 1>; + power-domains =3D <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x2460000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 55 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 55 1>; + assigned-clock-parents =3D <&k3_clks 55 2>; + power-domains =3D <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x2470000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 57 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 57 1>, <&k3_clks 316 0>; + assigned-clock-parents =3D <&k3_clks 57 2>, <&k3_clks 316 1>; + power-domains =3D <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer8: timer@2480000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x2480000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 58 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 58 1>; + assigned-clock-parents =3D <&k3_clks 58 2>; + power-domains =3D <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer9: timer@2490000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x2490000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 59 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 59 1>, <&k3_clks 317 0>; + assigned-clock-parents =3D <&k3_clks 59 2>, <&k3_clks 317 1>; + power-domains =3D <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer10: timer@24a0000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x24a0000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 60 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 60 1>; + assigned-clock-parents =3D <&k3_clks 60 2>; + power-domains =3D <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer11: timer@24b0000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x24b0000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 62 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 62 1>, <&k3_clks 318 0>; + assigned-clock-parents =3D <&k3_clks 62 2>, <&k3_clks 318 1>; + power-domains =3D <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer12: timer@24c0000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x24c0000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 63 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 63 1>; + assigned-clock-parents =3D <&k3_clks 63 2>; + power-domains =3D <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer13: timer@24d0000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x24d0000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 64 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 64 1>, <&k3_clks 319 0>; + assigned-clock-parents =3D <&k3_clks 64 2>, <&k3_clks 319 1>; + power-domains =3D <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer14: timer@24e0000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x24e0000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 65 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 65 1>; + assigned-clock-parents =3D <&k3_clks 65 2>; + power-domains =3D <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer15: timer@24f0000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x24f0000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 66 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 66 1>, <&k3_clks 320 0>; + assigned-clock-parents =3D <&k3_clks 66 2>, <&k3_clks 320 1>; + power-domains =3D <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer16: timer@2500000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x2500000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 67 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 67 1>; + assigned-clock-parents =3D <&k3_clks 67 2>; + power-domains =3D <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer17: timer@2510000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x2510000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 68 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 68 1>, <&k3_clks 321 0>; + assigned-clock-parents =3D <&k3_clks 68 2>, <&k3_clks 321 1>; + power-domains =3D <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer18: timer@2520000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x2520000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 69 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 69 1>; + assigned-clock-parents =3D <&k3_clks 69 2>; + power-domains =3D <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer19: timer@2530000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x2530000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 70 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 70 1>, <&k3_clks 322 0>; + assigned-clock-parents =3D <&k3_clks 70 2>, <&k3_clks 322 1>; + power-domains =3D <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + main_r5fss0: r5fss@5c00000 { compatible =3D "ti,j7200-r5fss"; ti,cluster-mode =3D <1>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 674e695ef844..dcb6696cff17 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -34,6 +34,136 @@ k3_reset: reset-controller { }; }; =20 + mcu_timer0: timer@40400000 { + status =3D "reserved"; + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x40400000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 35 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 35 1>; + assigned-clock-parents =3D <&k3_clks 35 2>; + power-domains =3D <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer1: timer@40410000 { + status =3D "reserved"; + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x40410000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 71 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 71 1>, <&k3_clks 308 0>; + assigned-clock-parents =3D <&k3_clks 71 2>, <&k3_clks 308 1>; + power-domains =3D <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer2: timer@40420000 { + status =3D "reserved"; + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x40420000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 72 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 72 1>; + assigned-clock-parents =3D <&k3_clks 72 2>; + power-domains =3D <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer3: timer@40430000 { + status =3D "reserved"; + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x40430000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 73 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 73 1>, <&k3_clks 309 0>; + assigned-clock-parents =3D <&k3_clks 73 2>, <&k3_clks 309 1>; + power-domains =3D <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer4: timer@40440000 { + status =3D "reserved"; + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x40440000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 74 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 74 1>; + assigned-clock-parents =3D <&k3_clks 74 2>; + power-domains =3D <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer5: timer@40450000 { + status =3D "reserved"; + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x40450000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 75 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 75 1>, <&k3_clks 310 0>; + assigned-clock-parents =3D <&k3_clks 75 2>, <&k3_clks 310 1>; + power-domains =3D <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer6: timer@40460000 { + status =3D "reserved"; + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x40460000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 76 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 76 1>; + assigned-clock-parents =3D <&k3_clks 76 2>; + power-domains =3D <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer7: timer@40470000 { + status =3D "reserved"; + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x40470000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 77 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 77 1>, <&k3_clks 311 0>; + assigned-clock-parents =3D <&k3_clks 77 2>, <&k3_clks 311 1>; + power-domains =3D <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer8: timer@40480000 { + status =3D "reserved"; + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x40480000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 78 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 78 1>; + assigned-clock-parents =3D <&k3_clks 78 2>; + power-domains =3D <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer9: timer@40490000 { + status =3D "reserved"; + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x40490000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 79 1>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 79 1>, <&k3_clks 312 0>; + assigned-clock-parents =3D <&k3_clks 79 2>, <&k3_clks 312 1>; + power-domains =3D <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + mcu_conf: syscon@40f00000 { compatible =3D "syscon", "simple-mfd"; reg =3D <0x00 0x40f00000 0x00 0x20000>; --=20 2.34.1 From nobody Sat Feb 7 11:05:25 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02F05C83005 for ; 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Sun, 11 Jun 2023 06:11:55 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sun, 11 Jun 2023 06:11:54 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sun, 11 Jun 2023 06:11:54 -0500 Received: from udit-HP-Z2-Tower-G9-Workstation-Desktop-PC.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 35BBBh10010303; Sun, 11 Jun 2023 06:11:51 -0500 From: Udit Kumar To: , , , , , , , , , , CC: Udit Kumar , Tony Lindgren Subject: [v4 2/6] arm64: dts: ti: k3-j7200: Configure pinctrl for timer IO pads Date: Sun, 11 Jun 2023 16:41:36 +0530 Message-ID: <20230611111140.3189111-3-u-kumar1@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611111140.3189111-1-u-kumar1@ti.com> References: <20230611111140.3189111-1-u-kumar1@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There are timer IO pads in the MCU domain, and in the MAIN domain. These pads can be muxed for the related timers. There are timer IO control registers for input and output. The registers for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and CTRLMMR_MCU_TIMERIO*_CTRL the output. The multiplexing is documented in TRM "5.1.2.3.1.4 Timer IO Muxing Control Registers" and "5.1.3.3.1.5 Timer IO Muxing Control Registers", and the CASCADE_EN bit is documented in TRM "12.6.3.1 Timers Overview". For chaining timers, the timer IO control registers also have a CASCADE_EN input bit in the CTRLMMR_TIMER*_CTRL in the registers. The CASCADE_EN bit muxes the previous timer output, or possibly and external TIMER_IO pad source, to the input clock of the selected timer instance for odd numered timers. For the even numbered timers, the CASCADE_EN bit does not do anything. The timer cascade input routing options are shown in TRM "Figure 12-3224. Timers Overview". For handling beyond multiplexing, the driver support for timer cascading should be likely be handled via the clock framework. The MCU timer controls are also marked as reserved for usage by the MCU firmware. Cc: Nishanth Menon Cc: Vignesh Raghavendra Cc: Tony Lindgren Reviewed-by: Tony Lindgren Signed-off-by: Udit Kumar Reviewed-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 18 +++++++++++++++++ .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 20 +++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j7200-main.dtsi index c6b15aceea82..a9b3bf8a5c6a 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -392,6 +392,24 @@ cpts@3d000 { }; }; =20 + /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ + main_timerio_input: pinctrl@104200 { + compatible =3D "pinctrl-single"; + reg =3D <0x0 0x104200 0x0 0x50>; + #pinctrl-cells =3D <1>; + pinctrl-single,register-width =3D <32>; + pinctrl-single,function-mask =3D <0x000001ff>; + }; + + /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ + main_timerio_output: pinctrl@104280 { + compatible =3D "pinctrl-single"; + reg =3D <0x0 0x104280 0x0 0x20>; + #pinctrl-cells =3D <1>; + pinctrl-single,register-width =3D <32>; + pinctrl-single,function-mask =3D <0x0000001f>; + }; + main_pmx0: pinctrl@11c000 { compatible =3D "pinctrl-single"; /* Proxy 0 addressing */ diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j7200-mcu-wakeup.dtsi index dcb6696cff17..b518ec9eea32 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -183,6 +183,26 @@ chipid@43000014 { reg =3D <0x00 0x43000014 0x00 0x4>; }; =20 + /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ + mcu_timerio_input: pinctrl@40f04200 { + compatible =3D "pinctrl-single"; + reg =3D <0x0 0x40f04200 0x0 0x28>; + #pinctrl-cells =3D <1>; + pinctrl-single,register-width =3D <32>; + pinctrl-single,function-mask =3D <0x0000000F>; + status =3D "reserved"; + }; + + /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ + mcu_timerio_output: pinctrl@40f04280 { + compatible =3D "pinctrl-single"; + reg =3D <0x0 0x40f04280 0x0 0x28>; + #pinctrl-cells =3D <1>; + pinctrl-single,register-width =3D <32>; + pinctrl-single,function-mask =3D <0x0000000F>; + status =3D "reserved"; + }; + wkup_pmx0: pinctrl@4301c000 { compatible =3D "pinctrl-single"; /* Proxy 0 addressing */ --=20 2.34.1 From nobody Sat Feb 7 11:05:25 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 149ACC77B7A for ; Sun, 11 Jun 2023 11:12:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233523AbjFKLMW (ORCPT ); Sun, 11 Jun 2023 07:12:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34838 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232308AbjFKLMT (ORCPT ); Sun, 11 Jun 2023 07:12:19 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AEC841984; 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Sun, 11 Jun 2023 06:11:58 -0500 Received: from udit-HP-Z2-Tower-G9-Workstation-Desktop-PC.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 35BBBh11010303; Sun, 11 Jun 2023 06:11:55 -0500 From: Udit Kumar To: , , , , , , , , , , CC: Udit Kumar Subject: [v4 3/6] arm64: dts: ti: k3-j7200-common-proc-board: remove duplicate main_i2c0 pin mux Date: Sun, 11 Jun 2023 16:41:37 +0530 Message-ID: <20230611111140.3189111-4-u-kumar1@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611111140.3189111-1-u-kumar1@ti.com> References: <20230611111140.3189111-1-u-kumar1@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" main_i2c0 pin mux was duplicated in som and common file. So removing duplicated node from common file. Signed-off-by: Udit Kumar Reviewed-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 0cc0e1dc40c5..31b6501443b4 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -106,13 +106,6 @@ J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDI= O0_MDIO */ }; =20 &main_pmx0 { - main_i2c0_pins_default: main-i2c0-pins-default { - pinctrl-single,pins =3D < - J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ - J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ - >; - }; - main_i2c1_pins_default: main-i2c1-pins-default { pinctrl-single,pins =3D < J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_S= CL */ --=20 2.34.1 From nobody Sat Feb 7 11:05:25 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C4E3C7EE2E for ; Sun, 11 Jun 2023 11:12:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229746AbjFKLMb (ORCPT ); Sun, 11 Jun 2023 07:12:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34858 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233445AbjFKLMU (ORCPT ); Sun, 11 Jun 2023 07:12:20 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EEC97198C; Sun, 11 Jun 2023 04:12:17 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 35BBC2xL057640; Sun, 11 Jun 2023 06:12:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1686481922; bh=npbGbpRrLFgl60RMH9buwOQXvLGcxHJetMp7dwNYByA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=sHwcmM7FgSOCR+vpcW6LbYu3iUmP3gJELdjwaUuJ4JgAw+Ws6xjmoPyYBp9MT1lnf evV6VNsjO8lNf+KjFfm0+cdGtl85pOnCiWBjobRknv/SvtRfk2lqNgFH7Epvb+xxT5 4KzYCXkLJccxcKgbbyAmb4OGclOFDrKO7QZ5x2Lo= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 35BBC2m4002384 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sun, 11 Jun 2023 06:12:02 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sun, 11 Jun 2023 06:12:01 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sun, 11 Jun 2023 06:12:01 -0500 Received: from udit-HP-Z2-Tower-G9-Workstation-Desktop-PC.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 35BBBh12010303; Sun, 11 Jun 2023 06:11:58 -0500 From: Udit Kumar To: , , , , , , , , , , CC: Udit Kumar Subject: [v4 4/6] arm64: dts: ti: k3-j7200-common-proc-board: Add uart pinmux Date: Sun, 11 Jun 2023 16:41:38 +0530 Message-ID: <20230611111140.3189111-5-u-kumar1@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611111140.3189111-1-u-kumar1@ti.com> References: <20230611111140.3189111-1-u-kumar1@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add main, mcu, wakeup domain uart0 pin mux into common board file and it's reference to uart node. Signed-off-by: Udit Kumar Reviewed-by: Nishanth Menon --- .../dts/ti/k3-j7200-common-proc-board.dts | 58 ++++++++++++++++++- 1 file changed, 57 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 31b6501443b4..5569d48b900c 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -79,6 +79,24 @@ vdd_sd_dv: gpio-regulator-TLV71033 { }; }; =20 +&wkup_pmx0 { + mcu_uart0_pins_default: mcu-uart0-pins-default { + pinctrl-single,pins =3D < + J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ + J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ + J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */ + J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */ + >; + }; + + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins =3D < + J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ + J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ + >; + }; +}; + &wkup_pmx2 { mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins =3D < @@ -106,6 +124,29 @@ J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDI= O0_MDIO */ }; =20 &main_pmx0 { + main_uart0_pins_default: main-uart0-pins-default { + pinctrl-single,pins =3D < + J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */ + J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */ + J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */ + J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */ + >; + }; + + main_uart1_pins_default: main-uart1-pins-default { + pinctrl-single,pins =3D < + J721E_IOPAD(0xb8, PIN_INPUT, 0) /* (T18) UART1_RXD */ + J721E_IOPAD(0xbc, PIN_INPUT, 0) /* (T20) UART1_TXD */ + >; + }; + + main_uart3_pins_default: main-uart3-pins-default { + pinctrl-single,pins =3D < + J721E_IOPAD(0x60, PIN_INPUT, 11) /* (T15) MCAN8_TX.UART3_CTSn */ + J721E_IOPAD(0x30, PIN_INPUT, 11) /* (Y18) MCAN2_TX.UART3_RXD */ + >; + }; + main_i2c1_pins_default: main-i2c1-pins-default { pinctrl-single,pins =3D < J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_S= CL */ @@ -144,22 +185,30 @@ J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS= */ &wkup_uart0 { /* Wakeup UART is used by System firmware */ status =3D "reserved"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wkup_uart0_pins_default>; }; =20 &mcu_uart0 { status =3D "okay"; - /* Default pinmux */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_uart0_pins_default>; + clock-frequency =3D <96000000>; }; =20 &main_uart0 { status =3D "okay"; /* Shared with ATF on this platform */ power-domains =3D <&k3_pds 146 TI_SCI_PD_SHARED>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_uart0_pins_default>; }; =20 &main_uart1 { status =3D "okay"; /* Default pinmux */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_uart1_pins_default>; }; =20 &main_uart2 { @@ -167,6 +216,13 @@ &main_uart2 { status =3D "reserved"; }; =20 +&main_uart3 { + /* Shared with MCAN Interface */ + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_uart3_pins_default>; +}; + &main_gpio2 { status =3D "disabled"; }; --=20 2.34.1 From nobody Sat Feb 7 11:05:25 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AC42C7EE45 for ; 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Sun, 11 Jun 2023 06:12:05 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sun, 11 Jun 2023 06:12:05 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sun, 11 Jun 2023 06:12:05 -0500 Received: from udit-HP-Z2-Tower-G9-Workstation-Desktop-PC.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 35BBBh13010303; Sun, 11 Jun 2023 06:12:02 -0500 From: Udit Kumar To: , , , , , , , , , , CC: Udit Kumar Subject: [v4 5/6] arm64: dts: ti: k3-j7200-common-proc-board: Define aliases at board level Date: Sun, 11 Jun 2023 16:41:39 +0530 Message-ID: <20230611111140.3189111-6-u-kumar1@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611111140.3189111-1-u-kumar1@ti.com> References: <20230611111140.3189111-1-u-kumar1@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Define aliases at board level Signed-off-by: Udit Kumar Reviewed-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 5569d48b900c..38b48115ed0d 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -15,6 +15,16 @@ / { compatible =3D "ti,j7200-evm", "ti,j7200"; model =3D "Texas Instruments J7200 EVM"; =20 + aliases { + serial0 =3D &wkup_uart0; + serial1 =3D &mcu_uart0; + serial2 =3D &main_uart0; + serial3 =3D &main_uart1; + serial5 =3D &main_uart3; + mmc0 =3D &main_sdhci0; + mmc1 =3D &main_sdhci1; + }; + chosen { stdout-path =3D "serial2:115200n8"; }; --=20 2.34.1 From nobody Sat Feb 7 11:05:25 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E8BAC7EE2E for ; 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Sun, 11 Jun 2023 06:12:09 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sun, 11 Jun 2023 06:12:08 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sun, 11 Jun 2023 06:12:08 -0500 Received: from udit-HP-Z2-Tower-G9-Workstation-Desktop-PC.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 35BBBh14010303; Sun, 11 Jun 2023 06:12:05 -0500 From: Udit Kumar To: , , , , , , , , , , CC: Udit Kumar Subject: [v4 6/6] arm64: dts: ti: k3-j7200: Drop SoC level aliases Date: Sun, 11 Jun 2023 16:41:40 +0530 Message-ID: <20230611111140.3189111-7-u-kumar1@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611111140.3189111-1-u-kumar1@ti.com> References: <20230611111140.3189111-1-u-kumar1@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Aiases are defined at board level, so dropping from soc level Signed-off-by: Udit Kumar Reviewed-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j7200.dtsi | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/= k3-j7200.dtsi index f1836ec8e934..5ea869014bbc 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi @@ -18,23 +18,6 @@ / { #address-cells =3D <2>; #size-cells =3D <2>; =20 - aliases { - serial0 =3D &wkup_uart0; - serial1 =3D &mcu_uart0; - serial2 =3D &main_uart0; - serial3 =3D &main_uart1; - serial4 =3D &main_uart2; - serial5 =3D &main_uart3; - serial6 =3D &main_uart4; - serial7 =3D &main_uart5; - serial8 =3D &main_uart6; - serial9 =3D &main_uart7; - serial10 =3D &main_uart8; - serial11 =3D &main_uart9; - mmc0 =3D &main_sdhci0; - mmc1 =3D &main_sdhci1; - }; - chosen { }; =20 cpus { --=20 2.34.1