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[178.147.169.233]) by smtp.gmail.com with ESMTPSA id 17-20020a05600c22d100b003f8044b3436sm7394629wmg.23.2023.06.11.01.39.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 01:39:21 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Landen Chao , Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net v3 1/7] net: dsa: mt7530: fix trapping frames with multiple CPU ports on MT7531 Date: Sun, 11 Jun 2023 11:39:08 +0300 Message-Id: <20230611083914.28603-2-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230611083914.28603-1-arinc.unal@arinc9.com> References: <20230611083914.28603-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Every bit of the CPU port bitmap for MT7531 and the switch on the MT7988 SoC represents a CPU port to trap frames to. These switches trap frames to the CPU port the user port, which the frames are received from, is affine to. Currently, only the bit that corresponds to the first found CPU port is set on the bitmap. When multiple CPU ports are being used, frames from the user ports affine to the other CPU port which are set to be trapped will be dropped as the affine CPU port is not set on the bitmap. Only the MT7531 switch is affected as there's only one port to be used as a CPU port on the switch on the MT7988 SoC. To fix this, introduce the MT7531_CPU_PMAP macro to individually set the bits of the CPU port bitmap. Set the CPU port bitmap for MT7531 and the switch on the MT7988 SoC on mt753x_cpu_port_enable() which runs on a loop for each CPU port. Add comments to explain frame trapping for these switches. According to the document MT7531 Reference Manual for Development Board v1.0, the MT7531_CPU_PMAP bits are unset after reset so no need to clear it beforehand. Since there's currently no public document for the switch on the MT7988 SoC, I assume this is also the case for this switch. Fixes: c288575f7810 ("net: dsa: mt7530: Add the support of MT7531 switch") Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 16 +++++++++------- drivers/net/dsa/mt7530.h | 1 + 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 9bc54e1348cb..8ab4718abb06 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -1010,6 +1010,14 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int po= rt) if (priv->id =3D=3D ID_MT7621) mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); =20 + /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on + * the MT7988 SoC. Any frames set for trapping to CPU port will be + * trapped to the CPU port the user port, which the frames are received + * from, is affine to. + */ + if (priv->id =3D=3D ID_MT7531 || priv->id =3D=3D ID_MT7988) + mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port))); + /* CPU port gets connected to all user ports of * the switch. */ @@ -2352,15 +2360,9 @@ static int mt7531_setup_common(struct dsa_switch *ds) { struct mt7530_priv *priv =3D ds->priv; - struct dsa_port *cpu_dp; int ret, i; =20 - /* BPDU to CPU port */ - dsa_switch_for_each_cpu_port(cpu_dp, ds) { - mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, - BIT(cpu_dp->index)); - break; - } + /* Trap BPDUs to the CPU port(s) */ mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, MT753X_BPDU_CPU_ONLY); =20 diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 5084f48a8869..e590cf43f3ae 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -54,6 +54,7 @@ enum mt753x_id { #define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK) #define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16) #define MT7531_CPU_PMAP_MASK GENMASK(7, 0) +#define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x) =20 #define MT753X_MIRROR_REG(id) ((((id) =3D=3D ID_MT7531) || ((id) =3D=3D I= D_MT7988)) ? \ MT7531_CFC : MT7530_MFC) --=20 2.39.2 From nobody Fri Sep 20 16:40:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67C4AC7EE2E for ; Sun, 11 Jun 2023 08:39:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233352AbjFKIjf (ORCPT ); Sun, 11 Jun 2023 04:39:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40140 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233243AbjFKIj2 (ORCPT ); Sun, 11 Jun 2023 04:39:28 -0400 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC0F92136; Sun, 11 Jun 2023 01:39:26 -0700 (PDT) Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-3f7f6341b99so23920955e9.2; Sun, 11 Jun 2023 01:39:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686472765; x=1689064765; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aGjSubHB5nyBi9j8FAFQdMcIlI87DT0LBIyRr04BO1s=; b=PNU5zVDx2CelSpV0Ev7A+zsdWWBzu9WqPi5au1pRJoFaqgzwAzPFOKRmki5m2JAfta EurquF9ue3YFhSmqmHgNHjg9OVWfuBvn80zg5K97MDCKqLeE2PtE1ElTwUOIGdKslVWm sDXA+9Gzcik7aY/s6X1Yx9eiMYq3XA36u728Kr/ZVIn0kLYpQMWMhspQqjYzfImdulyd MLGXR/IiGJgf1OuN7PPZo8X0dZ7LKGBwVOd2A2SJjiqYnRfuLXFXi/LIltVo7Fv84pNx iX5IspBCFXQakEeonH3w5dcDMJjzZ54GItWx14PGMiZVjdJO1u8+70c/D9OHsdMR1rc1 cHJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686472765; x=1689064765; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aGjSubHB5nyBi9j8FAFQdMcIlI87DT0LBIyRr04BO1s=; b=SetRpR8ggUW2C4GmOfdEVFcsUR4h7KCJjT/523+oO2Qz/H8fWwn/Ba+eJr4LSme4/G qN6hvh6BXYr+nBNXZa5E71GlplfuihHRcCMRnzNGYfbuRjG5AdHk/WNisnb94dVAgECK RAOOzliyH1fAx2g7gBfjEJE9SGcwDXDP1wCaWH4l7uHLlnmIJ+l5KBqj5Cx04j74B7Jo ZEjwGldPfjgxD7iYc16aFADHwEXhZBWvoKgDuPSqfnpZosHuTQsFF5Fh2d1yPbiQ/cRQ ONiot0+fsk+phu3wNIJ35UNGIcsZ1x7aHAZa76Z6oTl4sl6PV5D90xbFDLWOti79XChU h0Qw== X-Gm-Message-State: AC+VfDw/WcGydMK+oC761GQqzqMbM5dl9G4Mx3jRbkp3/UulSMKaiR6U MN1EibFfyqKpsoY2tkA7Kw8= X-Google-Smtp-Source: ACHHUZ47Yo4aCctQJTM6/sgph7/C53Vo6Ns/4gbAaKuHVHeqrz74CbHq7XcgsterxVaPmL3Oq1SFMw== X-Received: by 2002:a05:600c:2291:b0:3f6:1a3:4cee with SMTP id 17-20020a05600c229100b003f601a34ceemr4653033wmf.14.1686472765218; Sun, 11 Jun 2023 01:39:25 -0700 (PDT) Received: from arinc9-Xeront.lan (178-147-169-233.haap.dm.cosmote.net. [178.147.169.233]) by smtp.gmail.com with ESMTPSA id 17-20020a05600c22d100b003f8044b3436sm7394629wmg.23.2023.06.11.01.39.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 01:39:24 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Landen Chao , Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net v3 2/7] net: dsa: mt7530: fix trapping frames with multiple CPU ports on MT7530 Date: Sun, 11 Jun 2023 11:39:09 +0300 Message-Id: <20230611083914.28603-3-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230611083914.28603-1-arinc.unal@arinc9.com> References: <20230611083914.28603-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL The CPU_PORT bits represent the CPU port to trap frames to for the MT7530 switch. This switch traps frames to the CPU port set on the CPU_PORT bits, regardless of the affinity of the user port which the frames are received from. When multiple CPU ports are being used, the trapped frames won't be received when the DSA conduit interface, which the frames are supposed to be trapped to, is down because it's not affine to any user port. This requires the DSA conduit interface to be manually set up for the trapped frames to be received. To fix this, implement ds->ops->master_state_change() on this subdriver and set the CPU_PORT bits to the CPU port which the DSA conduit interface its affine to is up. Introduce the active_cpu_ports field to store the information of the active CPU ports. Correct the macros, CPU_PORT is bits 4 through 6 of the register. Add comments to explain frame trapping for this switch. Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 sw= itch") Suggested-by: Vladimir Oltean Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 32 ++++++++++++++++++++++++++++---- drivers/net/dsa/mt7530.h | 6 ++++-- 2 files changed, 32 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 8ab4718abb06..da75f9b312bc 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -1006,10 +1006,6 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int po= rt) mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port))); =20 - /* Set CPU port number */ - if (priv->id =3D=3D ID_MT7621) - mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); - /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on * the MT7988 SoC. Any frames set for trapping to CPU port will be * trapped to the CPU port the user port, which the frames are received @@ -3063,6 +3059,33 @@ static int mt753x_set_mac_eee(struct dsa_switch *ds,= int port, return 0; } =20 +static void +mt753x_master_state_change(struct dsa_switch *ds, + const struct net_device *master, + bool operational) +{ + struct mt7530_priv *priv =3D ds->priv; + struct dsa_port *cpu_dp =3D master->dsa_ptr; + + /* Set the CPU port to trap frames to for MT7530. There can be only one + * CPU port due to CPU_PORT having only 3 bits. Any frames received from + * a user port which are set for trapping to CPU port will be trapped to + * the numerically smallest CPU port which is affine to the DSA conduit + * interface that is up. + */ + if (priv->id !=3D ID_MT7621) + return; + + if (operational) + priv->active_cpu_ports |=3D BIT(cpu_dp->index); + else + priv->active_cpu_ports &=3D ~BIT(cpu_dp->index); + + if (priv->active_cpu_ports) + mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, CPU_EN | + CPU_PORT(__ffs(priv->active_cpu_ports))); +} + static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interfa= ce) { return 0; @@ -3117,6 +3140,7 @@ const struct dsa_switch_ops mt7530_switch_ops =3D { .phylink_mac_link_up =3D mt753x_phylink_mac_link_up, .get_mac_eee =3D mt753x_get_mac_eee, .set_mac_eee =3D mt753x_set_mac_eee, + .master_state_change =3D mt753x_master_state_change, }; EXPORT_SYMBOL_GPL(mt7530_switch_ops); =20 diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index e590cf43f3ae..28dbd131a535 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -41,8 +41,8 @@ enum mt753x_id { #define UNU_FFP(x) (((x) & 0xff) << 8) #define UNU_FFP_MASK UNU_FFP(~0) #define CPU_EN BIT(7) -#define CPU_PORT(x) ((x) << 4) -#define CPU_MASK (0xf << 4) +#define CPU_PORT_MASK GENMASK(6, 4) +#define CPU_PORT(x) FIELD_PREP(CPU_PORT_MASK, x) #define MIRROR_EN BIT(3) #define MIRROR_PORT(x) ((x) & 0x7) #define MIRROR_MASK 0x7 @@ -753,6 +753,7 @@ struct mt753x_info { * @irq_domain: IRQ domain of the switch irq_chip * @irq_enable: IRQ enable bits, synced to SYS_INT_EN * @create_sgmii: Pointer to function creating SGMII PCS instance(s) + * @active_cpu_ports: Holding the active CPU ports */ struct mt7530_priv { struct device *dev; @@ -779,6 +780,7 @@ struct mt7530_priv { struct irq_domain *irq_domain; u32 irq_enable; int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii); + unsigned long active_cpu_ports; }; =20 struct mt7530_hw_vlan_entry { --=20 2.39.2 From nobody Fri Sep 20 16:40:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59023C7EE2E for ; Sun, 11 Jun 2023 08:39:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233425AbjFKIjm (ORCPT ); Sun, 11 Jun 2023 04:39:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233328AbjFKIjc (ORCPT ); Sun, 11 Jun 2023 04:39:32 -0400 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7E07B2136; Sun, 11 Jun 2023 01:39:30 -0700 (PDT) Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-3f7e7fc9fe6so32652105e9.3; Sun, 11 Jun 2023 01:39:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686472769; x=1689064769; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f09kXODUN5iNYLPQ79n740eNlnLbhpMepUm6pYfWMww=; b=C/fGGl6ASR0cY/wWkKRZtQQ4KpGLYV9M+zANFT52eDrclJ0wCbtsjkKhWrzWrDHd/n u2JbTgb6Kz4l2JhvVw+5y5dJGCqblfSdv28SbtY6yrGrE9dL8GV7OX9RkE4m6khAV4oL HZtbLbpQCn/WhcdT3BrfJaagczpFAP1FLELKkbi/DMGkx9c6lLMP7kEe9CbKTd4GrQ1r CxnTbVrYwNm19qtPAfPJKnlODci+4HHRa2ToVubD6L1UjRIw0PYfqAmSNxfmnCgucJAv NRvBwU3AHH0cFNx6UmSY3vhvGhMfAerb0MUMU/aIaU6Wd6r+AGxkii3D9b3GFFFMhfQk nsIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686472769; x=1689064769; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f09kXODUN5iNYLPQ79n740eNlnLbhpMepUm6pYfWMww=; b=aW8ui1dc5zfCTdHxGg5iP5nv3EJvp1EMmzHDOAIDt6Ya+srfrd5oJQoLt3YlRcMkLq L1A+Dhh23JKxKgOfMXMAzjGny8CbT4mpO3KHC8qLe6CIB3aTXuJRowmrqE8NZxciYrEn Q1uBC02XDcfIdWZqU+X0si+gOubsA+EM512BnvPEYWpH1FQKHg43jDhjuGT6UG+klutH 6HVcY4c6MjZ/C5jIQKNIZu11kAEqc8aypm+fhPpHnc5B7FJDNEMym9Sx+64F7XT+OLNt xhg8HZpY2IDz8y0eDDmQsalWDyBv8awoJewnkN6P5GkttRWnTAg98BGZmzvVSKhJ9db3 1L4g== X-Gm-Message-State: AC+VfDyido0MOT1sZaq0V7ToiN3lvtUzIQcXNL9EAf09kpcKLXeLM9Om 3x9wqbUZkmrJNh2CJ1GsmjU= X-Google-Smtp-Source: ACHHUZ6I7W3aULN9NVIUPkKt8BHEZeda5LOSEjeuWyIokENebTg8/N4IOGkT5DCztsx5csgtjhw8ug== X-Received: by 2002:a05:600c:ac7:b0:3f7:38e1:5e5a with SMTP id c7-20020a05600c0ac700b003f738e15e5amr4744827wmr.33.1686472768980; Sun, 11 Jun 2023 01:39:28 -0700 (PDT) Received: from arinc9-Xeront.lan (178-147-169-233.haap.dm.cosmote.net. [178.147.169.233]) by smtp.gmail.com with ESMTPSA id 17-20020a05600c22d100b003f8044b3436sm7394629wmg.23.2023.06.11.01.39.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 01:39:28 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Landen Chao , Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net v3 3/7] net: dsa: mt7530: fix trapping frames on non-MT7621 SoC MT7530 switch Date: Sun, 11 Jun 2023 11:39:10 +0300 Message-Id: <20230611083914.28603-4-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230611083914.28603-1-arinc.unal@arinc9.com> References: <20230611083914.28603-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL The check for setting the CPU_PORT bits must include the non-MT7621 SoC MT7530 switch variants to trap frames. Expand the check to include them. Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 sw= itch") Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index da75f9b312bc..df2626f72367 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -3073,7 +3073,7 @@ mt753x_master_state_change(struct dsa_switch *ds, * the numerically smallest CPU port which is affine to the DSA conduit * interface that is up. */ - if (priv->id !=3D ID_MT7621) + if (priv->id !=3D ID_MT7530 && priv->id !=3D ID_MT7621) return; =20 if (operational) --=20 2.39.2 From nobody Fri Sep 20 16:40:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E722CC7EE23 for ; Sun, 11 Jun 2023 08:39:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230468AbjFKIjr (ORCPT ); Sun, 11 Jun 2023 04:39:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233339AbjFKIje (ORCPT ); Sun, 11 Jun 2023 04:39:34 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34FEF26B0; Sun, 11 Jun 2023 01:39:33 -0700 (PDT) Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-3f7fc9014fdso23691875e9.3; Sun, 11 Jun 2023 01:39:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686472771; x=1689064771; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FQB4VuigsMedHCtX/KwIwxZ3hq2ZGXrdSk/vXxwDWOc=; b=A/0zUzEiWv8PMoQ/ihdeZFYygXwdSne9zmBgI5K7ovfCCxWSobu1Mwppkhy2w8glNu MYhdVuRgTCRIdlSFHClY/yvO1AQspAksVr3tyaKl+LQiylhN5CxMK8aEbajYniuGMWK9 Z24Y6XvKM0Ck6/2rnuAwrTA4388TWF8iwVX8hCuQ5uIowGEko8jll+8Xwvk/WeXEc1CH vbT2UEvkBK4pTh8WcD0CKAxmuN153lL5HPdQbIxfzKx3SPIbkZikXvyGnUbp42KIYi0o Gtyr5196ivwP34HfIM4ebUzOzxEF5Ka3P7Lo82AvpkpllHEn6mWDBRQDOgykuy82ZPKr uOEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686472771; x=1689064771; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FQB4VuigsMedHCtX/KwIwxZ3hq2ZGXrdSk/vXxwDWOc=; b=UOzHwLVIf0IKhOWa9MTIVdMYyH2FS+0dmX3IlgccEtllJhsBC4IWBDbG+GMTMClAKR xzkjaD3WR1skFbpoZy595HzM2cfy+3MacUhoxsZ6vpcv53J9GHzTo/ITZEH17Fgedv0n n6MacAzHynQ2DBuZVer6FIPP/ohlzhqcKcFzSpEA4XWu8HKGqmGRtkSWGFuKe3tQzY5v 5KCfl3uAxUljOL5yCr83CgBYotMtarCW3hW4ZCQ4SEK0lACXWIytkbN1bfM8iLZEa7Rw ZJcbJiBdYwzUjHpAHQrQk3NrpCs/ZsAW0LILeZh4M83jhOMyz9JL9eCF50jT4Wfe4Oba fgEg== X-Gm-Message-State: AC+VfDxL58VKE81Po2GgPeYFq7Q8fKkSvFT7NIfzj43RSYVUeYK4bEwb yQusMJvLy3+4LFsjbSzXcOw= X-Google-Smtp-Source: ACHHUZ5WmPo6ky+0h5mL3oF6BdInjOv/GMMzhWmmzV0x6rKPo/vlw11QC42WnHwwdN9ge9Z26AQ7IQ== X-Received: by 2002:a05:600c:2190:b0:3f7:395a:c9fa with SMTP id e16-20020a05600c219000b003f7395ac9famr4721374wme.4.1686472771675; Sun, 11 Jun 2023 01:39:31 -0700 (PDT) Received: from arinc9-Xeront.lan (178-147-169-233.haap.dm.cosmote.net. [178.147.169.233]) by smtp.gmail.com with ESMTPSA id 17-20020a05600c22d100b003f8044b3436sm7394629wmg.23.2023.06.11.01.39.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 01:39:31 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Landen Chao , Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net v3 4/7] net: dsa: mt7530: fix handling of BPDUs on MT7530 switch Date: Sun, 11 Jun 2023 11:39:11 +0300 Message-Id: <20230611083914.28603-5-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230611083914.28603-1-arinc.unal@arinc9.com> References: <20230611083914.28603-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL BPDUs are link-local frames, therefore they must be trapped to the CPU port. Currently, the MT7530 switch treats BPDUs as regular multicast frames, therefore flooding them to user ports. To fix this, set BPDUs to be trapped to the CPU port. BPDUs received from a user port will be trapped to the numerically smallest CPU port which is affine to the DSA conduit interface that is up. Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 sw= itch") Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- v2: Add this patch. --- drivers/net/dsa/mt7530.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index df2626f72367..c2af23f2bc5d 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2259,6 +2259,10 @@ mt7530_setup(struct dsa_switch *ds) =20 priv->p6_interface =3D PHY_INTERFACE_MODE_NA; =20 + /* Trap BPDUs to the CPU port */ + mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, + MT753X_BPDU_CPU_ONLY); + /* Enable and reset MIB counters */ mt7530_mib_reset(ds); =20 --=20 2.39.2 From nobody Fri Sep 20 16:40:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7FF3CC7EE23 for ; Sun, 11 Jun 2023 08:39:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233339AbjFKIjv (ORCPT ); Sun, 11 Jun 2023 04:39:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233243AbjFKIjh (ORCPT ); Sun, 11 Jun 2023 04:39:37 -0400 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1ADD126B1; Sun, 11 Jun 2023 01:39:36 -0700 (PDT) Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-3f732d37d7cso32918305e9.2; Sun, 11 Jun 2023 01:39:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686472774; x=1689064774; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MawcVePra1qezae3jM9kLNrcTxxlCRgwx7hsVh8Pm7k=; b=T6xo+Zdt9hy/a3FOPQcorLiZmiUptS1PemQ75IHPcbz7eMZ5jRzmbVlKSvnohuHJmK 1dN5QBnhDNGdE5lR8ZPpwdBZ4uMOEN0OxRkZOdi0P1y5OEK3cxUzJvJrM3NnEwnyrOtX RDBNUhlBB3IvEhkaEZdGOwam1Or/F6Qf/MOAomKky00Lh9fT/jqbRBfnbtNacKK244eY G2m3RJ3cBUwJFg8tE5fniVAXFGE/qemMMgaCI0mFdNmiEl7PG/5yshtQZMdtw34XMo6R CHSvHw1kA97pN/B/si3VIR/ADUq3oP33KwEya9+AQGgNoStrV7hGuV0bG34zomOG6lTr BwtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686472774; x=1689064774; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MawcVePra1qezae3jM9kLNrcTxxlCRgwx7hsVh8Pm7k=; b=C1l3GcpyOB4x2mjyNXebf69+SAXH3M25xC0uTBngzVZOFs2+4Ainn5ONmJblge3aIg T9q/UafWFsKqU3PsKxFBguM0Tbs++8qqDPofz6yW0zV7mb5+tL0EILw5gDBHcuFIh3zZ S9RHPiqyv0RsEhKSrBuh8dxx22H3QVtg/H82gns7Y6SVXYFy65dkoi0TAjLTh6VTNI7v jrKkWPslsP+50FlLyvGvf/1mMa8y2TFcS+t6nOdOb6xjntVFhKQeTWLjtk7X5LmJsfYP IWr7joO1Lv8ebTJB2akAceAJEJgsJ8gvqnVU5Yj0Uo1MSmspscbnNeN9kLouSQCKbYLm pwaw== X-Gm-Message-State: AC+VfDy2pYjGybdf1HLnYirzpf370HXsB1OEjKm6QPBvkTSmazssoR+W PAojl438svJQ0o5N/zjNR0M= X-Google-Smtp-Source: ACHHUZ4OHnQrAXoJ6/BuM+FWQspwC/JIQ4feX6or84CeOcTTlPRSy8pKOgrR4bUD/OHBsM/HrrSJhg== X-Received: by 2002:a05:600c:290:b0:3f7:f7d5:a07f with SMTP id 16-20020a05600c029000b003f7f7d5a07fmr5112604wmk.17.1686472774459; Sun, 11 Jun 2023 01:39:34 -0700 (PDT) Received: from arinc9-Xeront.lan (178-147-169-233.haap.dm.cosmote.net. [178.147.169.233]) by smtp.gmail.com with ESMTPSA id 17-20020a05600c22d100b003f8044b3436sm7394629wmg.23.2023.06.11.01.39.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 01:39:34 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Landen Chao , Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net v3 5/7] net: dsa: mt7530: fix handling of LLDP frames Date: Sun, 11 Jun 2023 11:39:12 +0300 Message-Id: <20230611083914.28603-6-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230611083914.28603-1-arinc.unal@arinc9.com> References: <20230611083914.28603-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL LLDP frames are link-local frames, therefore they must be trapped to the CPU port. Currently, the MT753X switches treat LLDP frames as regular multicast frames, therefore flooding them to user ports. To fix this, set LLDP frames to be trapped to the CPU port(s). The mt753x_bpdu_port_fw enum is universally used for trapping frames, therefore rename it and the values in it to mt753x_port_fw. For MT7530, LLDP frames received from a user port will be trapped to the numerically smallest CPU port which is affine to the DSA conduit interface that is up. For MT7531 and the switch on the MT7988 SoC, LLDP frames received from a user port will be trapped to the CPU port the user port is affine to. The bit for R0E_MANG_FR is 27. When set, the switch regards the frames with :0E MAC DA as management (LLDP) frames. This bit is set to 1 after reset on MT7530 and MT7531 according to the documents MT7620 Programming Guide v1.0 and MT7531 Reference Manual for Development Board v1.0, so there's no need to deal with this bit. Since there's currently no public document for the switch on the MT7988 SoC, I assume this is also the case for this switch. Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 sw= itch") Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- v2: Add this patch. --- drivers/net/dsa/mt7530.c | 12 ++++++++++-- drivers/net/dsa/mt7530.h | 19 ++++++++++++------- 2 files changed, 22 insertions(+), 9 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index c2af23f2bc5d..97f389f8d6ea 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2261,7 +2261,11 @@ mt7530_setup(struct dsa_switch *ds) =20 /* Trap BPDUs to the CPU port */ mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, - MT753X_BPDU_CPU_ONLY); + MT753X_PORT_FW_CPU_ONLY); + + /* Trap LLDP frames with :0E MAC DA to the CPU port */ + mt7530_rmw(priv, MT753X_RGAC2, MT753X_R0E_PORT_FW_MASK, + MT753X_R0E_PORT_FW(MT753X_PORT_FW_CPU_ONLY)); =20 /* Enable and reset MIB counters */ mt7530_mib_reset(ds); @@ -2364,7 +2368,11 @@ mt7531_setup_common(struct dsa_switch *ds) =20 /* Trap BPDUs to the CPU port(s) */ mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, - MT753X_BPDU_CPU_ONLY); + MT753X_PORT_FW_CPU_ONLY); + + /* Trap LLDP frames with :0E MAC DA to the CPU port(s) */ + mt7530_rmw(priv, MT753X_RGAC2, MT753X_R0E_PORT_FW_MASK, + MT753X_R0E_PORT_FW(MT753X_PORT_FW_CPU_ONLY)); =20 /* Enable and reset MIB counters */ mt7530_mib_reset(ds); diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 28dbd131a535..5f048af2d89f 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -63,16 +63,21 @@ enum mt753x_id { #define MT753X_MIRROR_MASK(id) ((((id) =3D=3D ID_MT7531) || ((id) =3D=3D = ID_MT7988)) ? \ MT7531_MIRROR_MASK : MIRROR_MASK) =20 -/* Registers for BPDU and PAE frame control*/ +/* Register for BPDU and PAE frame control */ #define MT753X_BPC 0x24 #define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0) =20 -enum mt753x_bpdu_port_fw { - MT753X_BPDU_FOLLOW_MFC, - MT753X_BPDU_CPU_EXCLUDE =3D 4, - MT753X_BPDU_CPU_INCLUDE =3D 5, - MT753X_BPDU_CPU_ONLY =3D 6, - MT753X_BPDU_DROP =3D 7, +/* Register for :03 and :0E MAC DA frame control */ +#define MT753X_RGAC2 0x2c +#define MT753X_R0E_PORT_FW_MASK GENMASK(18, 16) +#define MT753X_R0E_PORT_FW(x) FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x) + +enum mt753x_port_fw { + MT753X_PORT_FW_FOLLOW_MFC, + MT753X_PORT_FW_CPU_EXCLUDE =3D 4, + MT753X_PORT_FW_CPU_INCLUDE =3D 5, + MT753X_PORT_FW_CPU_ONLY =3D 6, + MT753X_PORT_FW_DROP =3D 7, }; =20 /* Registers for address table access */ --=20 2.39.2 From nobody Fri Sep 20 16:40:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0958BC7EE2E for ; Sun, 11 Jun 2023 08:40:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233473AbjFKIj7 (ORCPT ); Sun, 11 Jun 2023 04:39:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233414AbjFKIjk (ORCPT ); Sun, 11 Jun 2023 04:39:40 -0400 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 069AA270F; Sun, 11 Jun 2023 01:39:37 -0700 (PDT) Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-3f7f6341b99so23921475e9.2; Sun, 11 Jun 2023 01:39:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686472777; x=1689064777; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MAnAZVSPifd50CdoCXOUbyrbAVvi3EcR5cj3t2QSLWo=; b=NAcl+hecbl7ELRNNe0Tm7sD7y7VxCoaTm2Kwc+7EADc9UhIYJjsylcrIo9nklwLGtv LvrHD5jaeN5WGZlUeM5Us2afaIBN1mFuWpoYGS2FI1YfTIVT2GUZHeCf9SaI0VYfJc++ TMjk1v7m4DSAdQ2xMlDMjlwD04EfPRTy+iv7cSPOFBOPldxaYa/id0x01UhH9GtQ3SZK 8HHiVEm/4UJG6zc+zkmTDC1SsNM1GQX2I8dOn8yv8AYNcu2ZunPqlV8oQBJ6I7zvj8Uv 5vgnHhBVCXxqZbR9eJpFmSwbfNH8Ys+4OKac8sK1OPLN1Yd6mu0sFYh0wI/GFP30cvfE avEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686472777; x=1689064777; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MAnAZVSPifd50CdoCXOUbyrbAVvi3EcR5cj3t2QSLWo=; b=b8GLm6vq7zSVQem5UfPsRQ9Ovsq16SQyyYEvixccuegppoCrG1nmvG9ew8ggpkCHik z+sWUKO3EZ9O2fJUelgqAh45qzJHgyW1OsfnS5gpctkBYkLfdL96MW9ow8ImCc4vrfCK oY1QVUh6EZMPWNcvNNQvbr+3oTadJEI4PMEMKIBJho6w7ZxqfmyFTEbQ3Ql1tzVMrJja ZRXjegMGC7OXESxoj9yP5MmqPKX/7ja/xiFriMQjouM+2sAJFfxjG30No6Zmvjv0qSpo xfySxMhW1eu3e0Dgu5TaeVVxhkLMXNlK8I+afSLH/n13HbOVFt1pxqKzWNonVdt0aOSA XdRw== X-Gm-Message-State: AC+VfDxtK65oLt1h5DfBa9Sjfshpz7Bi79tSwebfKABkkm2Q5jijXUaF KaW+8O5sdFCT/C6AzuM/ySw= X-Google-Smtp-Source: ACHHUZ5PDbzHHpaPuRf/VYBY2pI17Rv3g5jflGHbNwYkw1TG0thMQ1DzrhJJ2EK7x6zW5nw+iVRGHw== X-Received: by 2002:a7b:cd0d:0:b0:3f7:e497:aa03 with SMTP id f13-20020a7bcd0d000000b003f7e497aa03mr4213388wmj.28.1686472777346; Sun, 11 Jun 2023 01:39:37 -0700 (PDT) Received: from arinc9-Xeront.lan (178-147-169-233.haap.dm.cosmote.net. [178.147.169.233]) by smtp.gmail.com with ESMTPSA id 17-20020a05600c22d100b003f8044b3436sm7394629wmg.23.2023.06.11.01.39.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 01:39:37 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Landen Chao , Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net v3 6/7] net: dsa: introduce preferred_default_local_cpu_port and use on MT7530 Date: Sun, 11 Jun 2023 11:39:13 +0300 Message-Id: <20230611083914.28603-7-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230611083914.28603-1-arinc.unal@arinc9.com> References: <20230611083914.28603-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Vladimir Oltean Since the introduction of the OF bindings, DSA has always had a policy that in case multiple CPU ports are present in the device tree, the numerically smallest one is always chosen. The MT7530 switch family, except the switch on the MT7988 SoC, has 2 CPU ports, 5 and 6, where port 6 is preferable on the MT7531BE switch because it has higher bandwidth. The MT7530 driver developers had 3 options: - to modify DSA when the MT7531 switch support was introduced, such as to prefer the better port - to declare both CPU ports in device trees as CPU ports, and live with the sub-optimal performance resulting from not preferring the better port - to declare just port 6 in the device tree as a CPU port Of course they chose the path of least resistance (3rd option), kicking the can down the road. The hardware description in the device tree is supposed to be stable - developers are not supposed to adopt the strategy of piecemeal hardware description, where the device tree is updated in lockstep with the features that the kernel currently supports. Now, as a result of the fact that they did that, any attempts to modify the device tree and describe both CPU ports as CPU ports would make DSA change its default selection from port 6 to 5, effectively resulting in a performance degradation visible to users with the MT7531BE switch as can be seen below. Without preferring port 6: [ ID][Role] Interval Transfer Bitrate Retr [ 5][TX-C] 0.00-20.00 sec 374 MBytes 157 Mbits/sec 734 sender [ 5][TX-C] 0.00-20.00 sec 373 MBytes 156 Mbits/sec receiver [ 7][RX-C] 0.00-20.00 sec 1.81 GBytes 778 Mbits/sec 0 sender [ 7][RX-C] 0.00-20.00 sec 1.81 GBytes 777 Mbits/sec receiver With preferring port 6: [ ID][Role] Interval Transfer Bitrate Retr [ 5][TX-C] 0.00-20.00 sec 1.99 GBytes 856 Mbits/sec 273 sender [ 5][TX-C] 0.00-20.00 sec 1.99 GBytes 855 Mbits/sec receiver [ 7][RX-C] 0.00-20.00 sec 1.72 GBytes 737 Mbits/sec 15 sender [ 7][RX-C] 0.00-20.00 sec 1.71 GBytes 736 Mbits/sec receiver Using one port for WAN and the other ports for LAN is a very popular use case which is what this test emulates. As such, this change proposes that we retroactively modify stable kernels to keep the mt7530 driver preferring port 6 even with device trees where the hardware is more fully described. Fixes: c288575f7810 ("net: dsa: mt7530: Add the support of MT7531 switch") Signed-off-by: Vladimir Oltean Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 15 +++++++++++++++ include/net/dsa.h | 8 ++++++++ net/dsa/dsa.c | 24 +++++++++++++++++++++++- 3 files changed, 46 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 97f389f8d6ea..1ec047e552d2 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -399,6 +399,20 @@ static void mt7530_pll_setup(struct mt7530_priv *priv) core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); } =20 +/* If port 6 is available as a CPU port, always prefer that as the default, + * otherwise don't care. + */ +static struct dsa_port * +mt753x_preferred_default_local_cpu_port(struct dsa_switch *ds) +{ + struct dsa_port *cpu_dp =3D dsa_to_port(ds, 6); + + if (dsa_port_is_cpu(cpu_dp)) + return cpu_dp; + + return NULL; +} + /* Setup port 6 interface mode and TRGMII TX circuit */ static int mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) @@ -3122,6 +3136,7 @@ static int mt7988_setup(struct dsa_switch *ds) const struct dsa_switch_ops mt7530_switch_ops =3D { .get_tag_protocol =3D mtk_get_tag_protocol, .setup =3D mt753x_setup, + .preferred_default_local_cpu_port =3D mt753x_preferred_default_local_cpu_= port, .get_strings =3D mt7530_get_strings, .get_ethtool_stats =3D mt7530_get_ethtool_stats, .get_sset_count =3D mt7530_get_sset_count, diff --git a/include/net/dsa.h b/include/net/dsa.h index 8903053fa5aa..ab0f0a5b0860 100644 --- a/include/net/dsa.h +++ b/include/net/dsa.h @@ -958,6 +958,14 @@ struct dsa_switch_ops { struct phy_device *phy); void (*port_disable)(struct dsa_switch *ds, int port); =20 + /* + * Compatibility between device trees defining multiple CPU ports and + * drivers which are not OK to use by default the numerically smallest + * CPU port of a switch for its local ports. This can return NULL, + * meaning "don't know/don't care". + */ + struct dsa_port *(*preferred_default_local_cpu_port)(struct dsa_switch *d= s); + /* * Port's MAC EEE settings */ diff --git a/net/dsa/dsa.c b/net/dsa/dsa.c index ab1afe67fd18..1afed89e03c0 100644 --- a/net/dsa/dsa.c +++ b/net/dsa/dsa.c @@ -403,6 +403,24 @@ static int dsa_tree_setup_default_cpu(struct dsa_switc= h_tree *dst) return 0; } =20 +static struct dsa_port * +dsa_switch_preferred_default_local_cpu_port(struct dsa_switch *ds) +{ + struct dsa_port *cpu_dp; + + if (!ds->ops->preferred_default_local_cpu_port) + return NULL; + + cpu_dp =3D ds->ops->preferred_default_local_cpu_port(ds); + if (!cpu_dp) + return NULL; + + if (WARN_ON(!dsa_port_is_cpu(cpu_dp) || cpu_dp->ds !=3D ds)) + return NULL; + + return cpu_dp; +} + /* Perform initial assignment of CPU ports to user ports and DSA links in = the * fabric, giving preference to CPU ports local to each switch. Default to * using the first CPU port in the switch tree if the port does not have a= CPU @@ -410,12 +428,16 @@ static int dsa_tree_setup_default_cpu(struct dsa_swit= ch_tree *dst) */ static int dsa_tree_setup_cpu_ports(struct dsa_switch_tree *dst) { - struct dsa_port *cpu_dp, *dp; + struct dsa_port *preferred_cpu_dp, *cpu_dp, *dp; =20 list_for_each_entry(cpu_dp, &dst->ports, list) { if (!dsa_port_is_cpu(cpu_dp)) continue; =20 + preferred_cpu_dp =3D dsa_switch_preferred_default_local_cpu_port(cpu_dp-= >ds); + if (preferred_cpu_dp && preferred_cpu_dp !=3D cpu_dp) + continue; + /* Prefer a local CPU port */ dsa_switch_for_each_port(dp, cpu_dp->ds) { /* Prefer the first local CPU port found */ --=20 2.39.2 From nobody Fri Sep 20 16:40:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F862C7EE23 for ; Sun, 11 Jun 2023 08:40:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231552AbjFKIkD (ORCPT ); Sun, 11 Jun 2023 04:40:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233581AbjFKIjt (ORCPT ); Sun, 11 Jun 2023 04:39:49 -0400 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E337E3589; Sun, 11 Jun 2023 01:39:42 -0700 (PDT) Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-3f6d38a140bso23659895e9.1; Sun, 11 Jun 2023 01:39:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686472781; x=1689064781; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AIVXF0NWT+mxXgpNldoq9Ep8Ze5GWaI0IQCYTwDNGis=; b=fyj5u9TgodvwQiPlaW3l2gBOlGMjw4nB4gyrbVYsdzQuKc6KYDmX3RflBr27L3Mf/p 0l7NqqFFR/f6Y1znVmuMCzv332atRp7QEdAeP0jWlZNIVL2oK6w5QYRjyRE4s7Pxo3Qc IdOBKbwjtK/zI9+ecW+xixlC48lJBSXEvpgPwLDaYE4peCcAREuZv1tzr9vwPiEDEmZL g0wYFZwWp7AN3JclhU0F9/mEDe0s5kfJNsur+8KuPqh8YEQInF0H++V4pWKxDj7Xxv7U He6ga3IhvbLH1pFSFocLaq35lqSGTDuLpdVCA3hlBFEUjXBVs/q4fXLxWq214BjsDFYs Uw8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686472781; x=1689064781; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AIVXF0NWT+mxXgpNldoq9Ep8Ze5GWaI0IQCYTwDNGis=; b=OwSrdvC0JKtUCjRpfmbavDx579bxoCDfHlGXgutEGUUIinlLZFy289aYDwzAyIZEn+ gliCKEKShHV60/PxgmmZbphx+v41B/uGiSUbGMvriYhJM9QKwgQ7w931rQ2hVctyS90f 7mHSXBWmffOzVme8vkzjaLztpix5eTvY64NYpQhC1lJe4T8xK/vxLCCNq1RJF40MfKP9 mVIIX91wee12s7H8dR1WtgYNGls+ArZsX0LgXCq5/pTilv3IfFoeQe21Y5elT7CEESDv n4aqGbpRTDwUnFwABC+k48AVzh3C5TlvNsVJwI9iu5iY5vKgwL6TdSeyCJ5v2Kxq0J8s Ym7w== X-Gm-Message-State: AC+VfDzwShlt9M0h6A+PPjRd7EJrjHYug5bEIxwy6I9H+U8DzGueec/J Z/RnjLD6bBkD7bP+VN250lg= X-Google-Smtp-Source: ACHHUZ573Z43w980OoHuSFbgqdWgSkSlzAF1vEzQjNCHRAk6evwG2lmA/378fvU8tBQfx7HmyGZLKA== X-Received: by 2002:a1c:7204:0:b0:3f6:d90:3db with SMTP id n4-20020a1c7204000000b003f60d9003dbmr5029112wmc.3.1686472780674; Sun, 11 Jun 2023 01:39:40 -0700 (PDT) Received: from arinc9-Xeront.lan (178-147-169-233.haap.dm.cosmote.net. [178.147.169.233]) by smtp.gmail.com with ESMTPSA id 17-20020a05600c22d100b003f8044b3436sm7394629wmg.23.2023.06.11.01.39.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 01:39:40 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Landen Chao , Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net v3 7/7] MAINTAINERS: add me as maintainer of MEDIATEK SWITCH DRIVER Date: Sun, 11 Jun 2023 11:39:14 +0300 Message-Id: <20230611083914.28603-8-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230611083914.28603-1-arinc.unal@arinc9.com> References: <20230611083914.28603-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Add me as a maintainer of the MediaTek MT7530 DSA subdriver. List maintainers in alphabetical order by first name. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Vladimir Oltean --- MAINTAINERS | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index a73e5a98503a..c58d7fbb40ed 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13259,10 +13259,11 @@ F: drivers/memory/mtk-smi.c F: include/soc/mediatek/smi.h =20 MEDIATEK SWITCH DRIVER -M: Sean Wang +M: Ar=C4=B1n=C3=A7 =C3=9CNAL +M: Daniel Golle M: Landen Chao M: DENG Qingfang -M: Daniel Golle +M: Sean Wang L: netdev@vger.kernel.org S: Maintained F: drivers/net/dsa/mt7530-mdio.c --=20 2.39.2