From nobody Sun Feb 8 12:18:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02C0BC7EE25 for ; Fri, 9 Jun 2023 18:37:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231731AbjFIShQ (ORCPT ); Fri, 9 Jun 2023 14:37:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230422AbjFIShG (ORCPT ); Fri, 9 Jun 2023 14:37:06 -0400 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 750183A9A for ; Fri, 9 Jun 2023 11:37:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686335824; x=1717871824; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1UrDnJHGNX2U4JfQB881tpK0A4pQCMjacd032qm+qm8=; b=c8oN27BMU7y1VjQJHkbOD4ZZ3u2m6bKgKX6fOB1NO17v97IvZYnYG5ry 2mRDHRjVDPgRWiUf29bg54W9YsyNLyuEqBBldNiESTH7Vq5jBLh4Ndigw ex4qTHivHK91uGUOIGuhlfZ4V9PXQD4hSXnZ2b/T1nritXd5iCPaiFKNL M9ndFVopFKWWub5Qpu4r+MkVV3sBU4llYlE+Ru/5kZOty3mHKAmbWD8IG /4xBBiB250kzsk+4nql1IEfW8FH0O8+MpDG4Z3aBedXnMd7Q1PEmD0gke IVRU0iQs9eB51uAncPmYuK3mZBRTvfS0KCK9Z2fhHgTh0m9DvhcR6hUM1 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10736"; a="338022115" X-IronPort-AV: E=Sophos;i="6.00,230,1681196400"; d="scan'208";a="338022115" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jun 2023 11:37:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10736"; a="710443981" X-IronPort-AV: E=Sophos;i="6.00,230,1681196400"; d="scan'208";a="710443981" Received: from black.fi.intel.com (HELO black.fi.intel.com.) ([10.237.72.28]) by orsmga002.jf.intel.com with ESMTP; 09 Jun 2023 11:37:01 -0700 From: Alexander Shishkin To: linux-kernel@vger.kernel.org, x86@kernel.org, Andy Lutomirski , Dave Hansen , Ravi Shankar , Tony Luck , Sohil Mehta Cc: Alexander Shishkin Subject: [PATCH v3 04/12] x86/cpu: Enable LASS during CPU initialization Date: Fri, 9 Jun 2023 21:36:24 +0300 Message-Id: <20230609183632.48706-5-alexander.shishkin@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230609183632.48706-1-alexander.shishkin@linux.intel.com> References: <20230609183632.48706-1-alexander.shishkin@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Sohil Mehta Being a security feature, enable LASS by default if the platform supports it. Signed-off-by: Sohil Mehta Signed-off-by: Alexander Shishkin --- arch/x86/kernel/cpu/common.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 80710a68ef7d..315cc67ba93a 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -413,6 +413,12 @@ static __always_inline void setup_umip(struct cpuinfo_= x86 *c) cr4_clear_bits(X86_CR4_UMIP); } =20 +static __always_inline void setup_lass(struct cpuinfo_x86 *c) +{ + if (cpu_feature_enabled(X86_FEATURE_LASS)) + cr4_set_bits(X86_CR4_LASS); +} + /* These bits should not change their value after CPU init is finished. */ static const unsigned long cr4_pinned_mask =3D X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | @@ -1859,6 +1865,7 @@ static void identify_cpu(struct cpuinfo_x86 *c) setup_smep(c); setup_smap(c); setup_umip(c); + setup_lass(c); =20 /* Enable FSGSBASE instructions if available. */ if (cpu_has(c, X86_FEATURE_FSGSBASE)) { --=20 2.39.2