From nobody Fri Sep 20 16:25:49 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A80EBC7EE43 for ; Fri, 9 Jun 2023 07:30:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238775AbjFIH3w (ORCPT ); Fri, 9 Jun 2023 03:29:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43760 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238702AbjFIH3n (ORCPT ); Fri, 9 Jun 2023 03:29:43 -0400 Received: from mail-oa1-x2c.google.com (mail-oa1-x2c.google.com [IPv6:2001:4860:4864:20::2c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF0A130CB for ; Fri, 9 Jun 2023 00:29:14 -0700 (PDT) Received: by mail-oa1-x2c.google.com with SMTP id 586e51a60fabf-1a1fa977667so462833fac.1 for ; Fri, 09 Jun 2023 00:29:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1686295754; x=1688887754; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Fiqfy79Fm9eELrPZKhr0IzKYUTLKfOcN1zfjvWIor1U=; b=LxMNX7PgqJYg8YS2zT4J43YxXo9Sb8PLiIJ9k2lgNd1Xh5voESEHcivw8u8jtBBzP/ WiRjfyprxZi9kjfz9+meNBuo3OXBMaIc9u8YgtjYmT8e8l4RFqLi+LfeOuUoUm04yQKX bABGqbnX15cF3yKr5Ljr5dlBDIn9cA8v6Uc0Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686295754; x=1688887754; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Fiqfy79Fm9eELrPZKhr0IzKYUTLKfOcN1zfjvWIor1U=; b=ct77bIZh24UIyCYdRVHcZC9nvZxXJIWruBzEchQVE1jZRNytdVLVccPk+fK6FAziOk A215RhozpRcPZZKvWimqgZsCqppp9YWwBO9Utpa+zHHKL2Wbzz7h8wwFhfIhtSkXuSBT mblzj5HNWEqIgJiVwyW1jw4ztrjmnCcj5pIVx0FAHSJj7Bn6eoAy6xynNwkljTcHeZ7x waKQZGGL7DlLrL1HN98uGNLZqH4lUSad9CX/cj66msce8vuVg/XqB7Huyg3DV5a+28Ke yXUpmcB/4y0uCuc2dDBWNXq5B/mq7bV/BB/wSi1E1fRBM1bcG9M4LljPD6E2rcljSbRN lfnw== X-Gm-Message-State: AC+VfDyG+Zn6viI1x1rzIvRoOK3rPLrs6i7Ydo6ajHFvl2UKygdpbAep jmUJHPaDMrZoAySFufVCbImOxw== X-Google-Smtp-Source: ACHHUZ501Ve/MgepNvdJuxacEzoyyJ1OpWSjaxrZfy48TfjQ3Y9Q5kePfUaxCgQyognbCgNex8NP+g== X-Received: by 2002:a05:6870:3505:b0:1a3:5de8:e78b with SMTP id k5-20020a056870350500b001a35de8e78bmr576923oah.21.1686295754188; Fri, 09 Jun 2023 00:29:14 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:c2ea:d8e4:1fe8:21f0]) by smtp.gmail.com with ESMTPSA id y9-20020a655a09000000b005287a0560c9sm2160283pgs.1.2023.06.09.00.29.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jun 2023 00:29:13 -0700 (PDT) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno Cc: Chen-Yu Tsai , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH v2 1/4] arm64: dts: mediatek: mt8186: Add CCI node and CCI OPP table Date: Fri, 9 Jun 2023 15:29:02 +0800 Message-ID: <20230609072906.2784594-2-wenst@chromium.org> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230609072906.2784594-1-wenst@chromium.org> References: <20230609072906.2784594-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a device node for the CCI (cache coherent interconnect) and an OPP table for it. The OPP table was taken from the downstream ChromeOS kernel. Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- Angelo, I didn't pick up your Reviewed-by since I dropped the "opp-level" properties. arch/arm64/boot/dts/mediatek/mt8186.dtsi | 101 +++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index 8c02232cac38..93f3c45ba372 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -27,6 +27,99 @@ aliases { rdma1 =3D &rdma1; }; =20 + cci: cci { + compatible =3D "mediatek,mt8186-cci"; + clocks =3D <&mcusys CLK_MCU_ARMPLL_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names =3D "cci", "intermediate"; + operating-points-v2 =3D <&cci_opp>; + }; + + cci_opp: opp-table-cci { + compatible =3D "operating-points-v2"; + opp-shared; + + cci_opp_0: opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + opp-microvolt =3D <600000>; + }; + + cci_opp_1: opp-560000000 { + opp-hz =3D /bits/ 64 <560000000>; + opp-microvolt =3D <675000>; + }; + + cci_opp_2: opp-612000000 { + opp-hz =3D /bits/ 64 <612000000>; + opp-microvolt =3D <693750>; + }; + + cci_opp_3: opp-682000000 { + opp-hz =3D /bits/ 64 <682000000>; + opp-microvolt =3D <718750>; + }; + + cci_opp_4: opp-752000000 { + opp-hz =3D /bits/ 64 <752000000>; + opp-microvolt =3D <743750>; + }; + + cci_opp_5: opp-822000000 { + opp-hz =3D /bits/ 64 <822000000>; + opp-microvolt =3D <768750>; + }; + + cci_opp_6: opp-875000000 { + opp-hz =3D /bits/ 64 <875000000>; + opp-microvolt =3D <781250>; + }; + + cci_opp_7: opp-927000000 { + opp-hz =3D /bits/ 64 <927000000>; + opp-microvolt =3D <800000>; + }; + + cci_opp_8: opp-980000000 { + opp-hz =3D /bits/ 64 <980000000>; + opp-microvolt =3D <818750>; + }; + + cci_opp_9: opp-1050000000 { + opp-hz =3D /bits/ 64 <1050000000>; + opp-microvolt =3D <843750>; + }; + + cci_opp_10: opp-1120000000 { + opp-hz =3D /bits/ 64 <1120000000>; + opp-microvolt =3D <862500>; + }; + + cci_opp_11: opp-1155000000 { + opp-hz =3D /bits/ 64 <1155000000>; + opp-microvolt =3D <887500>; + }; + + cci_opp_12: opp-1190000000 { + opp-hz =3D /bits/ 64 <1190000000>; + opp-microvolt =3D <906250>; + }; + + cci_opp_13: opp-1260000000 { + opp-hz =3D /bits/ 64 <1260000000>; + opp-microvolt =3D <950000>; + }; + + cci_opp_14: opp-1330000000 { + opp-hz =3D /bits/ 64 <1330000000>; + opp-microvolt =3D <993750>; + }; + + cci_opp_15: opp-1400000000 { + opp-hz =3D /bits/ 64 <1400000000>; + opp-microvolt =3D <1031250>; + }; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; @@ -83,6 +176,7 @@ cpu0: cpu@0 { d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; + mediatek,cci =3D <&cci>; }; =20 cpu1: cpu@100 { @@ -101,6 +195,7 @@ cpu1: cpu@100 { d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; + mediatek,cci =3D <&cci>; }; =20 cpu2: cpu@200 { @@ -119,6 +214,7 @@ cpu2: cpu@200 { d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; + mediatek,cci =3D <&cci>; }; =20 cpu3: cpu@300 { @@ -137,6 +233,7 @@ cpu3: cpu@300 { d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; + mediatek,cci =3D <&cci>; }; =20 cpu4: cpu@400 { @@ -155,6 +252,7 @@ cpu4: cpu@400 { d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; + mediatek,cci =3D <&cci>; }; =20 cpu5: cpu@500 { @@ -173,6 +271,7 @@ cpu5: cpu@500 { d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; + mediatek,cci =3D <&cci>; }; =20 cpu6: cpu@600 { @@ -191,6 +290,7 @@ cpu6: cpu@600 { d-cache-sets =3D <256>; next-level-cache =3D <&l2_1>; #cooling-cells =3D <2>; + mediatek,cci =3D <&cci>; }; =20 cpu7: cpu@700 { @@ -209,6 +309,7 @@ cpu7: cpu@700 { d-cache-sets =3D <256>; next-level-cache =3D <&l2_1>; #cooling-cells =3D <2>; + mediatek,cci =3D <&cci>; }; =20 idle-states { --=20 2.41.0.162.gfafddb0af9-goog From nobody Fri Sep 20 16:25:49 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6279BC7EE43 for ; Fri, 9 Jun 2023 07:30:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238759AbjFIHaP (ORCPT ); Fri, 9 Jun 2023 03:30:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43794 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238725AbjFIH3r (ORCPT ); Fri, 9 Jun 2023 03:29:47 -0400 Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0607530D1 for ; Fri, 9 Jun 2023 00:29:17 -0700 (PDT) Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-6532671ccc7so1547663b3a.2 for ; Fri, 09 Jun 2023 00:29:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1686295756; x=1688887756; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rx3f6Wm6ps/QyxePUFE7///Bl8akU2heb6xMNcQDqwE=; b=bEq/XMCkpRcn/qpDfFh99z+5pRb2nFrmgJNn9F9kUDTtU2LQ+LI0J1qjgUqrk0rPLH hQJN3j22wDDSUacsyVcbG4WIDzsX2OBa4xXh5s4XaEw/xZZXlaPkWAhS1QA0kT0r9RW8 MO4zMD7Y9KIHa23yY+/LVswNrlCvxT/zeqIuU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686295756; x=1688887756; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rx3f6Wm6ps/QyxePUFE7///Bl8akU2heb6xMNcQDqwE=; b=FffDS4BjljDf6r3ngmS8FJlExb12lewl7dKH/QBC3pvxvnMcq8VxTYgadweHWtLD1E s+l725/VgtYhcDEZ0VRbciRVwLU4eE1jPRp7VR1YQY61pf1USRZ/Fi48aWT7u3ecVLav 1Y3n5djbmiKsk6YSCN8DM1Fc/S55S8BmoCjPhctH8Bj971QScuIGiYipvXV8jM+lM+ZO TpWIbD/KogfKLuXMS355j+OG+EOhmSJxfKDWnr+LhlCkxMDA+2yMRwzOoRgdZ44fEQoc GmJl/vy8Yyg/pdQxVkAhDJuO87xzjZVHJUMpXWv73lAmZXK6LPPB05Sjf1XwlLCyBiQD fSTA== X-Gm-Message-State: AC+VfDxobYWs0eIp3urx5riE4xfwQzTnmTA/hXVLmWAAajDuc3unGTnf PKavlVYSj3p4FMVCIlGdfGi7Uw== X-Google-Smtp-Source: ACHHUZ67VLM8QCCvc4MuoUmV8m4uEBjlB2CTj8FhPA+2uw2ZYkdy5bOOBxBQum193wvjJV0yMbHdzA== X-Received: by 2002:a05:6a00:1a10:b0:652:98e9:fb1 with SMTP id g16-20020a056a001a1000b0065298e90fb1mr571983pfv.32.1686295756257; Fri, 09 Jun 2023 00:29:16 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:c2ea:d8e4:1fe8:21f0]) by smtp.gmail.com with ESMTPSA id y9-20020a655a09000000b005287a0560c9sm2160283pgs.1.2023.06.09.00.29.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jun 2023 00:29:16 -0700 (PDT) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno Cc: Chen-Yu Tsai , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH v2 2/4] arm64: dts: mediatek: mt8186: Wire up CPU frequency/voltage scaling Date: Fri, 9 Jun 2023 15:29:03 +0800 Message-ID: <20230609072906.2784594-3-wenst@chromium.org> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230609072906.2784594-1-wenst@chromium.org> References: <20230609072906.2784594-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds clocks, dynamic power coefficients, and OPP tables for the CPU cores, so that everything required at the SoC level for CPU freqency and voltage scaling is available. Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 242 +++++++++++++++++++++++ 1 file changed, 242 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index 93f3c45ba372..e2becf2fe79f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -120,6 +120,208 @@ cci_opp_15: opp-1400000000 { }; }; =20 + cluster0_opp: opp-table-cluster0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + opp-microvolt =3D <600000>; + required-opps =3D <&cci_opp_0>; + }; + + opp-774000000 { + opp-hz =3D /bits/ 64 <774000000>; + opp-microvolt =3D <675000>; + required-opps =3D <&cci_opp_1>; + }; + + opp-875000000 { + opp-hz =3D /bits/ 64 <875000000>; + opp-microvolt =3D <700000>; + required-opps =3D <&cci_opp_2>; + }; + + opp-975000000 { + opp-hz =3D /bits/ 64 <975000000>; + opp-microvolt =3D <725000>; + required-opps =3D <&cci_opp_3>; + }; + + opp-1075000000 { + opp-hz =3D /bits/ 64 <1075000000>; + opp-microvolt =3D <750000>; + required-opps =3D <&cci_opp_4>; + }; + + opp-1175000000 { + opp-hz =3D /bits/ 64 <1175000000>; + opp-microvolt =3D <775000>; + required-opps =3D <&cci_opp_5>; + }; + + opp-1275000000 { + opp-hz =3D /bits/ 64 <1275000000>; + opp-microvolt =3D <800000>; + required-opps =3D <&cci_opp_6>; + }; + + opp-1375000000 { + opp-hz =3D /bits/ 64 <1375000000>; + opp-microvolt =3D <825000>; + required-opps =3D <&cci_opp_7>; + }; + + opp-1500000000 { + opp-hz =3D /bits/ 64 <1500000000>; + opp-microvolt =3D <856250>; + required-opps =3D <&cci_opp_8>; + }; + + opp-1618000000 { + opp-hz =3D /bits/ 64 <1618000000>; + opp-microvolt =3D <875000>; + required-opps =3D <&cci_opp_9>; + }; + + opp-1666000000 { + opp-hz =3D /bits/ 64 <1666000000>; + opp-microvolt =3D <900000>; + required-opps =3D <&cci_opp_10>; + }; + + opp-1733000000 { + opp-hz =3D /bits/ 64 <1733000000>; + opp-microvolt =3D <925000>; + required-opps =3D <&cci_opp_11>; + }; + + opp-1800000000 { + opp-hz =3D /bits/ 64 <1800000000>; + opp-microvolt =3D <950000>; + required-opps =3D <&cci_opp_12>; + }; + + opp-1866000000 { + opp-hz =3D /bits/ 64 <1866000000>; + opp-microvolt =3D <981250>; + required-opps =3D <&cci_opp_13>; + }; + + opp-1933000000 { + opp-hz =3D /bits/ 64 <1933000000>; + opp-microvolt =3D <1006250>; + required-opps =3D <&cci_opp_14>; + }; + + opp-2000000000 { + opp-hz =3D /bits/ 64 <2000000000>; + opp-microvolt =3D <1031250>; + required-opps =3D <&cci_opp_15>; + }; + }; + + cluster1_opp: opp-table-cluster1 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-774000000 { + opp-hz =3D /bits/ 64 <774000000>; + opp-microvolt =3D <675000>; + required-opps =3D <&cci_opp_0>; + }; + + opp-835000000 { + opp-hz =3D /bits/ 64 <835000000>; + opp-microvolt =3D <693750>; + required-opps =3D <&cci_opp_1>; + }; + + opp-919000000 { + opp-hz =3D /bits/ 64 <919000000>; + opp-microvolt =3D <718750>; + required-opps =3D <&cci_opp_2>; + }; + + opp-1002000000 { + opp-hz =3D /bits/ 64 <1002000000>; + opp-microvolt =3D <743750>; + required-opps =3D <&cci_opp_3>; + }; + + opp-1085000000 { + opp-hz =3D /bits/ 64 <1085000000>; + opp-microvolt =3D <775000>; + required-opps =3D <&cci_opp_4>; + }; + + opp-1169000000 { + opp-hz =3D /bits/ 64 <1169000000>; + opp-microvolt =3D <800000>; + required-opps =3D <&cci_opp_5>; + }; + + opp-1308000000 { + opp-hz =3D /bits/ 64 <1308000000>; + opp-microvolt =3D <843750>; + required-opps =3D <&cci_opp_6>; + }; + + opp-1419000000 { + opp-hz =3D /bits/ 64 <1419000000>; + opp-microvolt =3D <875000>; + required-opps =3D <&cci_opp_7>; + }; + + opp-1530000000 { + opp-hz =3D /bits/ 64 <1530000000>; + opp-microvolt =3D <912500>; + required-opps =3D <&cci_opp_8>; + }; + + opp-1670000000 { + opp-hz =3D /bits/ 64 <1670000000>; + opp-microvolt =3D <956250>; + required-opps =3D <&cci_opp_9>; + }; + + opp-1733000000 { + opp-hz =3D /bits/ 64 <1733000000>; + opp-microvolt =3D <981250>; + required-opps =3D <&cci_opp_10>; + }; + + opp-1796000000 { + opp-hz =3D /bits/ 64 <1796000000>; + opp-microvolt =3D <1012500>; + required-opps =3D <&cci_opp_11>; + }; + + opp-1860000000 { + opp-hz =3D /bits/ 64 <1860000000>; + opp-microvolt =3D <1037500>; + required-opps =3D <&cci_opp_12>; + }; + + opp-1923000000 { + opp-hz =3D /bits/ 64 <1923000000>; + opp-microvolt =3D <1062500>; + required-opps =3D <&cci_opp_13>; + }; + + cluster1_opp_14: opp-1986000000 { + opp-hz =3D /bits/ 64 <1986000000>; + opp-microvolt =3D <1093750>; + required-opps =3D <&cci_opp_14>; + }; + + cluster1_opp_15: opp-2050000000 { + opp-hz =3D /bits/ 64 <2050000000>; + opp-microvolt =3D <1118750>; + required-opps =3D <&cci_opp_15>; + }; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; @@ -166,6 +368,11 @@ cpu0: cpu@0 { reg =3D <0x000>; enable-method =3D "psci"; clock-frequency =3D <2000000000>; + clocks =3D <&mcusys CLK_MCU_ARMPLL_LL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names =3D "cpu", "intermediate"; + operating-points-v2 =3D <&cluster0_opp>; + dynamic-power-coefficient =3D <84>; capacity-dmips-mhz =3D <382>; cpu-idle-states =3D <&cpu_ret_l &cpu_off_l>; i-cache-size =3D <32768>; @@ -185,6 +392,11 @@ cpu1: cpu@100 { reg =3D <0x100>; enable-method =3D "psci"; clock-frequency =3D <2000000000>; + clocks =3D <&mcusys CLK_MCU_ARMPLL_LL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names =3D "cpu", "intermediate"; + operating-points-v2 =3D <&cluster0_opp>; + dynamic-power-coefficient =3D <84>; capacity-dmips-mhz =3D <382>; cpu-idle-states =3D <&cpu_ret_l &cpu_off_l>; i-cache-size =3D <32768>; @@ -204,6 +416,11 @@ cpu2: cpu@200 { reg =3D <0x200>; enable-method =3D "psci"; clock-frequency =3D <2000000000>; + clocks =3D <&mcusys CLK_MCU_ARMPLL_LL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names =3D "cpu", "intermediate"; + operating-points-v2 =3D <&cluster0_opp>; + dynamic-power-coefficient =3D <84>; capacity-dmips-mhz =3D <382>; cpu-idle-states =3D <&cpu_ret_l &cpu_off_l>; i-cache-size =3D <32768>; @@ -223,6 +440,11 @@ cpu3: cpu@300 { reg =3D <0x300>; enable-method =3D "psci"; clock-frequency =3D <2000000000>; + clocks =3D <&mcusys CLK_MCU_ARMPLL_LL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names =3D "cpu", "intermediate"; + operating-points-v2 =3D <&cluster0_opp>; + dynamic-power-coefficient =3D <84>; capacity-dmips-mhz =3D <382>; cpu-idle-states =3D <&cpu_ret_l &cpu_off_l>; i-cache-size =3D <32768>; @@ -242,6 +464,11 @@ cpu4: cpu@400 { reg =3D <0x400>; enable-method =3D "psci"; clock-frequency =3D <2000000000>; + clocks =3D <&mcusys CLK_MCU_ARMPLL_LL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names =3D "cpu", "intermediate"; + operating-points-v2 =3D <&cluster0_opp>; + dynamic-power-coefficient =3D <84>; capacity-dmips-mhz =3D <382>; cpu-idle-states =3D <&cpu_ret_l &cpu_off_l>; i-cache-size =3D <32768>; @@ -261,6 +488,11 @@ cpu5: cpu@500 { reg =3D <0x500>; enable-method =3D "psci"; clock-frequency =3D <2000000000>; + clocks =3D <&mcusys CLK_MCU_ARMPLL_LL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names =3D "cpu", "intermediate"; + operating-points-v2 =3D <&cluster0_opp>; + dynamic-power-coefficient =3D <84>; capacity-dmips-mhz =3D <382>; cpu-idle-states =3D <&cpu_ret_l &cpu_off_l>; i-cache-size =3D <32768>; @@ -280,6 +512,11 @@ cpu6: cpu@600 { reg =3D <0x600>; enable-method =3D "psci"; clock-frequency =3D <2050000000>; + clocks =3D <&mcusys CLK_MCU_ARMPLL_BL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names =3D "cpu", "intermediate"; + operating-points-v2 =3D <&cluster1_opp>; + dynamic-power-coefficient =3D <335>; capacity-dmips-mhz =3D <1024>; cpu-idle-states =3D <&cpu_ret_b &cpu_off_b>; i-cache-size =3D <65536>; @@ -299,6 +536,11 @@ cpu7: cpu@700 { reg =3D <0x700>; enable-method =3D "psci"; clock-frequency =3D <2050000000>; + clocks =3D <&mcusys CLK_MCU_ARMPLL_BL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names =3D "cpu", "intermediate"; + operating-points-v2 =3D <&cluster1_opp>; + dynamic-power-coefficient =3D <335>; capacity-dmips-mhz =3D <1024>; cpu-idle-states =3D <&cpu_ret_b &cpu_off_b>; i-cache-size =3D <65536>; --=20 2.41.0.162.gfafddb0af9-goog From nobody Fri Sep 20 16:25:49 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B1DCC7EE2E for ; Fri, 9 Jun 2023 07:30:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238845AbjFIHaV (ORCPT ); Fri, 9 Jun 2023 03:30:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238740AbjFIH3s (ORCPT ); Fri, 9 Jun 2023 03:29:48 -0400 Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C7D3130E7 for ; Fri, 9 Jun 2023 00:29:18 -0700 (PDT) Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-65055aa4ed7so1187065b3a.3 for ; Fri, 09 Jun 2023 00:29:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1686295758; x=1688887758; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JFvJp9MKPzIyi6S8BZNnG0J1ZKcj9eDruvsl3ndG+x4=; b=W3zHlgeCteyA5/h7T/zT/CEDMd7tW5H1gmub4yPa84VsY/FzktFNe2sABDAQkpwRh0 dCEdP3yZh7fS/tDIWFkE7o4AW0BOH42bT+87wVmCL/w3I5l+YCEFHsGT6xLrpxx9y5ER i36Xt6lDg1HlB7E1sBMMx5SDeC4cqleCVRlMM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686295758; x=1688887758; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JFvJp9MKPzIyi6S8BZNnG0J1ZKcj9eDruvsl3ndG+x4=; b=fEOIDTELZZlTkQrDjuQj7Eu67LlRuEq2DwOxDf3IW7L80D4E/SuWIH+QywJCyi1jBW j2MzAa82kmT+3R52AblonDWP+7inq24F615XLZDEEyOtt1wJODMC4exIgTPYfiFmYiJU g4ymyKH/bDGhhGHLTad89V3oe+U7eRmUoSaV5TcTVnXs27Fl3mU3Wq7Hze2tIWfnMwm3 zQQJz7BncHeqJl/XRgIr6jXlY1Jy/tGXCHpX/R4UbwTzHdbeQXBznEfN0EIUy4SC4LKF zomNRyj3r2oV8WA4KJE2qV+eQMcxlOnA4LoahJSlofvh18KU1W0uvixmSpU1i7585lZS xRCA== X-Gm-Message-State: AC+VfDz/TDuI/z351iwFP3UXvUyvF+bqNpk/xdS7BT3rXRvDmFSohbB6 WhIC1VJlEnZ6TDC3AH/y1dB7qg== X-Google-Smtp-Source: ACHHUZ4/R41ts0yq+D+izuk9QKrBsLXtoNV2EZbQA6MjNw8ibgUQYZmX3lZZXPG4B8U0fqhKZw9tvQ== X-Received: by 2002:a05:6a00:24d6:b0:646:59e4:94eb with SMTP id d22-20020a056a0024d600b0064659e494ebmr445628pfv.15.1686295758318; Fri, 09 Jun 2023 00:29:18 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:c2ea:d8e4:1fe8:21f0]) by smtp.gmail.com with ESMTPSA id y9-20020a655a09000000b005287a0560c9sm2160283pgs.1.2023.06.09.00.29.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jun 2023 00:29:18 -0700 (PDT) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno Cc: Chen-Yu Tsai , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH v2 3/4] arm64: dts: mediatek: mt8186: Add GPU speed bin NVMEM cells Date: Fri, 9 Jun 2023 15:29:04 +0800 Message-ID: <20230609072906.2784594-4-wenst@chromium.org> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230609072906.2784594-1-wenst@chromium.org> References: <20230609072906.2784594-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" On the MT8186, the chip is binned for different GPU voltages at the highest OPPs. The binning value is stored in the efuse. Add the NVMEM cell, and tie it to the GPU. Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index e2becf2fe79f..3762a70ccafb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -1519,6 +1519,11 @@ efuse: efuse@11cb0000 { reg =3D <0 0x11cb0000 0 0x1000>; #address-cells =3D <1>; #size-cells =3D <1>; + + gpu_speedbin: gpu-speed-bin@59c { + reg =3D <0x59c 0x4>; + bits =3D <0 3>; + }; }; =20 mipi_tx0: dsi-phy@11cc0000 { @@ -1551,6 +1556,8 @@ gpu: gpu@13040000 { <&spm MT8186_POWER_DOMAIN_MFG3>; power-domain-names =3D "core0", "core1"; #cooling-cells =3D <2>; + nvmem-cells =3D <&gpu_speedbin>; + nvmem-cell-names =3D "speed-bin"; status =3D "disabled"; }; =20 --=20 2.41.0.162.gfafddb0af9-goog From nobody Fri Sep 20 16:25:49 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E92C3C7EE2E for ; Fri, 9 Jun 2023 07:30:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238762AbjFIHaZ (ORCPT ); Fri, 9 Jun 2023 03:30:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43844 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238748AbjFIH3s (ORCPT ); Fri, 9 Jun 2023 03:29:48 -0400 Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E408D30E6 for ; Fri, 9 Jun 2023 00:29:20 -0700 (PDT) Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-651f2f38634so1494839b3a.0 for ; Fri, 09 Jun 2023 00:29:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1686295760; x=1688887760; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TD+KUgBGAZpos34KVNAuisH6maHzuZAbYL+cYk7AnpI=; b=W6ECPmFEywudFTGADngeW+8j6+RKfhMzOXW4JMxiaZhlyu+6dKLJveZYohzA7gk8N0 AkMgpbgmIfbZN1J9GhdzzkDX1+7MJh0oKuSRU+/09Ozmua9SOnTfqJSKU0rOAaTjLQRb 8ew0IxErShJiSYgM11P0AxrpUYhArPvNmzAN8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686295760; x=1688887760; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TD+KUgBGAZpos34KVNAuisH6maHzuZAbYL+cYk7AnpI=; b=GVWmyxTSsZZdMInV/2HpcMEjtyP57yWIIU9L7qtZhvkcARPnGjTBymMwidyHI5jNH6 mSV9FU+xJw6GUDFOJVgYBGssQHWd/DtYQ0Ow3N/ziJg0jjOt6YfD+rh2tRkPD/NmM9aV E8E0g14x/tKbHC4z204ohChTMRUs0De7upRwO9v1dx9DTXQI7FRnxExYz+y/S8yY8+YH W+naUQv1HjiZQygQpKt5Y7l4GqMeqCa2GcTC8ggi/K9EELdk4YWy8TQf2VrUjRQ3I/yI nQIK2s2k4DrMysU1+1692KwnAgpFx0X2yng5/ml2ANf++ETYBaMPD3scOK8ZfsfEDIXB FJlQ== X-Gm-Message-State: AC+VfDx3lj0ReMvFxkO9x6vtRpyhfFQVF6+5WaLZZwuhe4b7XcTxSUDk 4CfuCAV4I8F91h+xrD/sMwmCZQ== X-Google-Smtp-Source: ACHHUZ7CXCPz6Rn/bdtxmBFup4pQKAtT7ra/3D7+Bw2zj9cvrvb/EnPtR1cjdyv3l+/SW2uZbtn23g== X-Received: by 2002:aa7:8896:0:b0:658:f86f:b18e with SMTP id z22-20020aa78896000000b00658f86fb18emr643979pfe.22.1686295760403; Fri, 09 Jun 2023 00:29:20 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:c2ea:d8e4:1fe8:21f0]) by smtp.gmail.com with ESMTPSA id y9-20020a655a09000000b005287a0560c9sm2160283pgs.1.2023.06.09.00.29.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jun 2023 00:29:20 -0700 (PDT) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno Cc: Chen-Yu Tsai , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH v2 4/4] arm64: dts: mediatek: mt8186: Wire up GPU voltage/frequency scaling Date: Fri, 9 Jun 2023 15:29:05 +0800 Message-ID: <20230609072906.2784594-5-wenst@chromium.org> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230609072906.2784594-1-wenst@chromium.org> References: <20230609072906.2784594-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the GPU's OPP table. This is from the downstream ChromeOS kernel, adapted to the new upstream opp-supported-hw binning format. Also add dynamic-power-coefficient for the GPU. Also add label for mfg1 power domain. This is to be used at the board level to add a regulator supply for the power domain. Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 140 ++++++++++++++++++++++- 1 file changed, 139 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index 3762a70ccafb..f04ae70c470a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -647,6 +647,142 @@ clk32k: oscillator-32k { clock-output-names =3D "clk32k"; }; =20 + gpu_opp_table: opp-table-gpu { + compatible =3D "operating-points-v2"; + + opp-299000000 { + opp-hz =3D /bits/ 64 <299000000>; + opp-microvolt =3D <612500>; + opp-supported-hw =3D <0xff>; + }; + + opp-332000000 { + opp-hz =3D /bits/ 64 <332000000>; + opp-microvolt =3D <625000>; + opp-supported-hw =3D <0xff>; + }; + + opp-366000000 { + opp-hz =3D /bits/ 64 <366000000>; + opp-microvolt =3D <637500>; + opp-supported-hw =3D <0xff>; + }; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + opp-microvolt =3D <643750>; + opp-supported-hw =3D <0xff>; + }; + + opp-434000000 { + opp-hz =3D /bits/ 64 <434000000>; + opp-microvolt =3D <656250>; + opp-supported-hw =3D <0xff>; + }; + + opp-484000000 { + opp-hz =3D /bits/ 64 <484000000>; + opp-microvolt =3D <668750>; + opp-supported-hw =3D <0xff>; + }; + + opp-535000000 { + opp-hz =3D /bits/ 64 <535000000>; + opp-microvolt =3D <687500>; + opp-supported-hw =3D <0xff>; + }; + + opp-586000000 { + opp-hz =3D /bits/ 64 <586000000>; + opp-microvolt =3D <700000>; + opp-supported-hw =3D <0xff>; + }; + + opp-637000000 { + opp-hz =3D /bits/ 64 <637000000>; + opp-microvolt =3D <712500>; + opp-supported-hw =3D <0xff>; + }; + + opp-690000000 { + opp-hz =3D /bits/ 64 <690000000>; + opp-microvolt =3D <737500>; + opp-supported-hw =3D <0xff>; + }; + + opp-743000000 { + opp-hz =3D /bits/ 64 <743000000>; + opp-microvolt =3D <756250>; + opp-supported-hw =3D <0xff>; + }; + + opp-796000000 { + opp-hz =3D /bits/ 64 <796000000>; + opp-microvolt =3D <781250>; + opp-supported-hw =3D <0xff>; + }; + + opp-850000000 { + opp-hz =3D /bits/ 64 <850000000>; + opp-microvolt =3D <800000>; + opp-supported-hw =3D <0xff>; + }; + + opp-900000000-3 { + opp-hz =3D /bits/ 64 <900000000>; + opp-microvolt =3D <850000>; + opp-supported-hw =3D <0x8>; + }; + + opp-900000000-4 { + opp-hz =3D /bits/ 64 <900000000>; + opp-microvolt =3D <837500>; + opp-supported-hw =3D <0x10>; + }; + + opp-900000000-5 { + opp-hz =3D /bits/ 64 <900000000>; + opp-microvolt =3D <825000>; + opp-supported-hw =3D <0x30>; + }; + + opp-950000000-3 { + opp-hz =3D /bits/ 64 <950000000>; + opp-microvolt =3D <900000>; + opp-supported-hw =3D <0x8>; + }; + + opp-950000000-4 { + opp-hz =3D /bits/ 64 <950000000>; + opp-microvolt =3D <875000>; + opp-supported-hw =3D <0x10>; + }; + + opp-950000000-5 { + opp-hz =3D /bits/ 64 <950000000>; + opp-microvolt =3D <850000>; + opp-supported-hw =3D <0x30>; + }; + + opp-1000000000-3 { + opp-hz =3D /bits/ 64 <1000000000>; + opp-microvolt =3D <950000>; + opp-supported-hw =3D <0x8>; + }; + + opp-1000000000-4 { + opp-hz =3D /bits/ 64 <1000000000>; + opp-microvolt =3D <912500>; + opp-supported-hw =3D <0x10>; + }; + + opp-1000000000-5 { + opp-hz =3D /bits/ 64 <1000000000>; + opp-microvolt =3D <875000>; + opp-supported-hw =3D <0x30>; + }; + }; + pmu-a55 { compatible =3D "arm,cortex-a55-pmu"; interrupt-parent =3D <&gic>; @@ -765,7 +901,7 @@ mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 { #size-cells =3D <0>; #power-domain-cells =3D <1>; =20 - power-domain@MT8186_POWER_DOMAIN_MFG1 { + mfg1: power-domain@MT8186_POWER_DOMAIN_MFG1 { reg =3D ; mediatek,infracfg =3D <&infracfg_ao>; #address-cells =3D <1>; @@ -1558,6 +1694,8 @@ gpu: gpu@13040000 { #cooling-cells =3D <2>; nvmem-cells =3D <&gpu_speedbin>; nvmem-cell-names =3D "speed-bin"; + operating-points-v2 =3D <&gpu_opp_table>; + dynamic-power-coefficient =3D <4687>; status =3D "disabled"; }; =20 --=20 2.41.0.162.gfafddb0af9-goog