From nobody Mon Feb 9 01:11:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE410C87FDD for ; Thu, 8 Jun 2023 16:22:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234053AbjFHQWw (ORCPT ); Thu, 8 Jun 2023 12:22:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33018 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233578AbjFHQWp (ORCPT ); Thu, 8 Jun 2023 12:22:45 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8CFA12711; Thu, 8 Jun 2023 09:22:43 -0700 (PDT) Received: from jupiter.universe (dyndsl-091-248-189-092.ewe-ip-backbone.de [91.248.189.92]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id D6CEC6606F21; Thu, 8 Jun 2023 17:22:41 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1686241362; bh=FwPLJSnkJes7aEk1zAq6YjShJyVUZg9nQ3s3arUOpf0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XCM3/njX/QTdb8Ky5RrlS2NB0s/2mU4RP9KsQ64i4z8VGStaw6NtoWkl8EdqUGY0/ 8GTiH2MVJa8jifQeKCjf7c05zm98pre0S6JJOAmHiw2vBU019hEBm3AM5v3VevufDi 6nuU+kK91XQ8MJ8Mu8SywQ3NZysnDA/BpWJWXNxb/oe83vCb8Vx+xBXv1eFYHw8P/L 7fp/iHMC8sZgS4GtD2CovcA7jCo6RxuweGO1HlIjFtGZbUR/qoD91MBAryRya8pw+Z B+OVB/WzjSRR9zrO3efk2vpwcEXmq1zr4GOpP0/sDcjCjnxIWJOp2qOZB8aa90Orxa b0OJpb4OWE4Eg== Received: by jupiter.universe (Postfix, from userid 1000) id CA4164807E0; Thu, 8 Jun 2023 18:22:39 +0200 (CEST) From: Sebastian Reichel To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Damien Le Moal , Serge Semin , Vinod Koul , Kishon Vijay Abraham I , linux-ide@vger.kernel.org, linux-phy@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v3 1/5] dt-bindings: ata: dwc-ahci: add PHY clocks Date: Thu, 8 Jun 2023 18:22:34 +0200 Message-Id: <20230608162238.50078-2-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230608162238.50078-1-sebastian.reichel@collabora.com> References: <20230608162238.50078-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add PHY transmit and receive clocks as described by the DW SATA AHCI HW manual. Suggested-by: Serge Semin Signed-off-by: Sebastian Reichel Reviewed-by: Krzysztof Kozlowski Reviewed-by: Serge Semin --- .../devicetree/bindings/ata/snps,dwc-ahci-common.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yam= l b/Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml index c1457910520b..34c5bf65b02d 100644 --- a/Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml +++ b/Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml @@ -31,11 +31,11 @@ properties: PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/T= x) clock, etc. minItems: 1 - maxItems: 4 + maxItems: 6 =20 clock-names: minItems: 1 - maxItems: 4 + maxItems: 6 items: oneOf: - description: Application APB/AHB/AXI BIU clock @@ -48,6 +48,10 @@ properties: const: pmalive - description: RxOOB detection clock const: rxoob + - description: PHY Transmit Clock + const: asic + - description: PHY Receive Clock + const: rbc - description: SATA Ports reference clock const: ref =20 --=20 2.39.2 From nobody Mon Feb 9 01:11:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F70CC7EE45 for ; Thu, 8 Jun 2023 16:23:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234331AbjFHQW7 (ORCPT ); Thu, 8 Jun 2023 12:22:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33022 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233770AbjFHQWq (ORCPT ); Thu, 8 Jun 2023 12:22:46 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C207270F; Thu, 8 Jun 2023 09:22:43 -0700 (PDT) Received: from jupiter.universe (dyndsl-091-248-189-092.ewe-ip-backbone.de [91.248.189.92]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id E351A6606F23; Thu, 8 Jun 2023 17:22:41 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1686241362; bh=FonCoURcO7g6os0P5Lry6rxjs+kuIZse14bTr8E1Exk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=F5KlnpTuQFJ4my18FW/nI8RQGW0+E5iTneKQNFOHw2yiomPyhhch+cGXVduah2w1a vaeAa/eGnc3YPyU9rq/ZQClj2huNrYHURfv5U0QwCXH9YlfSridso03knEp6VaBMum eQ88TdD3kLsfwEGu0ex2CaH3t5ih6lnU31tWlgPD6KtGSDivxLGDjX/TdZwOw4JduM VlhgZ8fAyLvNpE145fOttcGApiOeWBec+ewjpE1E5iV49IoDx0SnAY87cbotYd7zVs ZcVeo8dnGntbn682aPm4fKiPvA0T6eosqF9S7+K6ezF8o7L/YdnxskDMJt3cB9/8HL 0FC70aBvf9HJQ== Received: by jupiter.universe (Postfix, from userid 1000) id CC1714807E1; Thu, 8 Jun 2023 18:22:39 +0200 (CEST) From: Sebastian Reichel To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Damien Le Moal , Serge Semin , Vinod Koul , Kishon Vijay Abraham I , linux-ide@vger.kernel.org, linux-phy@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v3 2/5] dt-bindings: ata: dwc-ahci: add Rockchip RK3588 Date: Thu, 8 Jun 2023 18:22:35 +0200 Message-Id: <20230608162238.50078-3-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230608162238.50078-1-sebastian.reichel@collabora.com> References: <20230608162238.50078-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds Rockchip RK3588 AHCI binding. In order to narrow down the allowed clocks without bloating the generic binding, the description of Rockchip's AHCI controllers has been moved to its own file. Signed-off-by: Sebastian Reichel --- .../bindings/ata/rockchip,dwc-ahci.yaml | 114 ++++++++++++++++++ .../bindings/ata/snps,dwc-ahci.yaml | 17 ++- 2 files changed, 125 insertions(+), 6 deletions(-) create mode 100644 Documentation/devicetree/bindings/ata/rockchip,dwc-ahci= .yaml diff --git a/Documentation/devicetree/bindings/ata/rockchip,dwc-ahci.yaml b= /Documentation/devicetree/bindings/ata/rockchip,dwc-ahci.yaml new file mode 100644 index 000000000000..86da9bd594a7 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/rockchip,dwc-ahci.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DWC AHCI SATA controller for Rockchip devices + +maintainers: + - Serge Semin + +description: + This document defines device tree bindings for the Synopsys DWC + implementation of the AHCI SATA controller found in Rockchip + devices. + +select: + properties: + compatible: + contains: + enum: + - rockchip,rk3568-dwc-ahci + - rockchip,rk3588-dwc-ahci + required: + - compatible + +properties: + compatible: + items: + - enum: + - rockchip,rk3568-dwc-ahci + - rockchip,rk3588-dwc-ahci + - const: snps,dwc-ahci + + ports-implemented: + const: 1 + +patternProperties: + "^sata-port@[0-9a-e]$": + $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port + + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - ports-implemented + +allOf: + - $ref: snps,dwc-ahci-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - rockchip,rk3588-dwc-ahci + then: + properties: + clock-names: + items: + - const: sata + - const: pmalive + - const: rxoob + - const: ref + - const: asic + - if: + properties: + compatible: + contains: + enum: + - rockchip,rk3568-dwc-ahci + then: + properties: + clock-names: + items: + - const: sata + - const: pmalive + - const: rxoob + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + sata@fe210000 { + compatible =3D "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg =3D <0xfe210000 0x1000>; + clocks =3D <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, + <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, + <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; + clock-names =3D "sata", "pmalive", "rxoob", "ref", "asic"; + interrupts =3D ; + ports-implemented =3D <0x1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + sata-port@0 { + reg =3D <0>; + hba-port-cap =3D ; + phys =3D <&combphy0_ps PHY_TYPE_SATA>; + phy-names =3D "sata-phy"; + snps,rx-ts-max =3D <32>; + snps,tx-ts-max =3D <32>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml b/Doc= umentation/devicetree/bindings/ata/snps,dwc-ahci.yaml index 5afa4b57ce20..55a4bdfa3d9a 100644 --- a/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml +++ b/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml @@ -13,8 +13,14 @@ description: This document defines device tree bindings for the generic Synopsys DWC implementation of the AHCI SATA controller. =20 -allOf: - - $ref: snps,dwc-ahci-common.yaml# +select: + properties: + compatible: + enum: + - snps,dwc-ahci + - snps,spear-ahci + required: + - compatible =20 properties: compatible: @@ -23,10 +29,6 @@ properties: const: snps,dwc-ahci - description: SPEAr1340 AHCI SATA device const: snps,spear-ahci - - description: Rockhip RK3568 AHCI controller - items: - - const: rockchip,rk3568-dwc-ahci - - const: snps,dwc-ahci =20 patternProperties: "^sata-port@[0-9a-e]$": @@ -39,6 +41,9 @@ required: - reg - interrupts =20 +allOf: + - $ref: snps,dwc-ahci-common.yaml# + unevaluatedProperties: false =20 examples: --=20 2.39.2 From nobody Mon Feb 9 01:11:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 894DBC7EE45 for ; Thu, 8 Jun 2023 16:22:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234105AbjFHQWz (ORCPT ); Thu, 8 Jun 2023 12:22:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33020 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232116AbjFHQWp (ORCPT ); Thu, 8 Jun 2023 12:22:45 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AAC552712; Thu, 8 Jun 2023 09:22:43 -0700 (PDT) Received: from jupiter.universe (dyndsl-091-248-189-092.ewe-ip-backbone.de [91.248.189.92]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id EB8676606F24; Thu, 8 Jun 2023 17:22:41 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1686241362; bh=d5W9cB5m/2xTUJ3EBNif6t03N/4rl9ZbDzQL72k7Itw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=V399m8BxIm0sskCAfXqxPOGJP/hCAWJRkGRMzdjWsXTs/b3sj1aS8itGiSFIvfkLC 01nY3deP4LQAK7XUvlnDjHIALP7YYcPQSlvVYaLSk4KaB5OaPJwwWnpgP7jXTS9ubD Qd6arz46D65sIhXjO5HQVzsJw1HO2xplt4NT7lhdVfSV/gpBs+JNY8stu5KBei0x1n qhXbfZyXiOzF2D8ko/RdXK0qxr0SaVc9IUHOAYuN93d1NGBtgubIcDpE2I6osRv/7/ Da8241ZE14m0dEbh0/2BDyzq9ymTTkGxFkJ4Ei1dcjuHQF8SQv55m0Z5b7M1JAhnoD ArC/q0LDeT2AA== Received: by jupiter.universe (Postfix, from userid 1000) id CDCFD4807E2; Thu, 8 Jun 2023 18:22:39 +0200 (CEST) From: Sebastian Reichel To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Damien Le Moal , Serge Semin , Vinod Koul , Kishon Vijay Abraham I , linux-ide@vger.kernel.org, linux-phy@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v3 3/5] dt-bindings: phy: rockchip: rk3588 has two reset lines Date: Thu, 8 Jun 2023 18:22:36 +0200 Message-Id: <20230608162238.50078-4-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230608162238.50078-1-sebastian.reichel@collabora.com> References: <20230608162238.50078-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The RK3588 has two reset lines for the combphy. One for the APB interface and one for the actual PHY. Signed-off-by: Sebastian Reichel Reviewed-by: Krzysztof Kozlowski --- .../phy/phy-rockchip-naneng-combphy.yaml | 34 ++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-comb= phy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combph= y.yaml index 9ae514fa7533..d3cd7997879f 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml @@ -31,8 +31,14 @@ properties: - const: pipe =20 resets: + minItems: 1 + maxItems: 2 + + reset-names: + minItems: 1 items: - - description: exclusive PHY reset line + - const: phy + - const: apb =20 rockchip,enable-ssc: type: boolean @@ -78,6 +84,32 @@ required: - rockchip,pipe-phy-grf - "#phy-cells" =20 +allOf: + - if: + properties: + compatible: + contains: + const: rockchip,rk3568-naneng-combphy + then: + properties: + resets: + maxItems: 1 + reset-names: + maxItems: 1 + - if: + properties: + compatible: + contains: + const: rockchip,rk3588-naneng-combphy + then: + properties: + resets: + minItems: 2 + reset-names: + minItems: 2 + required: + - reset-names + additionalProperties: false =20 examples: --=20 2.39.2 From nobody Mon Feb 9 01:11:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 208C3C7EE25 for ; Thu, 8 Jun 2023 16:23:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233256AbjFHQXC (ORCPT ); Thu, 8 Jun 2023 12:23:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233776AbjFHQWq (ORCPT ); Thu, 8 Jun 2023 12:22:46 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0124C2717; Thu, 8 Jun 2023 09:22:43 -0700 (PDT) Received: from jupiter.universe (dyndsl-091-248-189-092.ewe-ip-backbone.de [91.248.189.92]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id DC7BD6606F22; Thu, 8 Jun 2023 17:22:41 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1686241362; bh=51auYTRk2rmb/OCj/B4amurTw9Zrd8rSx4SmfWqBalc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GSy9NQNp4kLSJNJFtLoXi/8q2n8MWuFIN3uuUBBABGBOo4qia8lne4hr9cumhCyvD 5eP03Ut2IJNbtqNLJBoTcwDSFTLTcDBJrWp9nWPv91APoAint09BF0rahmTFg+r9Qn cZhnSu8CaMsrs3qeUejJbjEGq2ErE7GX61TPyXM5PpLJfjVLMEeOjGzzZCSP65hhRy 69Cx1stGNVtd0jJZfQIW7x70kCQaAnbpmImTZgT6O48IZ1NeWCp+urMfJBQgVKeXIf wMXjRr6Yce35za7whzxiLxn6/UWIPux+JZ+Hzqg5IpvRMjzRN8mfE+yC2U4YyIbEKV FJtmQU14BZXog== Received: by jupiter.universe (Postfix, from userid 1000) id CFAA04807EF; Thu, 8 Jun 2023 18:22:39 +0200 (CEST) From: Sebastian Reichel To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Damien Le Moal , Serge Semin , Vinod Koul , Kishon Vijay Abraham I , linux-ide@vger.kernel.org, linux-phy@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v3 4/5] arm64: dts: rockchip: rk3588: add combo PHYs Date: Thu, 8 Jun 2023 18:22:37 +0200 Message-Id: <20230608162238.50078-5-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230608162238.50078-1-sebastian.reichel@collabora.com> References: <20230608162238.50078-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add all 3 combo PHYs that can be found in RK3588. They are used for SATA, PCIe or USB3. Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 21 ++++++++++++ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 42 +++++++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts= /rockchip/rk3588.dtsi index 8be75556af8f..9d8539b5309b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -7,6 +7,11 @@ #include "rk3588-pinctrl.dtsi" =20 / { + pipe_phy1_grf: syscon@fd5c0000 { + compatible =3D "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg =3D <0x0 0xfd5c0000 0x0 0x100>; + }; + i2s8_8ch: i2s@fddc8000 { compatible =3D "rockchip,rk3588-i2s-tdm"; reg =3D <0x0 0xfddc8000 0x0 0x1000>; @@ -123,4 +128,20 @@ gmac0_mtl_tx_setup: tx-queues-config { queue1 {}; }; }; + + combphy1_ps: phy@fee10000 { + compatible =3D "rockchip,rk3588-naneng-combphy"; + reg =3D <0x0 0xfee10000 0x0 0x100>; + #phy-cells =3D <1>; + clocks =3D <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, + <&cru PCLK_PHP_ROOT>; + clock-names =3D "ref", "apb", "pipe"; + assigned-clocks =3D <&cru CLK_REF_PIPE_PHY1>; + assigned-clock-rates =3D <100000000>; + resets =3D <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; + reset-names =3D "phy", "apb"; + rockchip,pipe-grf =3D <&php_grf>; + rockchip,pipe-phy-grf =3D <&pipe_phy1_grf>; + status =3D "disabled"; + }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dt= s/rockchip/rk3588s.dtsi index 01058fed8f96..45ae457a22a4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -944,6 +944,16 @@ php_grf: syscon@fd5b0000 { reg =3D <0x0 0xfd5b0000 0x0 0x1000>; }; =20 + pipe_phy0_grf: syscon@fd5bc000 { + compatible =3D "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg =3D <0x0 0xfd5bc000 0x0 0x100>; + }; + + pipe_phy2_grf: syscon@fd5c4000 { + compatible =3D "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg =3D <0x0 0xfd5c4000 0x0 0x100>; + }; + ioc: syscon@fd5f0000 { compatible =3D "rockchip,rk3588-ioc", "syscon"; reg =3D <0x0 0xfd5f0000 0x0 0x10000>; @@ -2371,6 +2381,38 @@ dmac2: dma-controller@fed10000 { #dma-cells =3D <1>; }; =20 + combphy0_ps: phy@fee00000 { + compatible =3D "rockchip,rk3588-naneng-combphy"; + reg =3D <0x0 0xfee00000 0x0 0x100>; + #phy-cells =3D <1>; + clocks =3D <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, + <&cru PCLK_PHP_ROOT>; + clock-names =3D "ref", "apb", "pipe"; + assigned-clocks =3D <&cru CLK_REF_PIPE_PHY0>; + assigned-clock-rates =3D <100000000>; + resets =3D <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; + reset-names =3D "phy", "apb"; + rockchip,pipe-grf =3D <&php_grf>; + rockchip,pipe-phy-grf =3D <&pipe_phy0_grf>; + status =3D "disabled"; + }; + + combphy2_psu: phy@fee20000 { + compatible =3D "rockchip,rk3588-naneng-combphy"; + reg =3D <0x0 0xfee20000 0x0 0x100>; + #phy-cells =3D <1>; + clocks =3D <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, + <&cru PCLK_PHP_ROOT>; + clock-names =3D "ref", "apb", "pipe"; + assigned-clocks =3D <&cru CLK_REF_PIPE_PHY2>; + assigned-clock-rates =3D <100000000>; + resets =3D <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; + reset-names =3D "phy", "apb"; + rockchip,pipe-grf =3D <&php_grf>; + rockchip,pipe-phy-grf =3D <&pipe_phy2_grf>; + status =3D "disabled"; + }; + system_sram2: sram@ff001000 { compatible =3D "mmio-sram"; reg =3D <0x0 0xff001000 0x0 0xef000>; --=20 2.39.2 From nobody Mon Feb 9 01:11:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F2C9C7EE29 for ; Thu, 8 Jun 2023 16:23:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234429AbjFHQXF (ORCPT ); Thu, 8 Jun 2023 12:23:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33034 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229544AbjFHQWr (ORCPT ); Thu, 8 Jun 2023 12:22:47 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2DF4D1FDC; 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Thu, 8 Jun 2023 18:22:39 +0200 (CEST) From: Sebastian Reichel To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Damien Le Moal , Serge Semin , Vinod Koul , Kishon Vijay Abraham I , linux-ide@vger.kernel.org, linux-phy@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v3 5/5] arm64: dts: rockchip: rk3588: add SATA support Date: Thu, 8 Jun 2023 18:22:38 +0200 Message-Id: <20230608162238.50078-6-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230608162238.50078-1-sebastian.reichel@collabora.com> References: <20230608162238.50078-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add all three SATA IP blocks to the RK3588 DT. Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 23 +++++++++++ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 48 +++++++++++++++++++++++ 2 files changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts= /rockchip/rk3588.dtsi index 9d8539b5309b..b9508cea34f1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -129,6 +129,29 @@ gmac0_mtl_tx_setup: tx-queues-config { }; }; =20 + sata1: sata@fe220000 { + compatible =3D "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg =3D <0 0xfe220000 0 0x1000>; + clocks =3D <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, + <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, + <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; + clock-names =3D "sata", "pmalive", "rxoob", "ref", "asic"; + interrupts =3D ; + ports-implemented =3D <0x1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + + sata-port@0 { + reg =3D <0>; + hba-port-cap =3D ; + phys =3D <&combphy1_ps PHY_TYPE_SATA>; + phy-names =3D "sata-phy"; + snps,rx-ts-max =3D <32>; + snps,tx-ts-max =3D <32>; + }; + }; + combphy1_ps: phy@fee10000 { compatible =3D "rockchip,rk3588-naneng-combphy"; reg =3D <0x0 0xfee10000 0x0 0x100>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dt= s/rockchip/rk3588s.dtsi index 45ae457a22a4..00a91b08e3bb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -9,6 +9,8 @@ #include #include #include +#include +#include =20 / { compatible =3D "rockchip,rk3588"; @@ -1717,6 +1719,52 @@ gmac1_mtl_tx_setup: tx-queues-config { }; }; =20 + sata0: sata@fe210000 { + compatible =3D "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg =3D <0 0xfe210000 0 0x1000>; + clocks =3D <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, + <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, + <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; + clock-names =3D "sata", "pmalive", "rxoob", "ref", "asic"; + interrupts =3D ; + ports-implemented =3D <0x1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + + sata-port@0 { + reg =3D <0>; + hba-port-cap =3D ; + phys =3D <&combphy0_ps PHY_TYPE_SATA>; + phy-names =3D "sata-phy"; + snps,rx-ts-max =3D <32>; + snps,tx-ts-max =3D <32>; + }; + }; + + sata2: sata@fe230000 { + compatible =3D "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg =3D <0 0xfe230000 0 0x1000>; + clocks =3D <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, + <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, + <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; + clock-names =3D "sata", "pmalive", "rxoob", "ref", "asic"; + interrupts =3D ; + ports-implemented =3D <0x1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + + sata-port@0 { + reg =3D <0>; + hba-port-cap =3D ; + phys =3D <&combphy2_psu PHY_TYPE_SATA>; + phy-names =3D "sata-phy"; + snps,rx-ts-max =3D <32>; + snps,tx-ts-max =3D <32>; + }; + }; + sdmmc: mmc@fe2c0000 { compatible =3D "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; reg =3D <0x0 0xfe2c0000 0x0 0x4000>; --=20 2.39.2