From nobody Tue Feb 10 17:08:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10ED6C7EE23 for ; Thu, 8 Jun 2023 10:51:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236178AbjFHKvC (ORCPT ); Thu, 8 Jun 2023 06:51:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235157AbjFHKum (ORCPT ); Thu, 8 Jun 2023 06:50:42 -0400 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E770E2D69; Thu, 8 Jun 2023 03:50:36 -0700 (PDT) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35887B8X023585; Thu, 8 Jun 2023 03:50:30 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=3yaqcdBg41d7mhWAoxcGyVDU3b5DBL/sd2gMwajYnRY=; b=KIXCVREOZ/ZZ/GFs7DJsZquDuxUby+JLkS67P82Vj7oZEn+ZdHbWLSenFogiBfIv69xA aV6ahY3h6nsZNHClsSXPgEnQkVPweiWFrok+XQIJ/1cBRJF8VocpAHmRU2PUYtJbCSLU RmBtY4ZJwGk9g44vVIE7b4toVM5erKM/UifzgVr8MvTMFC2Id8Up+A2vwvmuMxfrxXQH pO7zkRitrYzwBvESOvPo9nTVzLyBCj6W9dxqN11iYPh9sVFg1JVacLb6++ny7e83H+wR 03nz4TTrXO3oHhE0QlzroZumKOkc2Eio1wEkiwtkoCWWd7nfJKZteM5cn5ihmVPiChdY 5A== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3r329c2c3c-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 08 Jun 2023 03:50:30 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 8 Jun 2023 03:50:28 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 8 Jun 2023 03:50:28 -0700 Received: from #hyd1583.marvell.com (unknown [10.29.37.44]) by maili.marvell.com (Postfix) with ESMTP id 90D623F707F; Thu, 8 Jun 2023 03:50:25 -0700 (PDT) From: Naveen Mamindlapalli To: , , , , , , CC: Nithin Dabilpuram , Jerin Jacob Kollanukkaran , Naveen Mamindlapalli Subject: [net-next PATCH 5/6] octeontx2-af: add option to toggle DROP_RE enable in rx cfg Date: Thu, 8 Jun 2023 16:20:06 +0530 Message-ID: <20230608105007.26924-6-naveenm@marvell.com> X-Mailer: git-send-email 2.39.0.198.ga38d39a4c5 In-Reply-To: <20230608105007.26924-1-naveenm@marvell.com> References: <20230608105007.26924-1-naveenm@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: 6QVY8VUU-nGZ68CMqLXeJgI5jlPPdlD4 X-Proofpoint-ORIG-GUID: 6QVY8VUU-nGZ68CMqLXeJgI5jlPPdlD4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-08_07,2023-06-08_01,2023-05-22_02 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Nithin Dabilpuram Add option to toggle DROP_RE bit in rx cfg mbox. This helps in modifying the config runtime as opposed to setting available via nix_lf_alloc() mbox at NIX LF init time. Signed-off-by: Nithin Dabilpuram Signed-off-by: Jerin Jacob Kollanukkaran Signed-off-by: Sunil Kovvuri Goutham Signed-off-by: Naveen Mamindlapalli --- drivers/net/ethernet/marvell/octeontx2/af/mbox.h | 1 + drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net= /ethernet/marvell/octeontx2/af/mbox.h index f233f98cbeea..3f30db28eff1 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -1151,6 +1151,7 @@ struct nix_rx_cfg { struct mbox_msghdr hdr; #define NIX_RX_OL3_VERIFY BIT(0) #define NIX_RX_OL4_VERIFY BIT(1) +#define NIX_RX_DROP_RE BIT(2) u8 len_verify; /* Outer L3/L4 len check */ #define NIX_RX_CSUM_OL4_VERIFY BIT(0) u8 csum_verify; /* Outer L4 checksum verification */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_nix.c index 842ee9909af4..18a146e9c4ef 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c @@ -4130,6 +4130,11 @@ int rvu_mbox_handler_nix_set_rx_cfg(struct rvu *rvu,= struct nix_rx_cfg *req, else cfg &=3D ~BIT_ULL(40); =20 + if (req->len_verify & NIX_RX_DROP_RE) + cfg |=3D BIT_ULL(32); + else + cfg &=3D ~BIT_ULL(32); + if (req->csum_verify & BIT(0)) cfg |=3D BIT_ULL(37); else --=20 2.39.0.198.ga38d39a4c5