From nobody Mon Feb 9 09:42:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ACB67C7EE23 for ; Thu, 8 Jun 2023 14:06:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236735AbjFHOG2 (ORCPT ); Thu, 8 Jun 2023 10:06:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44452 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235944AbjFHOG0 (ORCPT ); Thu, 8 Jun 2023 10:06:26 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7CDF52722 for ; Thu, 8 Jun 2023 07:06:25 -0700 (PDT) Received: from dude05.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::54]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1q7GHK-0007QF-H0; Thu, 08 Jun 2023 16:06:18 +0200 From: Philipp Zabel Date: Thu, 08 Jun 2023 16:06:02 +0200 Subject: [PATCH] pwm: stm32: Implement .get_state() MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230608-pwm-stm32-get-state-v1-1-db7e58a7461b@pengutronix.de> X-B4-Tracking: v=1; b=H4sIAErggWQC/x2N0QqDMAxFf0XyvECtQ2W/MvaQtpkGtJOmbgPx3 xf2ds+FwzlAuQgr3JoDCr9F5ZUN2ksDcaY8MUoyBu9853o34vZZUevaeZy42qLKeG3dECKlNIw9 mBlIGUOhHGdz874sdm6Fn/L9p+6P8/wBf0QZ1HoAAAA= To: Fabrice Gasnier , Thierry Reding , Uwe =?utf-8?q?Kleine-K=C3=B6nig?= , Maxime Coquelin , Alexandre Torgue Cc: linux-pwm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Philipp Zabel X-Mailer: b4 0.12-dev-aab37 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::54 X-SA-Exim-Mail-From: p.zabel@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Stop stm32_pwm_detect_channels() from disabling all channels and count the number of enabled PWMs to keep the clock running. Implement the &pwm_ops->get_state callback so drivers can inherit PWM state set by the bootloader. Signed-off-by: Philipp Zabel Reviewed-by: Fabrice Gasnier --- Make the necessary changes to allow inheriting PWM state set by the bootloader, for example to avoid flickering with a pre-enabled PWM backlight. --- drivers/pwm/pwm-stm32.c | 75 ++++++++++++++++++++++++++++++++++++++-------= ---- 1 file changed, 59 insertions(+), 16 deletions(-) diff --git a/drivers/pwm/pwm-stm32.c b/drivers/pwm/pwm-stm32.c index 62e397aeb9aa..e0677c954bdf 100644 --- a/drivers/pwm/pwm-stm32.c +++ b/drivers/pwm/pwm-stm32.c @@ -52,6 +52,21 @@ static u32 active_channels(struct stm32_pwm *dev) return ccer & TIM_CCER_CCXE; } =20 +static int read_ccrx(struct stm32_pwm *dev, int ch, u32 *value) +{ + switch (ch) { + case 0: + return regmap_read(dev->regmap, TIM_CCR1, value); + case 1: + return regmap_read(dev->regmap, TIM_CCR2, value); + case 2: + return regmap_read(dev->regmap, TIM_CCR3, value); + case 3: + return regmap_read(dev->regmap, TIM_CCR4, value); + } + return -EINVAL; +} + static int write_ccrx(struct stm32_pwm *dev, int ch, u32 value) { switch (ch) { @@ -486,9 +501,40 @@ static int stm32_pwm_apply_locked(struct pwm_chip *chi= p, struct pwm_device *pwm, return ret; } =20 +static int stm32_pwm_get_state(struct pwm_chip *chip, + struct pwm_device *pwm, struct pwm_state *state) +{ + struct stm32_pwm *priv =3D to_stm32_pwm_dev(chip); + int ch =3D pwm->hwpwm; + unsigned long rate; + u32 ccer, psc, arr, ccr; + u64 dty, prd; + int ret; + + ret =3D regmap_read(priv->regmap, TIM_CCER, &ccer); + if (ret) + return ret; + + state->enabled =3D ccer & (TIM_CCER_CC1E << (ch * 4)); + state->polarity =3D (ccer & (TIM_CCER_CC1P << (ch * 4))) ? + PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL; + regmap_read(priv->regmap, TIM_PSC, &psc); + regmap_read(priv->regmap, TIM_ARR, &arr); + read_ccrx(priv, ch, &ccr); + rate =3D clk_get_rate(priv->clk); + + prd =3D (u64)NSEC_PER_SEC * (psc + 1) * (arr + 1); + state->period =3D DIV_ROUND_UP_ULL(prd, rate); + dty =3D (u64)NSEC_PER_SEC * (psc + 1) * ccr; + state->duty_cycle =3D DIV_ROUND_UP_ULL(dty, rate); + + return ret; +} + static const struct pwm_ops stm32pwm_ops =3D { .owner =3D THIS_MODULE, .apply =3D stm32_pwm_apply_locked, + .get_state =3D stm32_pwm_get_state, .capture =3D IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL, }; =20 @@ -579,30 +625,22 @@ static void stm32_pwm_detect_complementary(struct stm= 32_pwm *priv) priv->have_complementary_output =3D (ccer !=3D 0); } =20 -static int stm32_pwm_detect_channels(struct stm32_pwm *priv) +static int stm32_pwm_detect_channels(struct stm32_pwm *priv, int *n_enable= d) { - u32 ccer; - int npwm =3D 0; + u32 ccer, ccer_backup; + int npwm; =20 /* * If channels enable bits don't exist writing 1 will have no * effect so we can detect and count them. */ + regmap_read(priv->regmap, TIM_CCER, &ccer_backup); regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE); regmap_read(priv->regmap, TIM_CCER, &ccer); - regmap_clear_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE); + regmap_write(priv->regmap, TIM_CCER, ccer_backup); =20 - if (ccer & TIM_CCER_CC1E) - npwm++; - - if (ccer & TIM_CCER_CC2E) - npwm++; - - if (ccer & TIM_CCER_CC3E) - npwm++; - - if (ccer & TIM_CCER_CC4E) - npwm++; + npwm =3D hweight32(ccer & TIM_CCER_CCXE); + *n_enabled =3D hweight32(ccer_backup & TIM_CCER_CCXE); =20 return npwm; } @@ -613,7 +651,9 @@ static int stm32_pwm_probe(struct platform_device *pdev) struct device_node *np =3D dev->of_node; struct stm32_timers *ddata =3D dev_get_drvdata(pdev->dev.parent); struct stm32_pwm *priv; + int n_enabled; int ret; + int i; =20 priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -635,7 +675,10 @@ static int stm32_pwm_probe(struct platform_device *pde= v) =20 priv->chip.dev =3D dev; priv->chip.ops =3D &stm32pwm_ops; - priv->chip.npwm =3D stm32_pwm_detect_channels(priv); + priv->chip.npwm =3D stm32_pwm_detect_channels(priv, &n_enabled); + + for (i =3D 0; i < n_enabled; i++) + clk_enable(priv->clk); =20 ret =3D pwmchip_add(&priv->chip); if (ret < 0) --- base-commit: ac9a78681b921877518763ba0e89202254349d1b change-id: 20230608-pwm-stm32-get-state-4107bcadd786 Best regards, --=20 Philipp Zabel