From nobody Fri Sep 20 20:29:49 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9E05C7EE43 for ; Wed, 7 Jun 2023 20:58:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235734AbjFGU6O (ORCPT ); Wed, 7 Jun 2023 16:58:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235671AbjFGU55 (ORCPT ); Wed, 7 Jun 2023 16:57:57 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FCE42693; Wed, 7 Jun 2023 13:57:43 -0700 (PDT) Received: from notapiano.myfiosgateway.com (zone.collabora.co.uk [167.235.23.81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 5C96A6606F00; Wed, 7 Jun 2023 21:57:40 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1686171462; bh=SX2kQXHH/m6V86MJ8NInkW8P4EQpUbbxEWsbsnTyfNw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VDgVaqU8ozr8487B8htKhaUh22RVmJT0IFTvQrjhRKNxbOWwZ1oM7q/pYHh+RLWPX eSF4Est21YuR+58D0gs+V5g9QtczhK0jSS4KrpdqhyVXDmQpGGxZY279D8wI1EEaIv TCYwOBiACJpEeJfdsVzuQ2ge03dip5+Wk2h6n39CN5IophZ9aQCvZ0mLQgBi5QzxVo 3JDCOHg6+b6y5B/Dzf7aPJEPqGVs+iPSpps2LmbM3LKeKbqVRETp+VCOTjwr0OlIbJ 9L6tZGNXDoEXMCw4orP36s5xjYuLtSXUKo1pxjTbp+x1b71lXKV6P6F0PLhT8HJu0k PLo/Br1QzZAkg== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger , Hans Verkuil Cc: kernel@collabora.com, AngeloGioacchino Del Regno , Yunfei Dong , =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 5/5] arm64: dts: mediatek: mt8183: Add decoder Date: Wed, 7 Jun 2023 16:53:42 -0400 Message-ID: <20230607205714.510012-6-nfraprado@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230607205714.510012-1-nfraprado@collabora.com> References: <20230607205714.510012-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Yunfei Dong Add node for the hardware decoder present on the MT8183 SoC. Signed-off-by: Yunfei Dong Signed-off-by: Qianqian Yan Signed-off-by: Frederic Chen Signed-off-by: Alexandre Courbot Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- Changes in v2: - Reformatted reg-names to fit in fewer lines arch/arm64/boot/dts/mediatek/mt8183.dtsi | 30 ++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts= /mediatek/mt8183.dtsi index 5169779d01df..28ad6c480430 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -2019,6 +2019,36 @@ vdecsys: syscon@16000000 { #clock-cells =3D <1>; }; =20 + vcodec_dec: video-codec@16020000 { + compatible =3D "mediatek,mt8183-vcodec-dec"; + reg =3D <0 0x16020000 0 0x1000>, /* VDEC_MISC */ + <0 0x16021000 0 0x800>, /* VDEC_VLD */ + <0 0x16021800 0 0x800>, /* VDEC_TOP */ + <0 0x16022000 0 0x1000>, /* VDEC_MC */ + <0 0x16023000 0 0x1000>, /* VDEC_AVCVLD */ + <0 0x16024000 0 0x1000>, /* VDEC_AVCMV */ + <0 0x16025000 0 0x1000>, /* VDEC_PP */ + <0 0x16026800 0 0x800>, /* VP8_VD */ + <0 0x16027000 0 0x800>, /* VP6_VD */ + <0 0x16027800 0 0x800>, /* VP8_VL */ + <0 0x16028400 0 0x400>; /* VP9_VD */ + reg-names =3D "misc", "ld", "top", "cm", "ad", "av", "pp", + "hwd", "hwq", "hwb", "hwg"; + interrupts =3D ; + iommus =3D <&iommu M4U_PORT_HW_VDEC_MC_EXT>, + <&iommu M4U_PORT_HW_VDEC_PP_EXT>, + <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, + <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, + <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, + <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, + <&iommu M4U_PORT_HW_VDEC_PPWRAP_EXT>; + mediatek,scp =3D <&scp>; + power-domains =3D <&spm MT8183_POWER_DOMAIN_VDEC>; + clocks =3D <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_ACTIVE>; + clock-names =3D "vdec", "active"; + }; + larb1: larb@16010000 { compatible =3D "mediatek,mt8183-smi-larb"; reg =3D <0 0x16010000 0 0x1000>; --=20 2.41.0