From nobody Fri Sep 20 20:37:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7466C7EE2E for ; Wed, 7 Jun 2023 09:08:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239811AbjFGJIQ (ORCPT ); Wed, 7 Jun 2023 05:08:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239795AbjFGJHl (ORCPT ); Wed, 7 Jun 2023 05:07:41 -0400 Received: from mail-oa1-x31.google.com (mail-oa1-x31.google.com [IPv6:2001:4860:4864:20::31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4468426B1 for ; Wed, 7 Jun 2023 02:07:03 -0700 (PDT) Received: by mail-oa1-x31.google.com with SMTP id 586e51a60fabf-1a27ffe9dcdso6801206fac.2 for ; Wed, 07 Jun 2023 02:07:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1686128822; x=1688720822; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Nz76j0qRG7M80pmlEKyVRAG1FYXj27a46ctowWFtgUI=; b=EwJ6ylXOZhGaP+0ge6C4IJsrjlSUexk1wQ6jL3h3wsudSISMlA/XDzEVnr91bilrJY ctT78e5Tf15nGS3bKaNGTd0zw4MoJ/EAwEfIcwuz2YEKYPhx6pX96frDRMCVbZKPXuIf zUPolFsiG4YV2W9LmDFX6U3BILbEJB4grFYuU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686128822; x=1688720822; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Nz76j0qRG7M80pmlEKyVRAG1FYXj27a46ctowWFtgUI=; b=WNGMXV37+1cVGLLcN35IWPjKvfwrLUt4yybOARN/QYA4bSNPDEqt3gjgVcRdz6QE8g LU9NxrPDUitX/An2LQacaVVEa0bY/uLOGQnS6Zxg+2/+C+NKfar+jVrcUziDoluaraGN sZV8GYUUA0GRGaVb+JkqcATlQRGFzAYMHuHaKEyRdLV0ElLH98RUAx0DXtQ5j0oteVyt 14E9xgtIAjNxyrnS25RInpV5l+3OQzdbLWdgK3pPYOo994UrZy0nSV7K6wUbNCxpCDa7 +FQXMBiRagcrgucLUIoTzIK+6rBhxJVcJSIzr2OY3h/ww5T8IgzRbYhHqXr8gSISPl6a Adiw== X-Gm-Message-State: AC+VfDznwyNbiQmJxDgdztiFoHCEhbEZGjOi+j0NYvxicWAETAxGqevA FRFoYIdvT0hb06HWUYw0ln+LYw== X-Google-Smtp-Source: ACHHUZ7hcSVOowiPXhPeqmmoXLnSzASTWamdqYbyKBsrA0/VfrVRfq1YMn7GAAugHeW71s9tNSygag== X-Received: by 2002:a05:6358:c591:b0:125:a552:4389 with SMTP id fc17-20020a056358c59100b00125a5524389mr2980713rwb.22.1686128822414; Wed, 07 Jun 2023 02:07:02 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:443b:29bb:b677:185d]) by smtp.gmail.com with ESMTPSA id b38-20020a631b66000000b0051eff0a70d7sm8505732pgm.94.2023.06.07.02.07.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Jun 2023 02:07:02 -0700 (PDT) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno Cc: Chen-Yu Tsai , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH 1/4] arm64: dts: mediatek: mt8186: Add CCI node and CCI OPP table Date: Wed, 7 Jun 2023 17:06:49 +0800 Message-ID: <20230607090653.2468317-2-wenst@chromium.org> X-Mailer: git-send-email 2.41.0.rc0.172.g3f132b7071-goog In-Reply-To: <20230607090653.2468317-1-wenst@chromium.org> References: <20230607090653.2468317-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a device node for the CCI (cache coherent interconnect) and an OPP table for it. The OPP table was taken from the downstream ChromeOS kernel. Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 117 +++++++++++++++++++++++ 1 file changed, 117 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index 8c02232cac38..1b754f7a0725 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -27,6 +27,115 @@ aliases { rdma1 =3D &rdma1; }; =20 + cci: cci { + compatible =3D "mediatek,mt8186-cci"; + clocks =3D <&mcusys CLK_MCU_ARMPLL_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names =3D "cci", "intermediate"; + operating-points-v2 =3D <&cci_opp>; + }; + + cci_opp: opp-table-cci { + compatible =3D "operating-points-v2"; + opp-shared; + + cci_opp_0: opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + opp-microvolt =3D <600000>; + opp-level =3D <15>; + }; + + cci_opp_1: opp-560000000 { + opp-hz =3D /bits/ 64 <560000000>; + opp-microvolt =3D <675000>; + opp-level =3D <14>; + }; + + cci_opp_2: opp-612000000 { + opp-hz =3D /bits/ 64 <612000000>; + opp-microvolt =3D <693750>; + opp-level =3D <13>; + }; + + cci_opp_3: opp-682000000 { + opp-hz =3D /bits/ 64 <682000000>; + opp-microvolt =3D <718750>; + opp-level =3D <12>; + }; + + cci_opp_4: opp-752000000 { + opp-hz =3D /bits/ 64 <752000000>; + opp-microvolt =3D <743750>; + opp-level =3D <11>; + }; + + cci_opp_5: opp-822000000 { + opp-hz =3D /bits/ 64 <822000000>; + opp-microvolt =3D <768750>; + opp-level =3D <10>; + }; + + cci_opp_6: opp-875000000 { + opp-hz =3D /bits/ 64 <875000000>; + opp-microvolt =3D <781250>; + opp-level =3D <9>; + }; + + cci_opp_7: opp-927000000 { + opp-hz =3D /bits/ 64 <927000000>; + opp-microvolt =3D <800000>; + opp-level =3D <8>; + }; + + cci_opp_8: opp-980000000 { + opp-hz =3D /bits/ 64 <980000000>; + opp-microvolt =3D <818750>; + opp-level =3D <7>; + }; + + cci_opp_9: opp-1050000000 { + opp-hz =3D /bits/ 64 <1050000000>; + opp-microvolt =3D <843750>; + opp-level =3D <6>; + }; + + cci_opp_10: opp-1120000000 { + opp-hz =3D /bits/ 64 <1120000000>; + opp-microvolt =3D <862500>; + opp-level =3D <5>; + }; + + cci_opp_11: opp-1155000000 { + opp-hz =3D /bits/ 64 <1155000000>; + opp-microvolt =3D <887500>; + opp-level =3D <4>; + }; + + cci_opp_12: opp-1190000000 { + opp-hz =3D /bits/ 64 <1190000000>; + opp-microvolt =3D <906250>; + opp-level =3D <3>; + }; + + cci_opp_13: opp-1260000000 { + opp-hz =3D /bits/ 64 <1260000000>; + opp-microvolt =3D <950000>; + opp-level =3D <2>; + }; + + cci_opp_14: opp-1330000000 { + opp-hz =3D /bits/ 64 <1330000000>; + opp-microvolt =3D <993750>; + opp-level =3D <1>; + }; + + cci_opp_15: opp-1400000000 { + opp-hz =3D /bits/ 64 <1400000000>; + opp-microvolt =3D <1031250>; + opp-level =3D <0>; + }; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; @@ -83,6 +192,7 @@ cpu0: cpu@0 { d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; + mediatek,cci =3D <&cci>; }; =20 cpu1: cpu@100 { @@ -101,6 +211,7 @@ cpu1: cpu@100 { d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; + mediatek,cci =3D <&cci>; }; =20 cpu2: cpu@200 { @@ -119,6 +230,7 @@ cpu2: cpu@200 { d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; + mediatek,cci =3D <&cci>; }; =20 cpu3: cpu@300 { @@ -137,6 +249,7 @@ cpu3: cpu@300 { d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; + mediatek,cci =3D <&cci>; }; =20 cpu4: cpu@400 { @@ -155,6 +268,7 @@ cpu4: cpu@400 { d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; + mediatek,cci =3D <&cci>; }; =20 cpu5: cpu@500 { @@ -173,6 +287,7 @@ cpu5: cpu@500 { d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; + mediatek,cci =3D <&cci>; }; =20 cpu6: cpu@600 { @@ -191,6 +306,7 @@ cpu6: cpu@600 { d-cache-sets =3D <256>; next-level-cache =3D <&l2_1>; #cooling-cells =3D <2>; + mediatek,cci =3D <&cci>; }; =20 cpu7: cpu@700 { @@ -209,6 +325,7 @@ cpu7: cpu@700 { d-cache-sets =3D <256>; next-level-cache =3D <&l2_1>; #cooling-cells =3D <2>; + mediatek,cci =3D <&cci>; }; =20 idle-states { --=20 2.41.0.rc0.172.g3f132b7071-goog