From nobody Fri Sep 20 18:46:28 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7466C7EE2E for ; Wed, 7 Jun 2023 09:08:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239811AbjFGJIQ (ORCPT ); Wed, 7 Jun 2023 05:08:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239795AbjFGJHl (ORCPT ); Wed, 7 Jun 2023 05:07:41 -0400 Received: from mail-oa1-x31.google.com (mail-oa1-x31.google.com [IPv6:2001:4860:4864:20::31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4468426B1 for ; Wed, 7 Jun 2023 02:07:03 -0700 (PDT) Received: by mail-oa1-x31.google.com with SMTP id 586e51a60fabf-1a27ffe9dcdso6801206fac.2 for ; Wed, 07 Jun 2023 02:07:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1686128822; x=1688720822; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Nz76j0qRG7M80pmlEKyVRAG1FYXj27a46ctowWFtgUI=; b=EwJ6ylXOZhGaP+0ge6C4IJsrjlSUexk1wQ6jL3h3wsudSISMlA/XDzEVnr91bilrJY ctT78e5Tf15nGS3bKaNGTd0zw4MoJ/EAwEfIcwuz2YEKYPhx6pX96frDRMCVbZKPXuIf zUPolFsiG4YV2W9LmDFX6U3BILbEJB4grFYuU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686128822; x=1688720822; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Nz76j0qRG7M80pmlEKyVRAG1FYXj27a46ctowWFtgUI=; b=WNGMXV37+1cVGLLcN35IWPjKvfwrLUt4yybOARN/QYA4bSNPDEqt3gjgVcRdz6QE8g LU9NxrPDUitX/An2LQacaVVEa0bY/uLOGQnS6Zxg+2/+C+NKfar+jVrcUziDoluaraGN sZV8GYUUA0GRGaVb+JkqcATlQRGFzAYMHuHaKEyRdLV0ElLH98RUAx0DXtQ5j0oteVyt 14E9xgtIAjNxyrnS25RInpV5l+3OQzdbLWdgK3pPYOo994UrZy0nSV7K6wUbNCxpCDa7 +FQXMBiRagcrgucLUIoTzIK+6rBhxJVcJSIzr2OY3h/ww5T8IgzRbYhHqXr8gSISPl6a Adiw== X-Gm-Message-State: AC+VfDznwyNbiQmJxDgdztiFoHCEhbEZGjOi+j0NYvxicWAETAxGqevA FRFoYIdvT0hb06HWUYw0ln+LYw== X-Google-Smtp-Source: ACHHUZ7hcSVOowiPXhPeqmmoXLnSzASTWamdqYbyKBsrA0/VfrVRfq1YMn7GAAugHeW71s9tNSygag== X-Received: by 2002:a05:6358:c591:b0:125:a552:4389 with SMTP id fc17-20020a056358c59100b00125a5524389mr2980713rwb.22.1686128822414; Wed, 07 Jun 2023 02:07:02 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:443b:29bb:b677:185d]) by smtp.gmail.com with ESMTPSA id b38-20020a631b66000000b0051eff0a70d7sm8505732pgm.94.2023.06.07.02.07.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Jun 2023 02:07:02 -0700 (PDT) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno Cc: Chen-Yu Tsai , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH 1/4] arm64: dts: mediatek: mt8186: Add CCI node and CCI OPP table Date: Wed, 7 Jun 2023 17:06:49 +0800 Message-ID: <20230607090653.2468317-2-wenst@chromium.org> X-Mailer: git-send-email 2.41.0.rc0.172.g3f132b7071-goog In-Reply-To: <20230607090653.2468317-1-wenst@chromium.org> References: <20230607090653.2468317-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a device node for the CCI (cache coherent interconnect) and an OPP table for it. The OPP table was taken from the downstream ChromeOS kernel. Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 117 +++++++++++++++++++++++ 1 file changed, 117 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index 8c02232cac38..1b754f7a0725 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -27,6 +27,115 @@ aliases { rdma1 =3D &rdma1; }; =20 + cci: cci { + compatible =3D "mediatek,mt8186-cci"; + clocks =3D <&mcusys CLK_MCU_ARMPLL_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names =3D "cci", "intermediate"; + operating-points-v2 =3D <&cci_opp>; + }; + + cci_opp: opp-table-cci { + compatible =3D "operating-points-v2"; + opp-shared; + + cci_opp_0: opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + opp-microvolt =3D <600000>; + opp-level =3D <15>; + }; + + cci_opp_1: opp-560000000 { + opp-hz =3D /bits/ 64 <560000000>; + opp-microvolt =3D <675000>; + opp-level =3D <14>; + }; + + cci_opp_2: opp-612000000 { + opp-hz =3D /bits/ 64 <612000000>; + opp-microvolt =3D <693750>; + opp-level =3D <13>; + }; + + cci_opp_3: opp-682000000 { + opp-hz =3D /bits/ 64 <682000000>; + opp-microvolt =3D <718750>; + opp-level =3D <12>; + }; + + cci_opp_4: opp-752000000 { + opp-hz =3D /bits/ 64 <752000000>; + opp-microvolt =3D <743750>; + opp-level =3D <11>; + }; + + cci_opp_5: opp-822000000 { + opp-hz =3D /bits/ 64 <822000000>; + opp-microvolt =3D <768750>; + opp-level =3D <10>; + }; + + cci_opp_6: opp-875000000 { + opp-hz =3D /bits/ 64 <875000000>; + opp-microvolt =3D <781250>; + opp-level =3D <9>; + }; + + cci_opp_7: opp-927000000 { + opp-hz =3D /bits/ 64 <927000000>; + opp-microvolt =3D <800000>; + opp-level =3D <8>; + }; + + cci_opp_8: opp-980000000 { + opp-hz =3D /bits/ 64 <980000000>; + opp-microvolt =3D <818750>; + opp-level =3D <7>; + }; + + cci_opp_9: opp-1050000000 { + opp-hz =3D /bits/ 64 <1050000000>; + opp-microvolt =3D <843750>; + opp-level =3D <6>; + }; + + cci_opp_10: opp-1120000000 { + opp-hz =3D /bits/ 64 <1120000000>; + opp-microvolt =3D <862500>; + opp-level =3D <5>; + }; + + cci_opp_11: opp-1155000000 { + opp-hz =3D /bits/ 64 <1155000000>; + opp-microvolt =3D <887500>; + opp-level =3D <4>; + }; + + cci_opp_12: opp-1190000000 { + opp-hz =3D /bits/ 64 <1190000000>; + opp-microvolt =3D <906250>; + opp-level =3D <3>; + }; + + cci_opp_13: opp-1260000000 { + opp-hz =3D /bits/ 64 <1260000000>; + opp-microvolt =3D <950000>; + opp-level =3D <2>; + }; + + cci_opp_14: opp-1330000000 { + opp-hz =3D /bits/ 64 <1330000000>; + opp-microvolt =3D <993750>; + opp-level =3D <1>; + }; + + cci_opp_15: opp-1400000000 { + opp-hz =3D /bits/ 64 <1400000000>; + opp-microvolt =3D <1031250>; + opp-level =3D <0>; + }; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; @@ -83,6 +192,7 @@ cpu0: cpu@0 { d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; + mediatek,cci =3D <&cci>; }; =20 cpu1: cpu@100 { @@ -101,6 +211,7 @@ cpu1: cpu@100 { d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; + mediatek,cci =3D <&cci>; }; =20 cpu2: cpu@200 { @@ -119,6 +230,7 @@ cpu2: cpu@200 { d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; + mediatek,cci =3D <&cci>; }; =20 cpu3: cpu@300 { @@ -137,6 +249,7 @@ cpu3: cpu@300 { d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; + mediatek,cci =3D <&cci>; }; =20 cpu4: cpu@400 { @@ -155,6 +268,7 @@ cpu4: cpu@400 { d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; + mediatek,cci =3D <&cci>; }; =20 cpu5: cpu@500 { @@ -173,6 +287,7 @@ cpu5: cpu@500 { d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; #cooling-cells =3D <2>; + mediatek,cci =3D <&cci>; }; =20 cpu6: cpu@600 { @@ -191,6 +306,7 @@ cpu6: cpu@600 { d-cache-sets =3D <256>; next-level-cache =3D <&l2_1>; #cooling-cells =3D <2>; + mediatek,cci =3D <&cci>; }; =20 cpu7: cpu@700 { @@ -209,6 +325,7 @@ cpu7: cpu@700 { d-cache-sets =3D <256>; next-level-cache =3D <&l2_1>; #cooling-cells =3D <2>; + mediatek,cci =3D <&cci>; }; =20 idle-states { --=20 2.41.0.rc0.172.g3f132b7071-goog From nobody Fri Sep 20 18:46:28 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5B2DC7EE2E for ; Wed, 7 Jun 2023 09:08:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238374AbjFGJIS (ORCPT ); Wed, 7 Jun 2023 05:08:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33144 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237902AbjFGJHm (ORCPT ); Wed, 7 Jun 2023 05:07:42 -0400 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 108EA1FFD for ; Wed, 7 Jun 2023 02:07:05 -0700 (PDT) Received: by mail-pj1-x1029.google.com with SMTP id 98e67ed59e1d1-25695bb6461so291807a91.1 for ; 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Wed, 07 Jun 2023 02:07:04 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:443b:29bb:b677:185d]) by smtp.gmail.com with ESMTPSA id b38-20020a631b66000000b0051eff0a70d7sm8505732pgm.94.2023.06.07.02.07.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Jun 2023 02:07:04 -0700 (PDT) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno Cc: Chen-Yu Tsai , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH 2/4] arm64: dts: mediatek: mt8186: Wire up CPU frequency/voltage scaling Date: Wed, 7 Jun 2023 17:06:50 +0800 Message-ID: <20230607090653.2468317-3-wenst@chromium.org> X-Mailer: git-send-email 2.41.0.rc0.172.g3f132b7071-goog In-Reply-To: <20230607090653.2468317-1-wenst@chromium.org> References: <20230607090653.2468317-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds clocks, dynamic power coefficients, and OPP tables for the CPU cores, so that everything required at the SoC level for CPU freqency and voltage scaling is available. Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 274 +++++++++++++++++++++++ 1 file changed, 274 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index 1b754f7a0725..6735c1feb26d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -136,6 +136,240 @@ cci_opp_15: opp-1400000000 { }; }; =20 + cluster0_opp: opp-table-cluster0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + opp-microvolt =3D <600000>; + opp-level =3D <15>; + required-opps =3D <&cci_opp_0>; + }; + + opp-774000000 { + opp-hz =3D /bits/ 64 <774000000>; + opp-microvolt =3D <675000>; + opp-level =3D <14>; + required-opps =3D <&cci_opp_1>; + }; + + opp-875000000 { + opp-hz =3D /bits/ 64 <875000000>; + opp-microvolt =3D <700000>; + opp-level =3D <13>; + required-opps =3D <&cci_opp_2>; + }; + + opp-975000000 { + opp-hz =3D /bits/ 64 <975000000>; + opp-microvolt =3D <725000>; + opp-level =3D <12>; + required-opps =3D <&cci_opp_3>; + }; + + opp-1075000000 { + opp-hz =3D /bits/ 64 <1075000000>; + opp-microvolt =3D <750000>; + opp-level =3D <11>; + required-opps =3D <&cci_opp_4>; + }; + + opp-1175000000 { + opp-hz =3D /bits/ 64 <1175000000>; + opp-microvolt =3D <775000>; + opp-level =3D <10>; + required-opps =3D <&cci_opp_5>; + }; + + opp-1275000000 { + opp-hz =3D /bits/ 64 <1275000000>; + opp-microvolt =3D <800000>; + opp-level =3D <9>; + required-opps =3D <&cci_opp_6>; + }; + + opp-1375000000 { + opp-hz =3D /bits/ 64 <1375000000>; + opp-microvolt =3D <825000>; + opp-level =3D <8>; + required-opps =3D <&cci_opp_7>; + }; + + opp-1500000000 { + opp-hz =3D /bits/ 64 <1500000000>; + opp-microvolt =3D <856250>; + opp-level =3D <7>; + required-opps =3D <&cci_opp_8>; + }; + + opp-1618000000 { + opp-hz =3D /bits/ 64 <1618000000>; + opp-microvolt =3D <875000>; + opp-level =3D <6>; + required-opps =3D <&cci_opp_9>; + }; + + opp-1666000000 { + opp-hz =3D /bits/ 64 <1666000000>; + opp-microvolt =3D <900000>; + opp-level =3D <5>; + required-opps =3D <&cci_opp_10>; + }; + + opp-1733000000 { + opp-hz =3D /bits/ 64 <1733000000>; + opp-microvolt =3D <925000>; + opp-level =3D <4>; + required-opps =3D <&cci_opp_11>; + }; + + opp-1800000000 { + opp-hz =3D /bits/ 64 <1800000000>; + opp-microvolt =3D <950000>; + opp-level =3D <3>; + required-opps =3D <&cci_opp_12>; + }; + + opp-1866000000 { + opp-hz =3D /bits/ 64 <1866000000>; + opp-microvolt =3D <981250>; + opp-level =3D <2>; + required-opps =3D <&cci_opp_13>; + }; + + opp-1933000000 { + opp-hz =3D /bits/ 64 <1933000000>; + opp-microvolt =3D <1006250>; + opp-level =3D <1>; + required-opps =3D <&cci_opp_14>; + }; + + opp-2000000000 { + opp-hz =3D /bits/ 64 <2000000000>; + opp-microvolt =3D <1031250>; + opp-level =3D <0>; + required-opps =3D <&cci_opp_15>; + }; + }; + + cluster1_opp: opp-table-cluster1 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-774000000 { + opp-hz =3D /bits/ 64 <774000000>; + opp-microvolt =3D <675000>; + opp-level =3D <15>; + required-opps =3D <&cci_opp_0>; + }; + + opp-835000000 { + opp-hz =3D /bits/ 64 <835000000>; + opp-microvolt =3D <693750>; + opp-level =3D <14>; + required-opps =3D <&cci_opp_1>; + }; + + opp-919000000 { + opp-hz =3D /bits/ 64 <919000000>; + opp-microvolt =3D <718750>; + opp-level =3D <13>; + required-opps =3D <&cci_opp_2>; + }; + + opp-1002000000 { + opp-hz =3D /bits/ 64 <1002000000>; + opp-microvolt =3D <743750>; + opp-level =3D <12>; + required-opps =3D <&cci_opp_3>; + }; + + opp-1085000000 { + opp-hz =3D /bits/ 64 <1085000000>; + opp-microvolt =3D <775000>; + opp-level =3D <11>; + required-opps =3D <&cci_opp_4>; + }; + + opp-1169000000 { + opp-hz =3D /bits/ 64 <1169000000>; + opp-microvolt =3D <800000>; + opp-level =3D <10>; + required-opps =3D <&cci_opp_5>; + }; + + opp-1308000000 { + opp-hz =3D /bits/ 64 <1308000000>; + opp-microvolt =3D <843750>; + opp-level =3D <9>; + required-opps =3D <&cci_opp_6>; + }; + + opp-1419000000 { + opp-hz =3D /bits/ 64 <1419000000>; + opp-microvolt =3D <875000>; + opp-level =3D <8>; + required-opps =3D <&cci_opp_7>; + }; + + opp-1530000000 { + opp-hz =3D /bits/ 64 <1530000000>; + opp-microvolt =3D <912500>; + opp-level =3D <7>; + required-opps =3D <&cci_opp_8>; + }; + + opp-1670000000 { + opp-hz =3D /bits/ 64 <1670000000>; + opp-microvolt =3D <956250>; + opp-level =3D <6>; + required-opps =3D <&cci_opp_9>; + }; + + opp-1733000000 { + opp-hz =3D /bits/ 64 <1733000000>; + opp-microvolt =3D <981250>; + opp-level =3D <5>; + required-opps =3D <&cci_opp_10>; + }; + + opp-1796000000 { + opp-hz =3D /bits/ 64 <1796000000>; + opp-microvolt =3D <1012500>; + opp-level =3D <4>; + required-opps =3D <&cci_opp_11>; + }; + + opp-1860000000 { + opp-hz =3D /bits/ 64 <1860000000>; + opp-microvolt =3D <1037500>; + opp-level =3D <3>; + required-opps =3D <&cci_opp_12>; + }; + + opp-1923000000 { + opp-hz =3D /bits/ 64 <1923000000>; + opp-microvolt =3D <1062500>; + opp-level =3D <2>; + required-opps =3D <&cci_opp_13>; + }; + + cluster1_opp_14: opp-1986000000 { + opp-hz =3D /bits/ 64 <1986000000>; + opp-microvolt =3D <1093750>; + opp-level =3D <1>; + required-opps =3D <&cci_opp_14>; + }; + + cluster1_opp_15: opp-2050000000 { + opp-hz =3D /bits/ 64 <2050000000>; + opp-microvolt =3D <1118750>; + opp-level =3D <0>; + required-opps =3D <&cci_opp_15>; + }; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; @@ -182,6 +416,11 @@ cpu0: cpu@0 { reg =3D <0x000>; enable-method =3D "psci"; clock-frequency =3D <2000000000>; + clocks =3D <&mcusys CLK_MCU_ARMPLL_LL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names =3D "cpu", "intermediate"; + operating-points-v2 =3D <&cluster0_opp>; + dynamic-power-coefficient =3D <84>; capacity-dmips-mhz =3D <382>; cpu-idle-states =3D <&cpu_ret_l &cpu_off_l>; i-cache-size =3D <32768>; @@ -201,6 +440,11 @@ cpu1: cpu@100 { reg =3D <0x100>; enable-method =3D "psci"; clock-frequency =3D <2000000000>; + clocks =3D <&mcusys CLK_MCU_ARMPLL_LL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names =3D "cpu", "intermediate"; + operating-points-v2 =3D <&cluster0_opp>; + dynamic-power-coefficient =3D <84>; capacity-dmips-mhz =3D <382>; cpu-idle-states =3D <&cpu_ret_l &cpu_off_l>; i-cache-size =3D <32768>; @@ -220,6 +464,11 @@ cpu2: cpu@200 { reg =3D <0x200>; enable-method =3D "psci"; clock-frequency =3D <2000000000>; + clocks =3D <&mcusys CLK_MCU_ARMPLL_LL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names =3D "cpu", "intermediate"; + operating-points-v2 =3D <&cluster0_opp>; + dynamic-power-coefficient =3D <84>; capacity-dmips-mhz =3D <382>; cpu-idle-states =3D <&cpu_ret_l &cpu_off_l>; i-cache-size =3D <32768>; @@ -239,6 +488,11 @@ cpu3: cpu@300 { reg =3D <0x300>; enable-method =3D "psci"; clock-frequency =3D <2000000000>; + clocks =3D <&mcusys CLK_MCU_ARMPLL_LL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names =3D "cpu", "intermediate"; + operating-points-v2 =3D <&cluster0_opp>; + dynamic-power-coefficient =3D <84>; capacity-dmips-mhz =3D <382>; cpu-idle-states =3D <&cpu_ret_l &cpu_off_l>; i-cache-size =3D <32768>; @@ -258,6 +512,11 @@ cpu4: cpu@400 { reg =3D <0x400>; enable-method =3D "psci"; clock-frequency =3D <2000000000>; + clocks =3D <&mcusys CLK_MCU_ARMPLL_LL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names =3D "cpu", "intermediate"; + operating-points-v2 =3D <&cluster0_opp>; + dynamic-power-coefficient =3D <84>; capacity-dmips-mhz =3D <382>; cpu-idle-states =3D <&cpu_ret_l &cpu_off_l>; i-cache-size =3D <32768>; @@ -277,6 +536,11 @@ cpu5: cpu@500 { reg =3D <0x500>; enable-method =3D "psci"; clock-frequency =3D <2000000000>; + clocks =3D <&mcusys CLK_MCU_ARMPLL_LL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names =3D "cpu", "intermediate"; + operating-points-v2 =3D <&cluster0_opp>; + dynamic-power-coefficient =3D <84>; capacity-dmips-mhz =3D <382>; cpu-idle-states =3D <&cpu_ret_l &cpu_off_l>; i-cache-size =3D <32768>; @@ -296,6 +560,11 @@ cpu6: cpu@600 { reg =3D <0x600>; enable-method =3D "psci"; clock-frequency =3D <2050000000>; + clocks =3D <&mcusys CLK_MCU_ARMPLL_BL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names =3D "cpu", "intermediate"; + operating-points-v2 =3D <&cluster1_opp>; + dynamic-power-coefficient =3D <335>; capacity-dmips-mhz =3D <1024>; cpu-idle-states =3D <&cpu_ret_b &cpu_off_b>; i-cache-size =3D <65536>; @@ -315,6 +584,11 @@ cpu7: cpu@700 { reg =3D <0x700>; enable-method =3D "psci"; clock-frequency =3D <2050000000>; + clocks =3D <&mcusys CLK_MCU_ARMPLL_BL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names =3D "cpu", "intermediate"; + operating-points-v2 =3D <&cluster1_opp>; + dynamic-power-coefficient =3D <335>; capacity-dmips-mhz =3D <1024>; cpu-idle-states =3D <&cpu_ret_b &cpu_off_b>; i-cache-size =3D <65536>; --=20 2.41.0.rc0.172.g3f132b7071-goog From nobody Fri Sep 20 18:46:28 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65A3DC7EE29 for ; Wed, 7 Jun 2023 09:08:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239346AbjFGJI3 (ORCPT ); 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Wed, 07 Jun 2023 02:07:06 -0700 (PDT) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno Cc: Chen-Yu Tsai , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH 3/4] arm64: dts: mediatek: mt8186: Add GPU speed bin NVMEM cells Date: Wed, 7 Jun 2023 17:06:51 +0800 Message-ID: <20230607090653.2468317-4-wenst@chromium.org> X-Mailer: git-send-email 2.41.0.rc0.172.g3f132b7071-goog In-Reply-To: <20230607090653.2468317-1-wenst@chromium.org> References: <20230607090653.2468317-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" On the MT8186, the chip is binned for different GPU voltages at the highest OPPs. The binning value is stored in the efuse. Add the NVMEM cell, and tie it to the GPU. Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index 6735c1feb26d..c58d7eb87b1d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -1567,6 +1567,11 @@ efuse: efuse@11cb0000 { reg =3D <0 0x11cb0000 0 0x1000>; #address-cells =3D <1>; #size-cells =3D <1>; + + gpu_speedbin: gpu-speed-bin@59c { + reg =3D <0x59c 0x4>; + bits =3D <0 3>; + }; }; =20 mipi_tx0: dsi-phy@11cc0000 { @@ -1599,6 +1604,8 @@ gpu: gpu@13040000 { <&spm MT8186_POWER_DOMAIN_MFG3>; power-domain-names =3D "core0", "core1"; #cooling-cells =3D <2>; + nvmem-cells =3D <&gpu_speedbin>; + nvmem-cell-names =3D "speed-bin"; status =3D "disabled"; }; =20 --=20 2.41.0.rc0.172.g3f132b7071-goog From nobody Fri Sep 20 18:46:28 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7991EC77B7A for ; Wed, 7 Jun 2023 09:08:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239837AbjFGJIh (ORCPT ); Wed, 7 Jun 2023 05:08:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239345AbjFGJHy (ORCPT ); Wed, 7 Jun 2023 05:07:54 -0400 Received: from mail-io1-xd36.google.com (mail-io1-xd36.google.com [IPv6:2607:f8b0:4864:20::d36]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5CD612705 for ; Wed, 7 Jun 2023 02:07:09 -0700 (PDT) Received: by mail-io1-xd36.google.com with SMTP id ca18e2360f4ac-777a9d7efabso139316039f.0 for ; Wed, 07 Jun 2023 02:07:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1686128828; x=1688720828; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=56q05UsuazQ3l9IlZm8IljgHBiGaLsgNecYNIgR23ec=; b=Pbg94OW6ek039a4YB9fBJOxqVm+c0gaM+NU3BtgP5wjdxHtmeqiTua5bs0no0CzVLD NTtR6cd3xEdCHngH4Od25Yaad1QfhRKp6dzXsWp8a8B27Yuznc7YnpifNu/2Jfh8CVT6 LGfEPy0OjxPUv4lrbBwjjmBYevQSsE9bZIFvo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686128828; x=1688720828; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=56q05UsuazQ3l9IlZm8IljgHBiGaLsgNecYNIgR23ec=; b=Ug5kDVI3z5syeMk4Sb6wnKZkEdks4Uk/Sju4YsHr2lLguXyPOe/9xYe5fC8wHB35E/ Kd73Fc0XftXKBNR1JRpj6K15kfLjsFQX0i0PWCxGw7iz9FtYeSob6x8eWMyiOKj6b/oR UWhKKueS9gea+q4DxYXbKq5MJUEhJjFxwwuUrXfr9BYmJgWLOIkrFXjjQiQ449M3P9y+ HZ2B9lg3CS8f4w/+QbOf4EkB1pEWCM68Jkr5th7eOOuVqjMNNaNJvqvcSKSGtrGyN3i0 K3O1PS51nO0d7+I7xOeu2aUddrxvxWNomTuwrVSHp0jvKL9d8qVYaPxFf76cKFAzcBso jLAg== X-Gm-Message-State: AC+VfDzNnXOgBuoyalgNw0iRPXvWugP0JBsONDUiKTY/zif5zMShZJ+4 oi8xyFV/BJi8j1X+Mx0K1Xw52A== X-Google-Smtp-Source: ACHHUZ4J+NGvRiWFsYnVvU8HZ+cJ1PTzOi6W8RcxMQCnO35ocFrm/rLAAwyedcTfixlvTCB6sxETLA== X-Received: by 2002:a6b:e31a:0:b0:777:b409:fb67 with SMTP id u26-20020a6be31a000000b00777b409fb67mr5631749ioc.4.1686128828683; Wed, 07 Jun 2023 02:07:08 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:443b:29bb:b677:185d]) by smtp.gmail.com with ESMTPSA id b38-20020a631b66000000b0051eff0a70d7sm8505732pgm.94.2023.06.07.02.07.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Jun 2023 02:07:08 -0700 (PDT) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno Cc: Chen-Yu Tsai , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH 4/4] arm64: dts: mediatek: mt8186: Wire up GPU voltage/frequency scaling Date: Wed, 7 Jun 2023 17:06:52 +0800 Message-ID: <20230607090653.2468317-5-wenst@chromium.org> X-Mailer: git-send-email 2.41.0.rc0.172.g3f132b7071-goog In-Reply-To: <20230607090653.2468317-1-wenst@chromium.org> References: <20230607090653.2468317-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the GPU's OPP table. This is from the downstream ChromeOS kernel, adapted to the new upstream opp-supported-hw binning format. Also add dynamic-power-coefficient for the GPU. Also add label for mfg1 power domain. This is to be used at the board level to add a regulator supply for the power domain. Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 140 ++++++++++++++++++++++- 1 file changed, 139 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index c58d7eb87b1d..a34489e27cd4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -695,6 +695,142 @@ clk32k: oscillator-32k { clock-output-names =3D "clk32k"; }; =20 + gpu_opp_table: opp-table-gpu { + compatible =3D "operating-points-v2"; + + opp-299000000 { + opp-hz =3D /bits/ 64 <299000000>; + opp-microvolt =3D <612500>; + opp-supported-hw =3D <0x38>; + }; + + opp-332000000 { + opp-hz =3D /bits/ 64 <332000000>; + opp-microvolt =3D <625000>; + opp-supported-hw =3D <0x38>; + }; + + opp-366000000 { + opp-hz =3D /bits/ 64 <366000000>; + opp-microvolt =3D <637500>; + opp-supported-hw =3D <0x38>; + }; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + opp-microvolt =3D <643750>; + opp-supported-hw =3D <0x38>; + }; + + opp-434000000 { + opp-hz =3D /bits/ 64 <434000000>; + opp-microvolt =3D <656250>; + opp-supported-hw =3D <0x38>; + }; + + opp-484000000 { + opp-hz =3D /bits/ 64 <484000000>; + opp-microvolt =3D <668750>; + opp-supported-hw =3D <0x38>; + }; + + opp-535000000 { + opp-hz =3D /bits/ 64 <535000000>; + opp-microvolt =3D <687500>; + opp-supported-hw =3D <0x38>; + }; + + opp-586000000 { + opp-hz =3D /bits/ 64 <586000000>; + opp-microvolt =3D <700000>; + opp-supported-hw =3D <0x38>; + }; + + opp-637000000 { + opp-hz =3D /bits/ 64 <637000000>; + opp-microvolt =3D <712500>; + opp-supported-hw =3D <0x38>; + }; + + opp-690000000 { + opp-hz =3D /bits/ 64 <690000000>; + opp-microvolt =3D <737500>; + opp-supported-hw =3D <0x38>; + }; + + opp-743000000 { + opp-hz =3D /bits/ 64 <743000000>; + opp-microvolt =3D <756250>; + opp-supported-hw =3D <0x38>; + }; + + opp-796000000 { + opp-hz =3D /bits/ 64 <796000000>; + opp-microvolt =3D <781250>; + opp-supported-hw =3D <0x38>; + }; + + opp-850000000 { + opp-hz =3D /bits/ 64 <850000000>; + opp-microvolt =3D <800000>; + opp-supported-hw =3D <0x38>; + }; + + opp-900000000-3 { + opp-hz =3D /bits/ 64 <900000000>; + opp-microvolt =3D <850000>; + opp-supported-hw =3D <0x8>; + }; + + opp-900000000-4 { + opp-hz =3D /bits/ 64 <900000000>; + opp-microvolt =3D <837500>; + opp-supported-hw =3D <0x10>; + }; + + opp-900000000-5 { + opp-hz =3D /bits/ 64 <900000000>; + opp-microvolt =3D <825000>; + opp-supported-hw =3D <0x30>; + }; + + opp-950000000-3 { + opp-hz =3D /bits/ 64 <950000000>; + opp-microvolt =3D <900000>; + opp-supported-hw =3D <0x8>; + }; + + opp-950000000-4 { + opp-hz =3D /bits/ 64 <950000000>; + opp-microvolt =3D <875000>; + opp-supported-hw =3D <0x10>; + }; + + opp-950000000-5 { + opp-hz =3D /bits/ 64 <950000000>; + opp-microvolt =3D <850000>; + opp-supported-hw =3D <0x30>; + }; + + opp-1000000000-3 { + opp-hz =3D /bits/ 64 <1000000000>; + opp-microvolt =3D <950000>; + opp-supported-hw =3D <0x8>; + }; + + opp-1000000000-4 { + opp-hz =3D /bits/ 64 <1000000000>; + opp-microvolt =3D <912500>; + opp-supported-hw =3D <0x10>; + }; + + opp-1000000000-5 { + opp-hz =3D /bits/ 64 <1000000000>; + opp-microvolt =3D <875000>; + opp-supported-hw =3D <0x30>; + }; + }; + pmu-a55 { compatible =3D "arm,cortex-a55-pmu"; interrupt-parent =3D <&gic>; @@ -813,7 +949,7 @@ mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 { #size-cells =3D <0>; #power-domain-cells =3D <1>; =20 - power-domain@MT8186_POWER_DOMAIN_MFG1 { + mfg1: power-domain@MT8186_POWER_DOMAIN_MFG1 { reg =3D ; mediatek,infracfg =3D <&infracfg_ao>; #address-cells =3D <1>; @@ -1606,6 +1742,8 @@ gpu: gpu@13040000 { #cooling-cells =3D <2>; nvmem-cells =3D <&gpu_speedbin>; nvmem-cell-names =3D "speed-bin"; + operating-points-v2 =3D <&gpu_opp_table>; + dynamic-power-coefficient =3D <4687>; status =3D "disabled"; }; =20 --=20 2.41.0.rc0.172.g3f132b7071-goog