From nobody Sat Feb 7 23:47:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7008C7EE37 for ; Wed, 7 Jun 2023 01:02:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240408AbjFGBCW (ORCPT ); Tue, 6 Jun 2023 21:02:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53598 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240381AbjFGBCN (ORCPT ); Tue, 6 Jun 2023 21:02:13 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EBE25124 for ; Tue, 6 Jun 2023 18:02:11 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-bad06cc7fb7so10988202276.3 for ; Tue, 06 Jun 2023 18:02:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1686099731; x=1688691731; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=Ppsx8Ceq66P31QklC+vqilKr6uT5OJgGHpP85vCiA6Y=; b=60F2xJuBCyVXi/iBprpW3GuxweYIVitbrvYdm3N96FsZqqFZ2ro1VTYWQECv2oLH9T CI2gz2e+UlSu7s1pZXNnbwYXsEm+k1euxY3C6yIvCmgmIolJD6TR5bB60JPREl2ol0gP hUNdZCWVahrHPFGvnvx5lSuPCK2zZm/XEuwkEfQ9bE2FTi6Ktk2TQUq6hJD+hEK9ICD1 BpdjfAF91eQb+bXOMKDTyqAtwYsVy7brSn5oVc8QGBuG9yLErI4FpJwMLGo6GaKFT2H7 N6Vk66Ff9rcSaU4QdOi/RBaBpfvf+XkX0h5fR2BbtqVkXmcdT/v9WsRrMgsA53jGf3bp 8hDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686099731; x=1688691731; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Ppsx8Ceq66P31QklC+vqilKr6uT5OJgGHpP85vCiA6Y=; b=LoEg/0/WmoyI+Q7LcoG/avyj04GaMwvTEcAFjH20ZUSW6zEiMBPRsdFuOgeDBsgB+a bC35jN5SQq3F3ymJi2Na5ZR8jCxwEmM3xnUJCrSvSt1xolvofPZkJaUlafbi/U9N3FYM 7Y5wmQOCKHH1M9BJCV/798WM7lkmp45A8uexWU4rl8d8d+JZybTcGGbrxSDpQiPkdcjO XwHhs29CmOQSvTOqgeKgXoD685JmSBuf8s3PKe5HKFwr/qd1PQnxcS9AaHfMUCHNv9/q BaaHiU+KkuGh4FmR7w2mo8kQJkONGuoaa32SSf+AD3btGr4iauMygeI8tsHLp6gGY94Q PN+A== X-Gm-Message-State: AC+VfDxARgsxxhk7Zdyu2t3MoilAk0tkBgNPf4AdvJmSsC9tz0zwW3Se fDcvmzI2vDTRXNlbSlBJu6znLj7CIcM= X-Google-Smtp-Source: ACHHUZ5lSKXxJyCIlFQNj+i2NLpdxteCe7UtCpTwxSQ6kftQAsIgDzwiQgT7wsKkC5cGIzPkeFP8vs8gKPI= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a25:50d3:0:b0:bb3:c4c2:5d2a with SMTP id e202-20020a2550d3000000b00bb3c4c25d2amr1201172ybb.7.1686099731265; Tue, 06 Jun 2023 18:02:11 -0700 (PDT) Reply-To: Sean Christopherson Date: Tue, 6 Jun 2023 18:02:03 -0700 In-Reply-To: <20230607010206.1425277-1-seanjc@google.com> Mime-Version: 1.0 References: <20230607010206.1425277-1-seanjc@google.com> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog Message-ID: <20230607010206.1425277-2-seanjc@google.com> Subject: [PATCH 1/4] KVM: x86/pmu: Use enums instead of hardcoded magic for arch event indices From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Aaron Lewis , Like Xu Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add "enum intel_pmu_architectural_events" to replace the magic numbers for the (pseudo-)architectural events, and to give a meaningful name to each event so that new readers don't need psychic powers to understand what the code is doing. Cc: Aaron Lewis Cc: Like Xu Signed-off-by: Sean Christopherson Reviewed-by: Like Xu --- arch/x86/kvm/vmx/pmu_intel.c | 55 ++++++++++++++++++++++++++++-------- 1 file changed, 43 insertions(+), 12 deletions(-) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 84be32d9f365..0050d71c9c01 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -22,23 +22,51 @@ =20 #define MSR_PMC_FULL_WIDTH_BIT (MSR_IA32_PMC0 - MSR_IA32_PERFCTR0) =20 +enum intel_pmu_architectural_events { + /* + * The order of the architectural events matters as support for each + * event is enumerated via CPUID using the index of the event. + */ + INTEL_ARCH_CPU_CYCLES, + INTEL_ARCH_INSTRUCTIONS_RETIRED, + INTEL_ARCH_REFERENCE_CYCLES, + INTEL_ARCH_LLC_REFERENCES, + INTEL_ARCH_LLC_MISSES, + INTEL_ARCH_BRANCHES_RETIRED, + INTEL_ARCH_BRANCHES_MISPREDICTED, + + NR_REAL_INTEL_ARCH_EVENTS, + + /* + * Pseudo-architectural event used to implement IA32_FIXED_CTR2, a.k.a. + * TSC reference cycles. The architectural reference cycles event may + * or may not actually use the TSC as the reference, e.g. might use the + * core crystal clock or the bus clock (yeah, "architectural"). + */ + PSEUDO_ARCH_REFERENCE_CYCLES =3D NR_REAL_INTEL_ARCH_EVENTS, + NR_INTEL_ARCH_EVENTS, +}; + static struct { u8 eventsel; u8 unit_mask; } const intel_arch_events[] =3D { - [0] =3D { 0x3c, 0x00 }, - [1] =3D { 0xc0, 0x00 }, - [2] =3D { 0x3c, 0x01 }, - [3] =3D { 0x2e, 0x4f }, - [4] =3D { 0x2e, 0x41 }, - [5] =3D { 0xc4, 0x00 }, - [6] =3D { 0xc5, 0x00 }, - /* The above index must match CPUID 0x0A.EBX bit vector */ - [7] =3D { 0x00, 0x03 }, + [INTEL_ARCH_CPU_CYCLES] =3D { 0x3c, 0x00 }, + [INTEL_ARCH_INSTRUCTIONS_RETIRED] =3D { 0xc0, 0x00 }, + [INTEL_ARCH_REFERENCE_CYCLES] =3D { 0x3c, 0x01 }, + [INTEL_ARCH_LLC_REFERENCES] =3D { 0x2e, 0x4f }, + [INTEL_ARCH_LLC_MISSES] =3D { 0x2e, 0x41 }, + [INTEL_ARCH_BRANCHES_RETIRED] =3D { 0xc4, 0x00 }, + [INTEL_ARCH_BRANCHES_MISPREDICTED] =3D { 0xc5, 0x00 }, + [PSEUDO_ARCH_REFERENCE_CYCLES] =3D { 0x00, 0x03 }, }; =20 /* mapping between fixed pmc index and intel_arch_events array */ -static int fixed_pmc_events[] =3D {1, 0, 7}; +static int fixed_pmc_events[] =3D { + [0] =3D INTEL_ARCH_INSTRUCTIONS_RETIRED, + [1] =3D INTEL_ARCH_CPU_CYCLES, + [2] =3D PSEUDO_ARCH_REFERENCE_CYCLES, +}; =20 static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data) { @@ -92,13 +120,16 @@ static bool intel_hw_event_available(struct kvm_pmc *p= mc) u8 unit_mask =3D (pmc->eventsel & ARCH_PERFMON_EVENTSEL_UMASK) >> 8; int i; =20 - for (i =3D 0; i < ARRAY_SIZE(intel_arch_events); i++) { + BUILD_BUG_ON(ARRAY_SIZE(intel_arch_events) !=3D NR_INTEL_ARCH_EVENTS); + + for (i =3D 0; i < NR_INTEL_ARCH_EVENTS; i++) { if (intel_arch_events[i].eventsel !=3D event_select || intel_arch_events[i].unit_mask !=3D unit_mask) continue; =20 /* disable event that reported as not present by cpuid */ - if ((i < 7) && !(pmu->available_event_types & (1 << i))) + if ((i < PSEUDO_ARCH_REFERENCE_CYCLES) && + !(pmu->available_event_types & (1 << i))) return false; =20 break; --=20 2.41.0.162.gfafddb0af9-goog From nobody Sat Feb 7 23:47:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22D2DC7EE2F for ; Wed, 7 Jun 2023 01:02:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240433AbjFGBCZ (ORCPT ); Tue, 6 Jun 2023 21:02:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240387AbjFGBCO (ORCPT ); Tue, 6 Jun 2023 21:02:14 -0400 Received: from mail-pg1-x54a.google.com (mail-pg1-x54a.google.com [IPv6:2607:f8b0:4864:20::54a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 53ABC10D5 for ; Tue, 6 Jun 2023 18:02:13 -0700 (PDT) Received: by mail-pg1-x54a.google.com with SMTP id 41be03b00d2f7-5343c1d114cso6231461a12.0 for ; Tue, 06 Jun 2023 18:02:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1686099733; x=1688691733; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=GdxTpX9Spmnpfwqe75ekBKH+Ldw87KCa0RRFcAselmo=; b=f3El6h4m5J8UNxRj4A3Eoe7PFYBiRVvCRS7XcW3t5c08Z3ub3hWjb5iqnmgk+kAqJ6 OCB9HveaWmu7txC0/3bapAUlHQAV7dnXwgqCC6ZTEpyPZEgS9yryjImgtqwNOYzHb++Q 2eX5upC9ARA+s2JKqAvyakW6S48rXgVswrhpWugfB3KHwjchSpZ4e+oKV3L1WDhfuEpn F9W82WDmGKAZg7LF1qNA2aH2i59k7UmicNdZATpGNgij8p6+t9m65K+wsLWJyveegdYP IlrmJGwMoGVPukj6ZMn9+cml7v6SBNm+ZnJ31oEyJMCF2dZHJCncUB4CpFo7Skez72MP MrQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686099733; x=1688691733; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=GdxTpX9Spmnpfwqe75ekBKH+Ldw87KCa0RRFcAselmo=; b=aECPSGy08uS5UBjEKy0HCH6xkn4mII6U90iQCDTEetqVx8qD88caBWbIBU5ATQCQCD wThneuSC0NjqrzAes671WVEvpPzhMmQLYmggboQYti/fx8rBDZh8XN9bM1XIplV1AfAS 7xFnAe9rjxEkTKd+hNuI80Pf6XxW1xD2k8dvjfauQlv5JDby9egMXRmyci0DBinRioGV PRrqD4LEolVNspC2u4zh9RTQfH3j1qAAVLoNYQrWGvLsOsN4E3hGZrI1sBrrF+spbBB6 iSwWox0AcLOawVofv1Xeb9ihmNN8kLANaLWHR++wpHrTj4Yj32FBQvTg1lk5sFaH5PbR wfNQ== X-Gm-Message-State: AC+VfDxCgX8rJYFJoiJqiqQ6AemJM7wJ+LLYIXw7ik2X9zXJ3azxTPgq JD5mwRBML0slUwdLJPtaVp4/Z+sqjsg= X-Google-Smtp-Source: ACHHUZ4oC1kUgVxWFiIo/95OlQu9U0TYB1bjBRCbryG3OehS1nQ1msVcE1xkdm7mCLPE3mpSxP/Qos6YgK8= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a65:68c6:0:b0:528:c2cd:9b42 with SMTP id k6-20020a6568c6000000b00528c2cd9b42mr761868pgt.3.1686099732871; Tue, 06 Jun 2023 18:02:12 -0700 (PDT) Reply-To: Sean Christopherson Date: Tue, 6 Jun 2023 18:02:04 -0700 In-Reply-To: <20230607010206.1425277-1-seanjc@google.com> Mime-Version: 1.0 References: <20230607010206.1425277-1-seanjc@google.com> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog Message-ID: <20230607010206.1425277-3-seanjc@google.com> Subject: [PATCH 2/4] KVM: x86/pmu: Simplify intel_hw_event_available() From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Aaron Lewis , Like Xu Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Walk only the "real", i.e. non-pseudo, architectural events when checking if a hardware event is available, i.e. isn't disabled by guest CPUID. Skipping pseudo-arch events in the loop body is unnecessarily convoluted, especially now that KVM has enums that delineate between real and pseudo events. Signed-off-by: Sean Christopherson --- arch/x86/kvm/vmx/pmu_intel.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 0050d71c9c01..f281e634af3c 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -122,17 +122,16 @@ static bool intel_hw_event_available(struct kvm_pmc *= pmc) =20 BUILD_BUG_ON(ARRAY_SIZE(intel_arch_events) !=3D NR_INTEL_ARCH_EVENTS); =20 - for (i =3D 0; i < NR_INTEL_ARCH_EVENTS; i++) { + /* + * Disallow events reported as unavailable in guest CPUID. Note, this + * doesn't apply to pseudo-architectural events. + */ + for (i =3D 0; i < NR_REAL_INTEL_ARCH_EVENTS; i++) { if (intel_arch_events[i].eventsel !=3D event_select || intel_arch_events[i].unit_mask !=3D unit_mask) continue; =20 - /* disable event that reported as not present by cpuid */ - if ((i < PSEUDO_ARCH_REFERENCE_CYCLES) && - !(pmu->available_event_types & (1 << i))) - return false; - - break; + return pmu->available_event_types & BIT(i); } =20 return true; --=20 2.41.0.162.gfafddb0af9-goog From nobody Sat Feb 7 23:47:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFD2EC7EE2F for ; Wed, 7 Jun 2023 01:02:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240440AbjFGBC3 (ORCPT ); Tue, 6 Jun 2023 21:02:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53652 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240401AbjFGBCR (ORCPT ); Tue, 6 Jun 2023 21:02:17 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B824F1712 for ; Tue, 6 Jun 2023 18:02:15 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-bb2fae9b286so4669091276.3 for ; Tue, 06 Jun 2023 18:02:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1686099735; x=1688691735; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=/p3hE18mmnljLb7fbFnVkkn8QwKXTaT5e9jEQlBWXcU=; b=6UvT6b0pBC2I3ReD74BskUKqwcHxT2DPwtJz6h4dQIf0lHIvZSKhTS2z6XHo0m2YyQ dyyCZPMTIaqqpphsP6+05vRW/aDN6KreYQqGeaaZWyXjMzJUD60PPE0HtOuAuZjtOHMu Oz+BBNEuK99s7gfi6PJtXvYxpHyEpOiYFxX+/yJI+S3tLnIoesOR7gyw8m4ynEGveJzT SDnYH7M+8WW2xoCXwUP1RnvMVPRCKHzj1ZNFKfxS2wp2nz7Ui38bmNTLEX2S2iKr5L45 Wb2+GpSmRSs1WwOAyl3F0INfi5pydWmUHlJRxYt6nOm1gQqIOSFij9xPXiJ3UssrOsEz RiNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686099735; x=1688691735; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=/p3hE18mmnljLb7fbFnVkkn8QwKXTaT5e9jEQlBWXcU=; b=TKmul+SGiTfMIUavBzh1Gw3oR5r5TehlRZcODkZf4IXQUNZ3eBecIc2n32HhBbhsKK op3+wggnvb6cuxS284euMF5cNIWiyOWm8aqWUT28AIO2o/RnvBSn+nrlRLdVzvaM3OMw dZuM8Y8Jq01JoLM2/is7W4g4Rfax2kZwlLW8cJn2XR5hn2EOIIF6WAmw0Z6q1LWWVX5I R/tNN21EbmQpAfJnAEwDV3LwuvsnP/YE33v+wa4agUyG1yJrXyt/DcLiZaDH72umCQsJ tyuSDcbHf7tomFSXqbvyV4cfoq+B6XyFpAfJXuJeht5fQVAVswZl3BUfkb4lWGXukLmA NCVg== X-Gm-Message-State: AC+VfDzRVMEXk6AuKL1Npc4R+SIYZ6MmA0PyEC602/pfSdiUO533Er1M oahioZVlsFVPUITeD2apOp1medE/5xg= X-Google-Smtp-Source: ACHHUZ66ZN18TSVUSFfTJ9KYMFh531G+fYQnxCFRROXfI3t6AlHX78mEuOWXgZ1KtH0TDjdOM2NxAZyogNQ= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a25:4117:0:b0:ba8:9653:c948 with SMTP id o23-20020a254117000000b00ba89653c948mr1341420yba.3.1686099734922; Tue, 06 Jun 2023 18:02:14 -0700 (PDT) Reply-To: Sean Christopherson Date: Tue, 6 Jun 2023 18:02:05 -0700 In-Reply-To: <20230607010206.1425277-1-seanjc@google.com> Mime-Version: 1.0 References: <20230607010206.1425277-1-seanjc@google.com> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog Message-ID: <20230607010206.1425277-4-seanjc@google.com> Subject: [PATCH 3/4] KVM: x86/pmu: Require nr fixed_pmc_events to match nr max fixed counters From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Aaron Lewis , Like Xu Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Assert that the number of known fixed_pmc_events matches the max number of fixed counters supported by KVM, and clean up related code. Opportunistically extend setup_fixed_pmc_eventsel()'s use of array_index_nospec() to cover fixed_counters, as nr_arch_fixed_counters is set based on userspace input (but capped using KVM-controlled values). Signed-off-by: Sean Christopherson --- arch/x86/kvm/vmx/pmu_intel.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index f281e634af3c..c0b0a721b97f 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -527,16 +527,17 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, s= truct msr_data *msr_info) =20 static void setup_fixed_pmc_eventsel(struct kvm_pmu *pmu) { - size_t size =3D ARRAY_SIZE(fixed_pmc_events); - struct kvm_pmc *pmc; - u32 event; int i; =20 + BUILD_BUG_ON(ARRAY_SIZE(fixed_pmc_events) !=3D KVM_PMC_MAX_FIXED); + for (i =3D 0; i < pmu->nr_arch_fixed_counters; i++) { - pmc =3D &pmu->fixed_counters[i]; - event =3D fixed_pmc_events[array_index_nospec(i, size)]; + int index =3D array_index_nospec(i, KVM_PMC_MAX_FIXED); + struct kvm_pmc *pmc =3D &pmu->fixed_counters[index]; + u32 event =3D fixed_pmc_events[index]; + pmc->eventsel =3D (intel_arch_events[event].unit_mask << 8) | - intel_arch_events[event].eventsel; + intel_arch_events[event].eventsel; } } =20 @@ -597,10 +598,8 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) if (pmu->version =3D=3D 1) { pmu->nr_arch_fixed_counters =3D 0; } else { - pmu->nr_arch_fixed_counters =3D - min3(ARRAY_SIZE(fixed_pmc_events), - (size_t) edx.split.num_counters_fixed, - (size_t)kvm_pmu_cap.num_counters_fixed); + pmu->nr_arch_fixed_counters =3D min_t(int, edx.split.num_counters_fixed, + kvm_pmu_cap.num_counters_fixed); edx.split.bit_width_fixed =3D min_t(int, edx.split.bit_width_fixed, kvm_pmu_cap.bit_width_fixed); pmu->counter_bitmask[KVM_PMC_FIXED] =3D --=20 2.41.0.162.gfafddb0af9-goog From nobody Sat Feb 7 23:47:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16C82C7EE2F for ; Wed, 7 Jun 2023 01:02:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240455AbjFGBCf (ORCPT ); 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Tue, 06 Jun 2023 18:02:16 -0700 (PDT) Reply-To: Sean Christopherson Date: Tue, 6 Jun 2023 18:02:06 -0700 In-Reply-To: <20230607010206.1425277-1-seanjc@google.com> Mime-Version: 1.0 References: <20230607010206.1425277-1-seanjc@google.com> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog Message-ID: <20230607010206.1425277-5-seanjc@google.com> Subject: [PATCH 4/4] KVM: x86/pmu: Move .hw_event_available() check out of PMC filter helper From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Aaron Lewis , Like Xu Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move the call to kvm_x86_pmu.hw_event_available(), which has nothing to with the userspace PMU filter, out of check_pmu_event_filter() and into its sole caller pmc_event_is_allowed(). pmc_event_is_allowed() didn't exist when commit 7aadaa988c5e ("KVM: x86/pmu: Drop amd_event_mapping[] in the KVM context"), so presumably the motivation for invoking .hw_event_available() from check_pmu_event_filter() was to avoid having to add multiple call sites. Signed-off-by: Sean Christopherson --- arch/x86/kvm/pmu.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 1690d41c1830..2a32dc6aa3f7 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -387,9 +387,6 @@ static bool check_pmu_event_filter(struct kvm_pmc *pmc) struct kvm_x86_pmu_event_filter *filter; struct kvm *kvm =3D pmc->vcpu->kvm; =20 - if (!static_call(kvm_x86_pmu_hw_event_available)(pmc)) - return false; - filter =3D srcu_dereference(kvm->arch.pmu_event_filter, &kvm->srcu); if (!filter) return true; @@ -403,6 +400,7 @@ static bool check_pmu_event_filter(struct kvm_pmc *pmc) static bool pmc_event_is_allowed(struct kvm_pmc *pmc) { return pmc_is_globally_enabled(pmc) && pmc_speculative_in_use(pmc) && + static_call(kvm_x86_pmu_hw_event_available)(pmc) && check_pmu_event_filter(pmc); } =20 --=20 2.41.0.162.gfafddb0af9-goog