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Mon, 12 Jun 2023 02:57:40 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id f25-20020a7bcd19000000b003f7ff520a14sm10829525wmj.22.2023.06.12.02.57.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jun 2023 02:57:40 -0700 (PDT) From: Neil Armstrong Date: Mon, 12 Jun 2023 11:57:23 +0200 Subject: [PATCH v2 06/19] clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKS MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230607-topic-amlogic-upstream-clkid-public-migration-v2-6-38172d17c27a@linaro.org> References: <20230607-topic-amlogic-upstream-clkid-public-migration-v2-0-38172d17c27a@linaro.org> In-Reply-To: <20230607-topic-amlogic-upstream-clkid-public-migration-v2-0-38172d17c27a@linaro.org> To: Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The way hw_onecell_data is declared: struct clk_hw_onecell_data { unsigned int num; struct clk_hw *hws[]; }; makes it impossible to have the clk_hw table declared outside while using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible array member. Completely move out of hw_onecell_data and add a custom devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw in order to finally get rid on the NR_CLKS define. Signed-off-by: Neil Armstrong --- drivers/clk/meson/Kconfig | 1 + drivers/clk/meson/axg-audio.c | 849 +++++++++++++++++++++-----------------= ---- drivers/clk/meson/axg-audio.h | 2 - 3 files changed, 424 insertions(+), 428 deletions(-) diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index ea88309c9582..135da8f2d0b1 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -100,6 +100,7 @@ config COMMON_CLK_AXG_AUDIO select COMMON_CLK_MESON_REGMAP select COMMON_CLK_MESON_PHASE select COMMON_CLK_MESON_SCLK_DIV + select COMMON_CLK_MESON_CLKC_UTILS select REGMAP_MMIO help Support for the audio clock controller on AmLogic A113D devices, diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c index 5016682e47c8..6917e35232b6 100644 --- a/drivers/clk/meson/axg-audio.c +++ b/drivers/clk/meson/axg-audio.c @@ -15,6 +15,7 @@ #include #include =20 +#include "meson-clkc-utils.h" #include "axg-audio.h" #include "clk-regmap.h" #include "clk-phase.h" @@ -811,436 +812,424 @@ static struct clk_regmap sm1_tdm_sclk_pad_2 =3D AUD= _TDM_PAD_CTRL( * Array of all clocks provided by this provider * The input clocks of the controller will be populated at runtime */ -static struct clk_hw_onecell_data axg_audio_hw_onecell_data =3D { - .hws =3D { - [AUD_CLKID_DDR_ARB] =3D &ddr_arb.hw, - [AUD_CLKID_PDM] =3D &pdm.hw, - [AUD_CLKID_TDMIN_A] =3D &tdmin_a.hw, - [AUD_CLKID_TDMIN_B] =3D &tdmin_b.hw, - [AUD_CLKID_TDMIN_C] =3D &tdmin_c.hw, - [AUD_CLKID_TDMIN_LB] =3D &tdmin_lb.hw, - [AUD_CLKID_TDMOUT_A] =3D &tdmout_a.hw, - [AUD_CLKID_TDMOUT_B] =3D &tdmout_b.hw, - [AUD_CLKID_TDMOUT_C] =3D &tdmout_c.hw, - [AUD_CLKID_FRDDR_A] =3D &frddr_a.hw, - [AUD_CLKID_FRDDR_B] =3D &frddr_b.hw, - [AUD_CLKID_FRDDR_C] =3D &frddr_c.hw, - [AUD_CLKID_TODDR_A] =3D &toddr_a.hw, - [AUD_CLKID_TODDR_B] =3D &toddr_b.hw, - [AUD_CLKID_TODDR_C] =3D &toddr_c.hw, - [AUD_CLKID_LOOPBACK] =3D &loopback.hw, - [AUD_CLKID_SPDIFIN] =3D &spdifin.hw, - [AUD_CLKID_SPDIFOUT] =3D &spdifout.hw, - [AUD_CLKID_RESAMPLE] =3D &resample.hw, - [AUD_CLKID_POWER_DETECT] =3D &power_detect.hw, - [AUD_CLKID_MST_A_MCLK_SEL] =3D &mst_a_mclk_sel.hw, - [AUD_CLKID_MST_B_MCLK_SEL] =3D &mst_b_mclk_sel.hw, - [AUD_CLKID_MST_C_MCLK_SEL] =3D &mst_c_mclk_sel.hw, - [AUD_CLKID_MST_D_MCLK_SEL] =3D &mst_d_mclk_sel.hw, - [AUD_CLKID_MST_E_MCLK_SEL] =3D &mst_e_mclk_sel.hw, - [AUD_CLKID_MST_F_MCLK_SEL] =3D &mst_f_mclk_sel.hw, - [AUD_CLKID_MST_A_MCLK_DIV] =3D &mst_a_mclk_div.hw, - [AUD_CLKID_MST_B_MCLK_DIV] =3D &mst_b_mclk_div.hw, - [AUD_CLKID_MST_C_MCLK_DIV] =3D &mst_c_mclk_div.hw, - [AUD_CLKID_MST_D_MCLK_DIV] =3D &mst_d_mclk_div.hw, - [AUD_CLKID_MST_E_MCLK_DIV] =3D &mst_e_mclk_div.hw, - [AUD_CLKID_MST_F_MCLK_DIV] =3D &mst_f_mclk_div.hw, - [AUD_CLKID_MST_A_MCLK] =3D &mst_a_mclk.hw, - [AUD_CLKID_MST_B_MCLK] =3D &mst_b_mclk.hw, - [AUD_CLKID_MST_C_MCLK] =3D &mst_c_mclk.hw, - [AUD_CLKID_MST_D_MCLK] =3D &mst_d_mclk.hw, - [AUD_CLKID_MST_E_MCLK] =3D &mst_e_mclk.hw, - [AUD_CLKID_MST_F_MCLK] =3D &mst_f_mclk.hw, - [AUD_CLKID_SPDIFOUT_CLK_SEL] =3D &spdifout_clk_sel.hw, - [AUD_CLKID_SPDIFOUT_CLK_DIV] =3D &spdifout_clk_div.hw, - [AUD_CLKID_SPDIFOUT_CLK] =3D &spdifout_clk.hw, - [AUD_CLKID_SPDIFIN_CLK_SEL] =3D &spdifin_clk_sel.hw, - [AUD_CLKID_SPDIFIN_CLK_DIV] =3D &spdifin_clk_div.hw, - [AUD_CLKID_SPDIFIN_CLK] =3D &spdifin_clk.hw, - [AUD_CLKID_PDM_DCLK_SEL] =3D &pdm_dclk_sel.hw, - [AUD_CLKID_PDM_DCLK_DIV] =3D &pdm_dclk_div.hw, - [AUD_CLKID_PDM_DCLK] =3D &pdm_dclk.hw, - [AUD_CLKID_PDM_SYSCLK_SEL] =3D &pdm_sysclk_sel.hw, - [AUD_CLKID_PDM_SYSCLK_DIV] =3D &pdm_sysclk_div.hw, - [AUD_CLKID_PDM_SYSCLK] =3D &pdm_sysclk.hw, - [AUD_CLKID_MST_A_SCLK_PRE_EN] =3D &mst_a_sclk_pre_en.hw, - [AUD_CLKID_MST_B_SCLK_PRE_EN] =3D &mst_b_sclk_pre_en.hw, - [AUD_CLKID_MST_C_SCLK_PRE_EN] =3D &mst_c_sclk_pre_en.hw, - [AUD_CLKID_MST_D_SCLK_PRE_EN] =3D &mst_d_sclk_pre_en.hw, - [AUD_CLKID_MST_E_SCLK_PRE_EN] =3D &mst_e_sclk_pre_en.hw, - [AUD_CLKID_MST_F_SCLK_PRE_EN] =3D &mst_f_sclk_pre_en.hw, - [AUD_CLKID_MST_A_SCLK_DIV] =3D &mst_a_sclk_div.hw, - [AUD_CLKID_MST_B_SCLK_DIV] =3D &mst_b_sclk_div.hw, - [AUD_CLKID_MST_C_SCLK_DIV] =3D &mst_c_sclk_div.hw, - [AUD_CLKID_MST_D_SCLK_DIV] =3D &mst_d_sclk_div.hw, - [AUD_CLKID_MST_E_SCLK_DIV] =3D &mst_e_sclk_div.hw, - [AUD_CLKID_MST_F_SCLK_DIV] =3D &mst_f_sclk_div.hw, - [AUD_CLKID_MST_A_SCLK_POST_EN] =3D &mst_a_sclk_post_en.hw, - [AUD_CLKID_MST_B_SCLK_POST_EN] =3D &mst_b_sclk_post_en.hw, - [AUD_CLKID_MST_C_SCLK_POST_EN] =3D &mst_c_sclk_post_en.hw, - [AUD_CLKID_MST_D_SCLK_POST_EN] =3D &mst_d_sclk_post_en.hw, - [AUD_CLKID_MST_E_SCLK_POST_EN] =3D &mst_e_sclk_post_en.hw, - [AUD_CLKID_MST_F_SCLK_POST_EN] =3D &mst_f_sclk_post_en.hw, - [AUD_CLKID_MST_A_SCLK] =3D &mst_a_sclk.hw, - [AUD_CLKID_MST_B_SCLK] =3D &mst_b_sclk.hw, - [AUD_CLKID_MST_C_SCLK] =3D &mst_c_sclk.hw, - [AUD_CLKID_MST_D_SCLK] =3D &mst_d_sclk.hw, - [AUD_CLKID_MST_E_SCLK] =3D &mst_e_sclk.hw, - [AUD_CLKID_MST_F_SCLK] =3D &mst_f_sclk.hw, - [AUD_CLKID_MST_A_LRCLK_DIV] =3D &mst_a_lrclk_div.hw, - [AUD_CLKID_MST_B_LRCLK_DIV] =3D &mst_b_lrclk_div.hw, - [AUD_CLKID_MST_C_LRCLK_DIV] =3D &mst_c_lrclk_div.hw, - [AUD_CLKID_MST_D_LRCLK_DIV] =3D &mst_d_lrclk_div.hw, - [AUD_CLKID_MST_E_LRCLK_DIV] =3D &mst_e_lrclk_div.hw, - [AUD_CLKID_MST_F_LRCLK_DIV] =3D &mst_f_lrclk_div.hw, - [AUD_CLKID_MST_A_LRCLK] =3D &mst_a_lrclk.hw, - [AUD_CLKID_MST_B_LRCLK] =3D &mst_b_lrclk.hw, - [AUD_CLKID_MST_C_LRCLK] =3D &mst_c_lrclk.hw, - [AUD_CLKID_MST_D_LRCLK] =3D &mst_d_lrclk.hw, - [AUD_CLKID_MST_E_LRCLK] =3D &mst_e_lrclk.hw, - [AUD_CLKID_MST_F_LRCLK] =3D &mst_f_lrclk.hw, - [AUD_CLKID_TDMIN_A_SCLK_SEL] =3D &tdmin_a_sclk_sel.hw, - [AUD_CLKID_TDMIN_B_SCLK_SEL] =3D &tdmin_b_sclk_sel.hw, - [AUD_CLKID_TDMIN_C_SCLK_SEL] =3D &tdmin_c_sclk_sel.hw, - [AUD_CLKID_TDMIN_LB_SCLK_SEL] =3D &tdmin_lb_sclk_sel.hw, - [AUD_CLKID_TDMOUT_A_SCLK_SEL] =3D &tdmout_a_sclk_sel.hw, - [AUD_CLKID_TDMOUT_B_SCLK_SEL] =3D &tdmout_b_sclk_sel.hw, - [AUD_CLKID_TDMOUT_C_SCLK_SEL] =3D &tdmout_c_sclk_sel.hw, - [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] =3D &tdmin_a_sclk_pre_en.hw, - [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] =3D &tdmin_b_sclk_pre_en.hw, - [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] =3D &tdmin_c_sclk_pre_en.hw, - [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] =3D &tdmin_lb_sclk_pre_en.hw, - [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] =3D &tdmout_a_sclk_pre_en.hw, - [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] =3D &tdmout_b_sclk_pre_en.hw, - [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] =3D &tdmout_c_sclk_pre_en.hw, - [AUD_CLKID_TDMIN_A_SCLK_POST_EN] =3D &tdmin_a_sclk_post_en.hw, - [AUD_CLKID_TDMIN_B_SCLK_POST_EN] =3D &tdmin_b_sclk_post_en.hw, - [AUD_CLKID_TDMIN_C_SCLK_POST_EN] =3D &tdmin_c_sclk_post_en.hw, - [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] =3D &tdmin_lb_sclk_post_en.hw, - [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] =3D &tdmout_a_sclk_post_en.hw, - [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] =3D &tdmout_b_sclk_post_en.hw, - [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] =3D &tdmout_c_sclk_post_en.hw, - [AUD_CLKID_TDMIN_A_SCLK] =3D &tdmin_a_sclk.hw, - [AUD_CLKID_TDMIN_B_SCLK] =3D &tdmin_b_sclk.hw, - [AUD_CLKID_TDMIN_C_SCLK] =3D &tdmin_c_sclk.hw, - [AUD_CLKID_TDMIN_LB_SCLK] =3D &tdmin_lb_sclk.hw, - [AUD_CLKID_TDMOUT_A_SCLK] =3D &axg_tdmout_a_sclk.hw, - [AUD_CLKID_TDMOUT_B_SCLK] =3D &axg_tdmout_b_sclk.hw, - [AUD_CLKID_TDMOUT_C_SCLK] =3D &axg_tdmout_c_sclk.hw, - [AUD_CLKID_TDMIN_A_LRCLK] =3D &tdmin_a_lrclk.hw, - [AUD_CLKID_TDMIN_B_LRCLK] =3D &tdmin_b_lrclk.hw, - [AUD_CLKID_TDMIN_C_LRCLK] =3D &tdmin_c_lrclk.hw, - [AUD_CLKID_TDMIN_LB_LRCLK] =3D &tdmin_lb_lrclk.hw, - [AUD_CLKID_TDMOUT_A_LRCLK] =3D &tdmout_a_lrclk.hw, - [AUD_CLKID_TDMOUT_B_LRCLK] =3D &tdmout_b_lrclk.hw, - [AUD_CLKID_TDMOUT_C_LRCLK] =3D &tdmout_c_lrclk.hw, - [AUD_CLKID_TOP] =3D &axg_aud_top, - [NR_CLKS] =3D NULL, - }, - .num =3D NR_CLKS, +static struct clk_hw *axg_audio_hw_clks[] =3D { + [AUD_CLKID_DDR_ARB] =3D &ddr_arb.hw, + [AUD_CLKID_PDM] =3D &pdm.hw, + [AUD_CLKID_TDMIN_A] =3D &tdmin_a.hw, + [AUD_CLKID_TDMIN_B] =3D &tdmin_b.hw, + [AUD_CLKID_TDMIN_C] =3D &tdmin_c.hw, + [AUD_CLKID_TDMIN_LB] =3D &tdmin_lb.hw, + [AUD_CLKID_TDMOUT_A] =3D &tdmout_a.hw, + [AUD_CLKID_TDMOUT_B] =3D &tdmout_b.hw, + [AUD_CLKID_TDMOUT_C] =3D &tdmout_c.hw, + [AUD_CLKID_FRDDR_A] =3D &frddr_a.hw, + [AUD_CLKID_FRDDR_B] =3D &frddr_b.hw, + [AUD_CLKID_FRDDR_C] =3D &frddr_c.hw, + [AUD_CLKID_TODDR_A] =3D &toddr_a.hw, + [AUD_CLKID_TODDR_B] =3D &toddr_b.hw, + [AUD_CLKID_TODDR_C] =3D &toddr_c.hw, + [AUD_CLKID_LOOPBACK] =3D &loopback.hw, + [AUD_CLKID_SPDIFIN] =3D &spdifin.hw, + [AUD_CLKID_SPDIFOUT] =3D &spdifout.hw, + [AUD_CLKID_RESAMPLE] =3D &resample.hw, + [AUD_CLKID_POWER_DETECT] =3D &power_detect.hw, + [AUD_CLKID_MST_A_MCLK_SEL] =3D &mst_a_mclk_sel.hw, + [AUD_CLKID_MST_B_MCLK_SEL] =3D &mst_b_mclk_sel.hw, + [AUD_CLKID_MST_C_MCLK_SEL] =3D &mst_c_mclk_sel.hw, + [AUD_CLKID_MST_D_MCLK_SEL] =3D &mst_d_mclk_sel.hw, + [AUD_CLKID_MST_E_MCLK_SEL] =3D &mst_e_mclk_sel.hw, + [AUD_CLKID_MST_F_MCLK_SEL] =3D &mst_f_mclk_sel.hw, + [AUD_CLKID_MST_A_MCLK_DIV] =3D &mst_a_mclk_div.hw, + [AUD_CLKID_MST_B_MCLK_DIV] =3D &mst_b_mclk_div.hw, + [AUD_CLKID_MST_C_MCLK_DIV] =3D &mst_c_mclk_div.hw, + [AUD_CLKID_MST_D_MCLK_DIV] =3D &mst_d_mclk_div.hw, + [AUD_CLKID_MST_E_MCLK_DIV] =3D &mst_e_mclk_div.hw, + [AUD_CLKID_MST_F_MCLK_DIV] =3D &mst_f_mclk_div.hw, + [AUD_CLKID_MST_A_MCLK] =3D &mst_a_mclk.hw, + [AUD_CLKID_MST_B_MCLK] =3D &mst_b_mclk.hw, + [AUD_CLKID_MST_C_MCLK] =3D &mst_c_mclk.hw, + [AUD_CLKID_MST_D_MCLK] =3D &mst_d_mclk.hw, + [AUD_CLKID_MST_E_MCLK] =3D &mst_e_mclk.hw, + [AUD_CLKID_MST_F_MCLK] =3D &mst_f_mclk.hw, + [AUD_CLKID_SPDIFOUT_CLK_SEL] =3D &spdifout_clk_sel.hw, + [AUD_CLKID_SPDIFOUT_CLK_DIV] =3D &spdifout_clk_div.hw, + [AUD_CLKID_SPDIFOUT_CLK] =3D &spdifout_clk.hw, + [AUD_CLKID_SPDIFIN_CLK_SEL] =3D &spdifin_clk_sel.hw, + [AUD_CLKID_SPDIFIN_CLK_DIV] =3D &spdifin_clk_div.hw, + [AUD_CLKID_SPDIFIN_CLK] =3D &spdifin_clk.hw, + [AUD_CLKID_PDM_DCLK_SEL] =3D &pdm_dclk_sel.hw, + [AUD_CLKID_PDM_DCLK_DIV] =3D &pdm_dclk_div.hw, + [AUD_CLKID_PDM_DCLK] =3D &pdm_dclk.hw, + [AUD_CLKID_PDM_SYSCLK_SEL] =3D &pdm_sysclk_sel.hw, + [AUD_CLKID_PDM_SYSCLK_DIV] =3D &pdm_sysclk_div.hw, + [AUD_CLKID_PDM_SYSCLK] =3D &pdm_sysclk.hw, + [AUD_CLKID_MST_A_SCLK_PRE_EN] =3D &mst_a_sclk_pre_en.hw, + [AUD_CLKID_MST_B_SCLK_PRE_EN] =3D &mst_b_sclk_pre_en.hw, + [AUD_CLKID_MST_C_SCLK_PRE_EN] =3D &mst_c_sclk_pre_en.hw, + [AUD_CLKID_MST_D_SCLK_PRE_EN] =3D &mst_d_sclk_pre_en.hw, + [AUD_CLKID_MST_E_SCLK_PRE_EN] =3D &mst_e_sclk_pre_en.hw, + [AUD_CLKID_MST_F_SCLK_PRE_EN] =3D &mst_f_sclk_pre_en.hw, + [AUD_CLKID_MST_A_SCLK_DIV] =3D &mst_a_sclk_div.hw, + [AUD_CLKID_MST_B_SCLK_DIV] =3D &mst_b_sclk_div.hw, + [AUD_CLKID_MST_C_SCLK_DIV] =3D &mst_c_sclk_div.hw, + [AUD_CLKID_MST_D_SCLK_DIV] =3D &mst_d_sclk_div.hw, + [AUD_CLKID_MST_E_SCLK_DIV] =3D &mst_e_sclk_div.hw, + [AUD_CLKID_MST_F_SCLK_DIV] =3D &mst_f_sclk_div.hw, + [AUD_CLKID_MST_A_SCLK_POST_EN] =3D &mst_a_sclk_post_en.hw, + [AUD_CLKID_MST_B_SCLK_POST_EN] =3D &mst_b_sclk_post_en.hw, + [AUD_CLKID_MST_C_SCLK_POST_EN] =3D &mst_c_sclk_post_en.hw, + [AUD_CLKID_MST_D_SCLK_POST_EN] =3D &mst_d_sclk_post_en.hw, + [AUD_CLKID_MST_E_SCLK_POST_EN] =3D &mst_e_sclk_post_en.hw, + [AUD_CLKID_MST_F_SCLK_POST_EN] =3D &mst_f_sclk_post_en.hw, + [AUD_CLKID_MST_A_SCLK] =3D &mst_a_sclk.hw, + [AUD_CLKID_MST_B_SCLK] =3D &mst_b_sclk.hw, + [AUD_CLKID_MST_C_SCLK] =3D &mst_c_sclk.hw, + [AUD_CLKID_MST_D_SCLK] =3D &mst_d_sclk.hw, + [AUD_CLKID_MST_E_SCLK] =3D &mst_e_sclk.hw, + [AUD_CLKID_MST_F_SCLK] =3D &mst_f_sclk.hw, + [AUD_CLKID_MST_A_LRCLK_DIV] =3D &mst_a_lrclk_div.hw, + [AUD_CLKID_MST_B_LRCLK_DIV] =3D &mst_b_lrclk_div.hw, + [AUD_CLKID_MST_C_LRCLK_DIV] =3D &mst_c_lrclk_div.hw, + [AUD_CLKID_MST_D_LRCLK_DIV] =3D &mst_d_lrclk_div.hw, + [AUD_CLKID_MST_E_LRCLK_DIV] =3D &mst_e_lrclk_div.hw, + [AUD_CLKID_MST_F_LRCLK_DIV] =3D &mst_f_lrclk_div.hw, + [AUD_CLKID_MST_A_LRCLK] =3D &mst_a_lrclk.hw, + [AUD_CLKID_MST_B_LRCLK] =3D &mst_b_lrclk.hw, + [AUD_CLKID_MST_C_LRCLK] =3D &mst_c_lrclk.hw, + [AUD_CLKID_MST_D_LRCLK] =3D &mst_d_lrclk.hw, + [AUD_CLKID_MST_E_LRCLK] =3D &mst_e_lrclk.hw, + [AUD_CLKID_MST_F_LRCLK] =3D &mst_f_lrclk.hw, + [AUD_CLKID_TDMIN_A_SCLK_SEL] =3D &tdmin_a_sclk_sel.hw, + [AUD_CLKID_TDMIN_B_SCLK_SEL] =3D &tdmin_b_sclk_sel.hw, + [AUD_CLKID_TDMIN_C_SCLK_SEL] =3D &tdmin_c_sclk_sel.hw, + [AUD_CLKID_TDMIN_LB_SCLK_SEL] =3D &tdmin_lb_sclk_sel.hw, + [AUD_CLKID_TDMOUT_A_SCLK_SEL] =3D &tdmout_a_sclk_sel.hw, + [AUD_CLKID_TDMOUT_B_SCLK_SEL] =3D &tdmout_b_sclk_sel.hw, + [AUD_CLKID_TDMOUT_C_SCLK_SEL] =3D &tdmout_c_sclk_sel.hw, + [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] =3D &tdmin_a_sclk_pre_en.hw, + [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] =3D &tdmin_b_sclk_pre_en.hw, + [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] =3D &tdmin_c_sclk_pre_en.hw, + [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] =3D &tdmin_lb_sclk_pre_en.hw, + [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] =3D &tdmout_a_sclk_pre_en.hw, + [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] =3D &tdmout_b_sclk_pre_en.hw, + [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] =3D &tdmout_c_sclk_pre_en.hw, + [AUD_CLKID_TDMIN_A_SCLK_POST_EN] =3D &tdmin_a_sclk_post_en.hw, + [AUD_CLKID_TDMIN_B_SCLK_POST_EN] =3D &tdmin_b_sclk_post_en.hw, + [AUD_CLKID_TDMIN_C_SCLK_POST_EN] =3D &tdmin_c_sclk_post_en.hw, + [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] =3D &tdmin_lb_sclk_post_en.hw, + [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] =3D &tdmout_a_sclk_post_en.hw, + [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] =3D &tdmout_b_sclk_post_en.hw, + [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] =3D &tdmout_c_sclk_post_en.hw, + [AUD_CLKID_TDMIN_A_SCLK] =3D &tdmin_a_sclk.hw, + [AUD_CLKID_TDMIN_B_SCLK] =3D &tdmin_b_sclk.hw, + [AUD_CLKID_TDMIN_C_SCLK] =3D &tdmin_c_sclk.hw, + [AUD_CLKID_TDMIN_LB_SCLK] =3D &tdmin_lb_sclk.hw, + [AUD_CLKID_TDMOUT_A_SCLK] =3D &axg_tdmout_a_sclk.hw, + [AUD_CLKID_TDMOUT_B_SCLK] =3D &axg_tdmout_b_sclk.hw, + [AUD_CLKID_TDMOUT_C_SCLK] =3D &axg_tdmout_c_sclk.hw, + [AUD_CLKID_TDMIN_A_LRCLK] =3D &tdmin_a_lrclk.hw, + [AUD_CLKID_TDMIN_B_LRCLK] =3D &tdmin_b_lrclk.hw, + [AUD_CLKID_TDMIN_C_LRCLK] =3D &tdmin_c_lrclk.hw, + [AUD_CLKID_TDMIN_LB_LRCLK] =3D &tdmin_lb_lrclk.hw, + [AUD_CLKID_TDMOUT_A_LRCLK] =3D &tdmout_a_lrclk.hw, + [AUD_CLKID_TDMOUT_B_LRCLK] =3D &tdmout_b_lrclk.hw, + [AUD_CLKID_TDMOUT_C_LRCLK] =3D &tdmout_c_lrclk.hw, + [AUD_CLKID_TOP] =3D &axg_aud_top, }; =20 /* * Array of all G12A clocks provided by this provider * The input clocks of the controller will be populated at runtime */ -static struct clk_hw_onecell_data g12a_audio_hw_onecell_data =3D { - .hws =3D { - [AUD_CLKID_DDR_ARB] =3D &ddr_arb.hw, - [AUD_CLKID_PDM] =3D &pdm.hw, - [AUD_CLKID_TDMIN_A] =3D &tdmin_a.hw, - [AUD_CLKID_TDMIN_B] =3D &tdmin_b.hw, - [AUD_CLKID_TDMIN_C] =3D &tdmin_c.hw, - [AUD_CLKID_TDMIN_LB] =3D &tdmin_lb.hw, - [AUD_CLKID_TDMOUT_A] =3D &tdmout_a.hw, - [AUD_CLKID_TDMOUT_B] =3D &tdmout_b.hw, - [AUD_CLKID_TDMOUT_C] =3D &tdmout_c.hw, - [AUD_CLKID_FRDDR_A] =3D &frddr_a.hw, - [AUD_CLKID_FRDDR_B] =3D &frddr_b.hw, - [AUD_CLKID_FRDDR_C] =3D &frddr_c.hw, - [AUD_CLKID_TODDR_A] =3D &toddr_a.hw, - [AUD_CLKID_TODDR_B] =3D &toddr_b.hw, - [AUD_CLKID_TODDR_C] =3D &toddr_c.hw, - [AUD_CLKID_LOOPBACK] =3D &loopback.hw, - [AUD_CLKID_SPDIFIN] =3D &spdifin.hw, - [AUD_CLKID_SPDIFOUT] =3D &spdifout.hw, - [AUD_CLKID_RESAMPLE] =3D &resample.hw, - [AUD_CLKID_POWER_DETECT] =3D &power_detect.hw, - [AUD_CLKID_SPDIFOUT_B] =3D &spdifout_b.hw, - [AUD_CLKID_MST_A_MCLK_SEL] =3D &mst_a_mclk_sel.hw, - [AUD_CLKID_MST_B_MCLK_SEL] =3D &mst_b_mclk_sel.hw, - [AUD_CLKID_MST_C_MCLK_SEL] =3D &mst_c_mclk_sel.hw, - [AUD_CLKID_MST_D_MCLK_SEL] =3D &mst_d_mclk_sel.hw, - [AUD_CLKID_MST_E_MCLK_SEL] =3D &mst_e_mclk_sel.hw, - [AUD_CLKID_MST_F_MCLK_SEL] =3D &mst_f_mclk_sel.hw, - [AUD_CLKID_MST_A_MCLK_DIV] =3D &mst_a_mclk_div.hw, - [AUD_CLKID_MST_B_MCLK_DIV] =3D &mst_b_mclk_div.hw, - [AUD_CLKID_MST_C_MCLK_DIV] =3D &mst_c_mclk_div.hw, - [AUD_CLKID_MST_D_MCLK_DIV] =3D &mst_d_mclk_div.hw, - [AUD_CLKID_MST_E_MCLK_DIV] =3D &mst_e_mclk_div.hw, - [AUD_CLKID_MST_F_MCLK_DIV] =3D &mst_f_mclk_div.hw, - [AUD_CLKID_MST_A_MCLK] =3D &mst_a_mclk.hw, - [AUD_CLKID_MST_B_MCLK] =3D &mst_b_mclk.hw, - [AUD_CLKID_MST_C_MCLK] =3D &mst_c_mclk.hw, - [AUD_CLKID_MST_D_MCLK] =3D &mst_d_mclk.hw, - [AUD_CLKID_MST_E_MCLK] =3D &mst_e_mclk.hw, - [AUD_CLKID_MST_F_MCLK] =3D &mst_f_mclk.hw, - [AUD_CLKID_SPDIFOUT_CLK_SEL] =3D &spdifout_clk_sel.hw, - [AUD_CLKID_SPDIFOUT_CLK_DIV] =3D &spdifout_clk_div.hw, - [AUD_CLKID_SPDIFOUT_CLK] =3D &spdifout_clk.hw, - [AUD_CLKID_SPDIFOUT_B_CLK_SEL] =3D &spdifout_b_clk_sel.hw, - [AUD_CLKID_SPDIFOUT_B_CLK_DIV] =3D &spdifout_b_clk_div.hw, - [AUD_CLKID_SPDIFOUT_B_CLK] =3D &spdifout_b_clk.hw, - [AUD_CLKID_SPDIFIN_CLK_SEL] =3D &spdifin_clk_sel.hw, - [AUD_CLKID_SPDIFIN_CLK_DIV] =3D &spdifin_clk_div.hw, - [AUD_CLKID_SPDIFIN_CLK] =3D &spdifin_clk.hw, - [AUD_CLKID_PDM_DCLK_SEL] =3D &pdm_dclk_sel.hw, - [AUD_CLKID_PDM_DCLK_DIV] =3D &pdm_dclk_div.hw, - [AUD_CLKID_PDM_DCLK] =3D &pdm_dclk.hw, - [AUD_CLKID_PDM_SYSCLK_SEL] =3D &pdm_sysclk_sel.hw, - [AUD_CLKID_PDM_SYSCLK_DIV] =3D &pdm_sysclk_div.hw, - [AUD_CLKID_PDM_SYSCLK] =3D &pdm_sysclk.hw, - [AUD_CLKID_MST_A_SCLK_PRE_EN] =3D &mst_a_sclk_pre_en.hw, - [AUD_CLKID_MST_B_SCLK_PRE_EN] =3D &mst_b_sclk_pre_en.hw, - [AUD_CLKID_MST_C_SCLK_PRE_EN] =3D &mst_c_sclk_pre_en.hw, - [AUD_CLKID_MST_D_SCLK_PRE_EN] =3D &mst_d_sclk_pre_en.hw, - [AUD_CLKID_MST_E_SCLK_PRE_EN] =3D &mst_e_sclk_pre_en.hw, - [AUD_CLKID_MST_F_SCLK_PRE_EN] =3D &mst_f_sclk_pre_en.hw, - [AUD_CLKID_MST_A_SCLK_DIV] =3D &mst_a_sclk_div.hw, - [AUD_CLKID_MST_B_SCLK_DIV] =3D &mst_b_sclk_div.hw, - [AUD_CLKID_MST_C_SCLK_DIV] =3D &mst_c_sclk_div.hw, - [AUD_CLKID_MST_D_SCLK_DIV] =3D &mst_d_sclk_div.hw, - [AUD_CLKID_MST_E_SCLK_DIV] =3D &mst_e_sclk_div.hw, - [AUD_CLKID_MST_F_SCLK_DIV] =3D &mst_f_sclk_div.hw, - [AUD_CLKID_MST_A_SCLK_POST_EN] =3D &mst_a_sclk_post_en.hw, - [AUD_CLKID_MST_B_SCLK_POST_EN] =3D &mst_b_sclk_post_en.hw, - [AUD_CLKID_MST_C_SCLK_POST_EN] =3D &mst_c_sclk_post_en.hw, - [AUD_CLKID_MST_D_SCLK_POST_EN] =3D &mst_d_sclk_post_en.hw, - [AUD_CLKID_MST_E_SCLK_POST_EN] =3D &mst_e_sclk_post_en.hw, - [AUD_CLKID_MST_F_SCLK_POST_EN] =3D &mst_f_sclk_post_en.hw, - [AUD_CLKID_MST_A_SCLK] =3D &mst_a_sclk.hw, - [AUD_CLKID_MST_B_SCLK] =3D &mst_b_sclk.hw, - [AUD_CLKID_MST_C_SCLK] =3D &mst_c_sclk.hw, - [AUD_CLKID_MST_D_SCLK] =3D &mst_d_sclk.hw, - [AUD_CLKID_MST_E_SCLK] =3D &mst_e_sclk.hw, - [AUD_CLKID_MST_F_SCLK] =3D &mst_f_sclk.hw, - [AUD_CLKID_MST_A_LRCLK_DIV] =3D &mst_a_lrclk_div.hw, - [AUD_CLKID_MST_B_LRCLK_DIV] =3D &mst_b_lrclk_div.hw, - [AUD_CLKID_MST_C_LRCLK_DIV] =3D &mst_c_lrclk_div.hw, - [AUD_CLKID_MST_D_LRCLK_DIV] =3D &mst_d_lrclk_div.hw, - [AUD_CLKID_MST_E_LRCLK_DIV] =3D &mst_e_lrclk_div.hw, - [AUD_CLKID_MST_F_LRCLK_DIV] =3D &mst_f_lrclk_div.hw, - [AUD_CLKID_MST_A_LRCLK] =3D &mst_a_lrclk.hw, - [AUD_CLKID_MST_B_LRCLK] =3D &mst_b_lrclk.hw, - [AUD_CLKID_MST_C_LRCLK] =3D &mst_c_lrclk.hw, - [AUD_CLKID_MST_D_LRCLK] =3D &mst_d_lrclk.hw, - [AUD_CLKID_MST_E_LRCLK] =3D &mst_e_lrclk.hw, - [AUD_CLKID_MST_F_LRCLK] =3D &mst_f_lrclk.hw, - [AUD_CLKID_TDMIN_A_SCLK_SEL] =3D &tdmin_a_sclk_sel.hw, - [AUD_CLKID_TDMIN_B_SCLK_SEL] =3D &tdmin_b_sclk_sel.hw, - [AUD_CLKID_TDMIN_C_SCLK_SEL] =3D &tdmin_c_sclk_sel.hw, - [AUD_CLKID_TDMIN_LB_SCLK_SEL] =3D &tdmin_lb_sclk_sel.hw, - [AUD_CLKID_TDMOUT_A_SCLK_SEL] =3D &tdmout_a_sclk_sel.hw, - [AUD_CLKID_TDMOUT_B_SCLK_SEL] =3D &tdmout_b_sclk_sel.hw, - [AUD_CLKID_TDMOUT_C_SCLK_SEL] =3D &tdmout_c_sclk_sel.hw, - [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] =3D &tdmin_a_sclk_pre_en.hw, - [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] =3D &tdmin_b_sclk_pre_en.hw, - [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] =3D &tdmin_c_sclk_pre_en.hw, - [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] =3D &tdmin_lb_sclk_pre_en.hw, - [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] =3D &tdmout_a_sclk_pre_en.hw, - [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] =3D &tdmout_b_sclk_pre_en.hw, - [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] =3D &tdmout_c_sclk_pre_en.hw, - [AUD_CLKID_TDMIN_A_SCLK_POST_EN] =3D &tdmin_a_sclk_post_en.hw, - [AUD_CLKID_TDMIN_B_SCLK_POST_EN] =3D &tdmin_b_sclk_post_en.hw, - [AUD_CLKID_TDMIN_C_SCLK_POST_EN] =3D &tdmin_c_sclk_post_en.hw, - [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] =3D &tdmin_lb_sclk_post_en.hw, - [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] =3D &tdmout_a_sclk_post_en.hw, - [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] =3D &tdmout_b_sclk_post_en.hw, - [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] =3D &tdmout_c_sclk_post_en.hw, - [AUD_CLKID_TDMIN_A_SCLK] =3D &tdmin_a_sclk.hw, - [AUD_CLKID_TDMIN_B_SCLK] =3D &tdmin_b_sclk.hw, - [AUD_CLKID_TDMIN_C_SCLK] =3D &tdmin_c_sclk.hw, - [AUD_CLKID_TDMIN_LB_SCLK] =3D &tdmin_lb_sclk.hw, - [AUD_CLKID_TDMOUT_A_SCLK] =3D &g12a_tdmout_a_sclk.hw, - [AUD_CLKID_TDMOUT_B_SCLK] =3D &g12a_tdmout_b_sclk.hw, - [AUD_CLKID_TDMOUT_C_SCLK] =3D &g12a_tdmout_c_sclk.hw, - [AUD_CLKID_TDMIN_A_LRCLK] =3D &tdmin_a_lrclk.hw, - [AUD_CLKID_TDMIN_B_LRCLK] =3D &tdmin_b_lrclk.hw, - [AUD_CLKID_TDMIN_C_LRCLK] =3D &tdmin_c_lrclk.hw, - [AUD_CLKID_TDMIN_LB_LRCLK] =3D &tdmin_lb_lrclk.hw, - [AUD_CLKID_TDMOUT_A_LRCLK] =3D &tdmout_a_lrclk.hw, - [AUD_CLKID_TDMOUT_B_LRCLK] =3D &tdmout_b_lrclk.hw, - [AUD_CLKID_TDMOUT_C_LRCLK] =3D &tdmout_c_lrclk.hw, - [AUD_CLKID_TDM_MCLK_PAD0] =3D &g12a_tdm_mclk_pad_0.hw, - [AUD_CLKID_TDM_MCLK_PAD1] =3D &g12a_tdm_mclk_pad_1.hw, - [AUD_CLKID_TDM_LRCLK_PAD0] =3D &g12a_tdm_lrclk_pad_0.hw, - [AUD_CLKID_TDM_LRCLK_PAD1] =3D &g12a_tdm_lrclk_pad_1.hw, - [AUD_CLKID_TDM_LRCLK_PAD2] =3D &g12a_tdm_lrclk_pad_2.hw, - [AUD_CLKID_TDM_SCLK_PAD0] =3D &g12a_tdm_sclk_pad_0.hw, - [AUD_CLKID_TDM_SCLK_PAD1] =3D &g12a_tdm_sclk_pad_1.hw, - [AUD_CLKID_TDM_SCLK_PAD2] =3D &g12a_tdm_sclk_pad_2.hw, - [AUD_CLKID_TOP] =3D &axg_aud_top, - [NR_CLKS] =3D NULL, - }, - .num =3D NR_CLKS, +static struct clk_hw *g12a_audio_hw_clks[] =3D { + [AUD_CLKID_DDR_ARB] =3D &ddr_arb.hw, + [AUD_CLKID_PDM] =3D &pdm.hw, + [AUD_CLKID_TDMIN_A] =3D &tdmin_a.hw, + [AUD_CLKID_TDMIN_B] =3D &tdmin_b.hw, + [AUD_CLKID_TDMIN_C] =3D &tdmin_c.hw, + [AUD_CLKID_TDMIN_LB] =3D &tdmin_lb.hw, + [AUD_CLKID_TDMOUT_A] =3D &tdmout_a.hw, + [AUD_CLKID_TDMOUT_B] =3D &tdmout_b.hw, + [AUD_CLKID_TDMOUT_C] =3D &tdmout_c.hw, + [AUD_CLKID_FRDDR_A] =3D &frddr_a.hw, + [AUD_CLKID_FRDDR_B] =3D &frddr_b.hw, + [AUD_CLKID_FRDDR_C] =3D &frddr_c.hw, + [AUD_CLKID_TODDR_A] =3D &toddr_a.hw, + [AUD_CLKID_TODDR_B] =3D &toddr_b.hw, + [AUD_CLKID_TODDR_C] =3D &toddr_c.hw, + [AUD_CLKID_LOOPBACK] =3D &loopback.hw, + [AUD_CLKID_SPDIFIN] =3D &spdifin.hw, + [AUD_CLKID_SPDIFOUT] =3D &spdifout.hw, + [AUD_CLKID_RESAMPLE] =3D &resample.hw, + [AUD_CLKID_POWER_DETECT] =3D &power_detect.hw, + [AUD_CLKID_SPDIFOUT_B] =3D &spdifout_b.hw, + [AUD_CLKID_MST_A_MCLK_SEL] =3D &mst_a_mclk_sel.hw, + [AUD_CLKID_MST_B_MCLK_SEL] =3D &mst_b_mclk_sel.hw, + [AUD_CLKID_MST_C_MCLK_SEL] =3D &mst_c_mclk_sel.hw, + [AUD_CLKID_MST_D_MCLK_SEL] =3D &mst_d_mclk_sel.hw, + [AUD_CLKID_MST_E_MCLK_SEL] =3D &mst_e_mclk_sel.hw, + [AUD_CLKID_MST_F_MCLK_SEL] =3D &mst_f_mclk_sel.hw, + [AUD_CLKID_MST_A_MCLK_DIV] =3D &mst_a_mclk_div.hw, + [AUD_CLKID_MST_B_MCLK_DIV] =3D &mst_b_mclk_div.hw, + [AUD_CLKID_MST_C_MCLK_DIV] =3D &mst_c_mclk_div.hw, + [AUD_CLKID_MST_D_MCLK_DIV] =3D &mst_d_mclk_div.hw, + [AUD_CLKID_MST_E_MCLK_DIV] =3D &mst_e_mclk_div.hw, + [AUD_CLKID_MST_F_MCLK_DIV] =3D &mst_f_mclk_div.hw, + [AUD_CLKID_MST_A_MCLK] =3D &mst_a_mclk.hw, + [AUD_CLKID_MST_B_MCLK] =3D &mst_b_mclk.hw, + [AUD_CLKID_MST_C_MCLK] =3D &mst_c_mclk.hw, + [AUD_CLKID_MST_D_MCLK] =3D &mst_d_mclk.hw, + [AUD_CLKID_MST_E_MCLK] =3D &mst_e_mclk.hw, + [AUD_CLKID_MST_F_MCLK] =3D &mst_f_mclk.hw, + [AUD_CLKID_SPDIFOUT_CLK_SEL] =3D &spdifout_clk_sel.hw, + [AUD_CLKID_SPDIFOUT_CLK_DIV] =3D &spdifout_clk_div.hw, + [AUD_CLKID_SPDIFOUT_CLK] =3D &spdifout_clk.hw, + [AUD_CLKID_SPDIFOUT_B_CLK_SEL] =3D &spdifout_b_clk_sel.hw, + [AUD_CLKID_SPDIFOUT_B_CLK_DIV] =3D &spdifout_b_clk_div.hw, + [AUD_CLKID_SPDIFOUT_B_CLK] =3D &spdifout_b_clk.hw, + [AUD_CLKID_SPDIFIN_CLK_SEL] =3D &spdifin_clk_sel.hw, + [AUD_CLKID_SPDIFIN_CLK_DIV] =3D &spdifin_clk_div.hw, + [AUD_CLKID_SPDIFIN_CLK] =3D &spdifin_clk.hw, + [AUD_CLKID_PDM_DCLK_SEL] =3D &pdm_dclk_sel.hw, + [AUD_CLKID_PDM_DCLK_DIV] =3D &pdm_dclk_div.hw, + [AUD_CLKID_PDM_DCLK] =3D &pdm_dclk.hw, + [AUD_CLKID_PDM_SYSCLK_SEL] =3D &pdm_sysclk_sel.hw, + [AUD_CLKID_PDM_SYSCLK_DIV] =3D &pdm_sysclk_div.hw, + [AUD_CLKID_PDM_SYSCLK] =3D &pdm_sysclk.hw, + [AUD_CLKID_MST_A_SCLK_PRE_EN] =3D &mst_a_sclk_pre_en.hw, + [AUD_CLKID_MST_B_SCLK_PRE_EN] =3D &mst_b_sclk_pre_en.hw, + [AUD_CLKID_MST_C_SCLK_PRE_EN] =3D &mst_c_sclk_pre_en.hw, + [AUD_CLKID_MST_D_SCLK_PRE_EN] =3D &mst_d_sclk_pre_en.hw, + [AUD_CLKID_MST_E_SCLK_PRE_EN] =3D &mst_e_sclk_pre_en.hw, + [AUD_CLKID_MST_F_SCLK_PRE_EN] =3D &mst_f_sclk_pre_en.hw, + [AUD_CLKID_MST_A_SCLK_DIV] =3D &mst_a_sclk_div.hw, + [AUD_CLKID_MST_B_SCLK_DIV] =3D &mst_b_sclk_div.hw, + [AUD_CLKID_MST_C_SCLK_DIV] =3D &mst_c_sclk_div.hw, + [AUD_CLKID_MST_D_SCLK_DIV] =3D &mst_d_sclk_div.hw, + [AUD_CLKID_MST_E_SCLK_DIV] =3D &mst_e_sclk_div.hw, + [AUD_CLKID_MST_F_SCLK_DIV] =3D &mst_f_sclk_div.hw, + [AUD_CLKID_MST_A_SCLK_POST_EN] =3D &mst_a_sclk_post_en.hw, + [AUD_CLKID_MST_B_SCLK_POST_EN] =3D &mst_b_sclk_post_en.hw, + [AUD_CLKID_MST_C_SCLK_POST_EN] =3D &mst_c_sclk_post_en.hw, + [AUD_CLKID_MST_D_SCLK_POST_EN] =3D &mst_d_sclk_post_en.hw, + [AUD_CLKID_MST_E_SCLK_POST_EN] =3D &mst_e_sclk_post_en.hw, + [AUD_CLKID_MST_F_SCLK_POST_EN] =3D &mst_f_sclk_post_en.hw, + [AUD_CLKID_MST_A_SCLK] =3D &mst_a_sclk.hw, + [AUD_CLKID_MST_B_SCLK] =3D &mst_b_sclk.hw, + [AUD_CLKID_MST_C_SCLK] =3D &mst_c_sclk.hw, + [AUD_CLKID_MST_D_SCLK] =3D &mst_d_sclk.hw, + [AUD_CLKID_MST_E_SCLK] =3D &mst_e_sclk.hw, + [AUD_CLKID_MST_F_SCLK] =3D &mst_f_sclk.hw, + [AUD_CLKID_MST_A_LRCLK_DIV] =3D &mst_a_lrclk_div.hw, + [AUD_CLKID_MST_B_LRCLK_DIV] =3D &mst_b_lrclk_div.hw, + [AUD_CLKID_MST_C_LRCLK_DIV] =3D &mst_c_lrclk_div.hw, + [AUD_CLKID_MST_D_LRCLK_DIV] =3D &mst_d_lrclk_div.hw, + [AUD_CLKID_MST_E_LRCLK_DIV] =3D &mst_e_lrclk_div.hw, + [AUD_CLKID_MST_F_LRCLK_DIV] =3D &mst_f_lrclk_div.hw, + [AUD_CLKID_MST_A_LRCLK] =3D &mst_a_lrclk.hw, + [AUD_CLKID_MST_B_LRCLK] =3D &mst_b_lrclk.hw, + [AUD_CLKID_MST_C_LRCLK] =3D &mst_c_lrclk.hw, + [AUD_CLKID_MST_D_LRCLK] =3D &mst_d_lrclk.hw, + [AUD_CLKID_MST_E_LRCLK] =3D &mst_e_lrclk.hw, + [AUD_CLKID_MST_F_LRCLK] =3D &mst_f_lrclk.hw, + [AUD_CLKID_TDMIN_A_SCLK_SEL] =3D &tdmin_a_sclk_sel.hw, + [AUD_CLKID_TDMIN_B_SCLK_SEL] =3D &tdmin_b_sclk_sel.hw, + [AUD_CLKID_TDMIN_C_SCLK_SEL] =3D &tdmin_c_sclk_sel.hw, + [AUD_CLKID_TDMIN_LB_SCLK_SEL] =3D &tdmin_lb_sclk_sel.hw, + [AUD_CLKID_TDMOUT_A_SCLK_SEL] =3D &tdmout_a_sclk_sel.hw, + [AUD_CLKID_TDMOUT_B_SCLK_SEL] =3D &tdmout_b_sclk_sel.hw, + [AUD_CLKID_TDMOUT_C_SCLK_SEL] =3D &tdmout_c_sclk_sel.hw, + [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] =3D &tdmin_a_sclk_pre_en.hw, + [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] =3D &tdmin_b_sclk_pre_en.hw, + [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] =3D &tdmin_c_sclk_pre_en.hw, + [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] =3D &tdmin_lb_sclk_pre_en.hw, + [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] =3D &tdmout_a_sclk_pre_en.hw, + [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] =3D &tdmout_b_sclk_pre_en.hw, + [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] =3D &tdmout_c_sclk_pre_en.hw, + [AUD_CLKID_TDMIN_A_SCLK_POST_EN] =3D &tdmin_a_sclk_post_en.hw, + [AUD_CLKID_TDMIN_B_SCLK_POST_EN] =3D &tdmin_b_sclk_post_en.hw, + [AUD_CLKID_TDMIN_C_SCLK_POST_EN] =3D &tdmin_c_sclk_post_en.hw, + [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] =3D &tdmin_lb_sclk_post_en.hw, + [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] =3D &tdmout_a_sclk_post_en.hw, + [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] =3D &tdmout_b_sclk_post_en.hw, + [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] =3D &tdmout_c_sclk_post_en.hw, + [AUD_CLKID_TDMIN_A_SCLK] =3D &tdmin_a_sclk.hw, + [AUD_CLKID_TDMIN_B_SCLK] =3D &tdmin_b_sclk.hw, + [AUD_CLKID_TDMIN_C_SCLK] =3D &tdmin_c_sclk.hw, + [AUD_CLKID_TDMIN_LB_SCLK] =3D &tdmin_lb_sclk.hw, + [AUD_CLKID_TDMOUT_A_SCLK] =3D &g12a_tdmout_a_sclk.hw, + [AUD_CLKID_TDMOUT_B_SCLK] =3D &g12a_tdmout_b_sclk.hw, + [AUD_CLKID_TDMOUT_C_SCLK] =3D &g12a_tdmout_c_sclk.hw, + [AUD_CLKID_TDMIN_A_LRCLK] =3D &tdmin_a_lrclk.hw, + [AUD_CLKID_TDMIN_B_LRCLK] =3D &tdmin_b_lrclk.hw, + [AUD_CLKID_TDMIN_C_LRCLK] =3D &tdmin_c_lrclk.hw, + [AUD_CLKID_TDMIN_LB_LRCLK] =3D &tdmin_lb_lrclk.hw, + [AUD_CLKID_TDMOUT_A_LRCLK] =3D &tdmout_a_lrclk.hw, + [AUD_CLKID_TDMOUT_B_LRCLK] =3D &tdmout_b_lrclk.hw, + [AUD_CLKID_TDMOUT_C_LRCLK] =3D &tdmout_c_lrclk.hw, + [AUD_CLKID_TDM_MCLK_PAD0] =3D &g12a_tdm_mclk_pad_0.hw, + [AUD_CLKID_TDM_MCLK_PAD1] =3D &g12a_tdm_mclk_pad_1.hw, + [AUD_CLKID_TDM_LRCLK_PAD0] =3D &g12a_tdm_lrclk_pad_0.hw, + [AUD_CLKID_TDM_LRCLK_PAD1] =3D &g12a_tdm_lrclk_pad_1.hw, + [AUD_CLKID_TDM_LRCLK_PAD2] =3D &g12a_tdm_lrclk_pad_2.hw, + [AUD_CLKID_TDM_SCLK_PAD0] =3D &g12a_tdm_sclk_pad_0.hw, + [AUD_CLKID_TDM_SCLK_PAD1] =3D &g12a_tdm_sclk_pad_1.hw, + [AUD_CLKID_TDM_SCLK_PAD2] =3D &g12a_tdm_sclk_pad_2.hw, + [AUD_CLKID_TOP] =3D &axg_aud_top, }; =20 /* * Array of all SM1 clocks provided by this provider * The input clocks of the controller will be populated at runtime */ -static struct clk_hw_onecell_data sm1_audio_hw_onecell_data =3D { - .hws =3D { - [AUD_CLKID_DDR_ARB] =3D &ddr_arb.hw, - [AUD_CLKID_PDM] =3D &pdm.hw, - [AUD_CLKID_TDMIN_A] =3D &tdmin_a.hw, - [AUD_CLKID_TDMIN_B] =3D &tdmin_b.hw, - [AUD_CLKID_TDMIN_C] =3D &tdmin_c.hw, - [AUD_CLKID_TDMIN_LB] =3D &tdmin_lb.hw, - [AUD_CLKID_TDMOUT_A] =3D &tdmout_a.hw, - [AUD_CLKID_TDMOUT_B] =3D &tdmout_b.hw, - [AUD_CLKID_TDMOUT_C] =3D &tdmout_c.hw, - [AUD_CLKID_FRDDR_A] =3D &frddr_a.hw, - [AUD_CLKID_FRDDR_B] =3D &frddr_b.hw, - [AUD_CLKID_FRDDR_C] =3D &frddr_c.hw, - [AUD_CLKID_TODDR_A] =3D &toddr_a.hw, - [AUD_CLKID_TODDR_B] =3D &toddr_b.hw, - [AUD_CLKID_TODDR_C] =3D &toddr_c.hw, - [AUD_CLKID_LOOPBACK] =3D &loopback.hw, - [AUD_CLKID_SPDIFIN] =3D &spdifin.hw, - [AUD_CLKID_SPDIFOUT] =3D &spdifout.hw, - [AUD_CLKID_RESAMPLE] =3D &resample.hw, - [AUD_CLKID_SPDIFOUT_B] =3D &spdifout_b.hw, - [AUD_CLKID_MST_A_MCLK_SEL] =3D &sm1_mst_a_mclk_sel.hw, - [AUD_CLKID_MST_B_MCLK_SEL] =3D &sm1_mst_b_mclk_sel.hw, - [AUD_CLKID_MST_C_MCLK_SEL] =3D &sm1_mst_c_mclk_sel.hw, - [AUD_CLKID_MST_D_MCLK_SEL] =3D &sm1_mst_d_mclk_sel.hw, - [AUD_CLKID_MST_E_MCLK_SEL] =3D &sm1_mst_e_mclk_sel.hw, - [AUD_CLKID_MST_F_MCLK_SEL] =3D &sm1_mst_f_mclk_sel.hw, - [AUD_CLKID_MST_A_MCLK_DIV] =3D &sm1_mst_a_mclk_div.hw, - [AUD_CLKID_MST_B_MCLK_DIV] =3D &sm1_mst_b_mclk_div.hw, - [AUD_CLKID_MST_C_MCLK_DIV] =3D &sm1_mst_c_mclk_div.hw, - [AUD_CLKID_MST_D_MCLK_DIV] =3D &sm1_mst_d_mclk_div.hw, - [AUD_CLKID_MST_E_MCLK_DIV] =3D &sm1_mst_e_mclk_div.hw, - [AUD_CLKID_MST_F_MCLK_DIV] =3D &sm1_mst_f_mclk_div.hw, - [AUD_CLKID_MST_A_MCLK] =3D &sm1_mst_a_mclk.hw, - [AUD_CLKID_MST_B_MCLK] =3D &sm1_mst_b_mclk.hw, - [AUD_CLKID_MST_C_MCLK] =3D &sm1_mst_c_mclk.hw, - [AUD_CLKID_MST_D_MCLK] =3D &sm1_mst_d_mclk.hw, - [AUD_CLKID_MST_E_MCLK] =3D &sm1_mst_e_mclk.hw, - [AUD_CLKID_MST_F_MCLK] =3D &sm1_mst_f_mclk.hw, - [AUD_CLKID_SPDIFOUT_CLK_SEL] =3D &spdifout_clk_sel.hw, - [AUD_CLKID_SPDIFOUT_CLK_DIV] =3D &spdifout_clk_div.hw, - [AUD_CLKID_SPDIFOUT_CLK] =3D &spdifout_clk.hw, - [AUD_CLKID_SPDIFOUT_B_CLK_SEL] =3D &spdifout_b_clk_sel.hw, - [AUD_CLKID_SPDIFOUT_B_CLK_DIV] =3D &spdifout_b_clk_div.hw, - [AUD_CLKID_SPDIFOUT_B_CLK] =3D &spdifout_b_clk.hw, - [AUD_CLKID_SPDIFIN_CLK_SEL] =3D &spdifin_clk_sel.hw, - [AUD_CLKID_SPDIFIN_CLK_DIV] =3D &spdifin_clk_div.hw, - [AUD_CLKID_SPDIFIN_CLK] =3D &spdifin_clk.hw, - [AUD_CLKID_PDM_DCLK_SEL] =3D &pdm_dclk_sel.hw, - [AUD_CLKID_PDM_DCLK_DIV] =3D &pdm_dclk_div.hw, - [AUD_CLKID_PDM_DCLK] =3D &pdm_dclk.hw, - [AUD_CLKID_PDM_SYSCLK_SEL] =3D &pdm_sysclk_sel.hw, - [AUD_CLKID_PDM_SYSCLK_DIV] =3D &pdm_sysclk_div.hw, - [AUD_CLKID_PDM_SYSCLK] =3D &pdm_sysclk.hw, - [AUD_CLKID_MST_A_SCLK_PRE_EN] =3D &mst_a_sclk_pre_en.hw, - [AUD_CLKID_MST_B_SCLK_PRE_EN] =3D &mst_b_sclk_pre_en.hw, - [AUD_CLKID_MST_C_SCLK_PRE_EN] =3D &mst_c_sclk_pre_en.hw, - [AUD_CLKID_MST_D_SCLK_PRE_EN] =3D &mst_d_sclk_pre_en.hw, - [AUD_CLKID_MST_E_SCLK_PRE_EN] =3D &mst_e_sclk_pre_en.hw, - [AUD_CLKID_MST_F_SCLK_PRE_EN] =3D &mst_f_sclk_pre_en.hw, - [AUD_CLKID_MST_A_SCLK_DIV] =3D &mst_a_sclk_div.hw, - [AUD_CLKID_MST_B_SCLK_DIV] =3D &mst_b_sclk_div.hw, - [AUD_CLKID_MST_C_SCLK_DIV] =3D &mst_c_sclk_div.hw, - [AUD_CLKID_MST_D_SCLK_DIV] =3D &mst_d_sclk_div.hw, - [AUD_CLKID_MST_E_SCLK_DIV] =3D &mst_e_sclk_div.hw, - [AUD_CLKID_MST_F_SCLK_DIV] =3D &mst_f_sclk_div.hw, - [AUD_CLKID_MST_A_SCLK_POST_EN] =3D &mst_a_sclk_post_en.hw, - [AUD_CLKID_MST_B_SCLK_POST_EN] =3D &mst_b_sclk_post_en.hw, - [AUD_CLKID_MST_C_SCLK_POST_EN] =3D &mst_c_sclk_post_en.hw, - [AUD_CLKID_MST_D_SCLK_POST_EN] =3D &mst_d_sclk_post_en.hw, - [AUD_CLKID_MST_E_SCLK_POST_EN] =3D &mst_e_sclk_post_en.hw, - [AUD_CLKID_MST_F_SCLK_POST_EN] =3D &mst_f_sclk_post_en.hw, - [AUD_CLKID_MST_A_SCLK] =3D &mst_a_sclk.hw, - [AUD_CLKID_MST_B_SCLK] =3D &mst_b_sclk.hw, - [AUD_CLKID_MST_C_SCLK] =3D &mst_c_sclk.hw, - [AUD_CLKID_MST_D_SCLK] =3D &mst_d_sclk.hw, - [AUD_CLKID_MST_E_SCLK] =3D &mst_e_sclk.hw, - [AUD_CLKID_MST_F_SCLK] =3D &mst_f_sclk.hw, - [AUD_CLKID_MST_A_LRCLK_DIV] =3D &mst_a_lrclk_div.hw, - [AUD_CLKID_MST_B_LRCLK_DIV] =3D &mst_b_lrclk_div.hw, - [AUD_CLKID_MST_C_LRCLK_DIV] =3D &mst_c_lrclk_div.hw, - [AUD_CLKID_MST_D_LRCLK_DIV] =3D &mst_d_lrclk_div.hw, - [AUD_CLKID_MST_E_LRCLK_DIV] =3D &mst_e_lrclk_div.hw, - [AUD_CLKID_MST_F_LRCLK_DIV] =3D &mst_f_lrclk_div.hw, - [AUD_CLKID_MST_A_LRCLK] =3D &mst_a_lrclk.hw, - [AUD_CLKID_MST_B_LRCLK] =3D &mst_b_lrclk.hw, - [AUD_CLKID_MST_C_LRCLK] =3D &mst_c_lrclk.hw, - [AUD_CLKID_MST_D_LRCLK] =3D &mst_d_lrclk.hw, - [AUD_CLKID_MST_E_LRCLK] =3D &mst_e_lrclk.hw, - [AUD_CLKID_MST_F_LRCLK] =3D &mst_f_lrclk.hw, - [AUD_CLKID_TDMIN_A_SCLK_SEL] =3D &tdmin_a_sclk_sel.hw, - [AUD_CLKID_TDMIN_B_SCLK_SEL] =3D &tdmin_b_sclk_sel.hw, - [AUD_CLKID_TDMIN_C_SCLK_SEL] =3D &tdmin_c_sclk_sel.hw, - [AUD_CLKID_TDMIN_LB_SCLK_SEL] =3D &tdmin_lb_sclk_sel.hw, - [AUD_CLKID_TDMOUT_A_SCLK_SEL] =3D &tdmout_a_sclk_sel.hw, - [AUD_CLKID_TDMOUT_B_SCLK_SEL] =3D &tdmout_b_sclk_sel.hw, - [AUD_CLKID_TDMOUT_C_SCLK_SEL] =3D &tdmout_c_sclk_sel.hw, - [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] =3D &tdmin_a_sclk_pre_en.hw, - [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] =3D &tdmin_b_sclk_pre_en.hw, - [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] =3D &tdmin_c_sclk_pre_en.hw, - [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] =3D &tdmin_lb_sclk_pre_en.hw, - [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] =3D &tdmout_a_sclk_pre_en.hw, - [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] =3D &tdmout_b_sclk_pre_en.hw, - [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] =3D &tdmout_c_sclk_pre_en.hw, - [AUD_CLKID_TDMIN_A_SCLK_POST_EN] =3D &tdmin_a_sclk_post_en.hw, - [AUD_CLKID_TDMIN_B_SCLK_POST_EN] =3D &tdmin_b_sclk_post_en.hw, - [AUD_CLKID_TDMIN_C_SCLK_POST_EN] =3D &tdmin_c_sclk_post_en.hw, - [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] =3D &tdmin_lb_sclk_post_en.hw, - [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] =3D &tdmout_a_sclk_post_en.hw, - [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] =3D &tdmout_b_sclk_post_en.hw, - [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] =3D &tdmout_c_sclk_post_en.hw, - [AUD_CLKID_TDMIN_A_SCLK] =3D &tdmin_a_sclk.hw, - [AUD_CLKID_TDMIN_B_SCLK] =3D &tdmin_b_sclk.hw, - [AUD_CLKID_TDMIN_C_SCLK] =3D &tdmin_c_sclk.hw, - [AUD_CLKID_TDMIN_LB_SCLK] =3D &tdmin_lb_sclk.hw, - [AUD_CLKID_TDMOUT_A_SCLK] =3D &g12a_tdmout_a_sclk.hw, - [AUD_CLKID_TDMOUT_B_SCLK] =3D &g12a_tdmout_b_sclk.hw, - [AUD_CLKID_TDMOUT_C_SCLK] =3D &g12a_tdmout_c_sclk.hw, - [AUD_CLKID_TDMIN_A_LRCLK] =3D &tdmin_a_lrclk.hw, - [AUD_CLKID_TDMIN_B_LRCLK] =3D &tdmin_b_lrclk.hw, - [AUD_CLKID_TDMIN_C_LRCLK] =3D &tdmin_c_lrclk.hw, - [AUD_CLKID_TDMIN_LB_LRCLK] =3D &tdmin_lb_lrclk.hw, - [AUD_CLKID_TDMOUT_A_LRCLK] =3D &tdmout_a_lrclk.hw, - [AUD_CLKID_TDMOUT_B_LRCLK] =3D &tdmout_b_lrclk.hw, - [AUD_CLKID_TDMOUT_C_LRCLK] =3D &tdmout_c_lrclk.hw, - [AUD_CLKID_TDM_MCLK_PAD0] =3D &sm1_tdm_mclk_pad_0.hw, - [AUD_CLKID_TDM_MCLK_PAD1] =3D &sm1_tdm_mclk_pad_1.hw, - [AUD_CLKID_TDM_LRCLK_PAD0] =3D &sm1_tdm_lrclk_pad_0.hw, - [AUD_CLKID_TDM_LRCLK_PAD1] =3D &sm1_tdm_lrclk_pad_1.hw, - [AUD_CLKID_TDM_LRCLK_PAD2] =3D &sm1_tdm_lrclk_pad_2.hw, - [AUD_CLKID_TDM_SCLK_PAD0] =3D &sm1_tdm_sclk_pad_0.hw, - [AUD_CLKID_TDM_SCLK_PAD1] =3D &sm1_tdm_sclk_pad_1.hw, - [AUD_CLKID_TDM_SCLK_PAD2] =3D &sm1_tdm_sclk_pad_2.hw, - [AUD_CLKID_TOP] =3D &sm1_aud_top.hw, - [AUD_CLKID_TORAM] =3D &toram.hw, - [AUD_CLKID_EQDRC] =3D &eqdrc.hw, - [AUD_CLKID_RESAMPLE_B] =3D &resample_b.hw, - [AUD_CLKID_TOVAD] =3D &tovad.hw, - [AUD_CLKID_LOCKER] =3D &locker.hw, - [AUD_CLKID_SPDIFIN_LB] =3D &spdifin_lb.hw, - [AUD_CLKID_FRDDR_D] =3D &frddr_d.hw, - [AUD_CLKID_TODDR_D] =3D &toddr_d.hw, - [AUD_CLKID_LOOPBACK_B] =3D &loopback_b.hw, - [AUD_CLKID_CLK81_EN] =3D &sm1_clk81_en.hw, - [AUD_CLKID_SYSCLK_A_DIV] =3D &sm1_sysclk_a_div.hw, - [AUD_CLKID_SYSCLK_A_EN] =3D &sm1_sysclk_a_en.hw, - [AUD_CLKID_SYSCLK_B_DIV] =3D &sm1_sysclk_b_div.hw, - [AUD_CLKID_SYSCLK_B_EN] =3D &sm1_sysclk_b_en.hw, - [NR_CLKS] =3D NULL, - }, - .num =3D NR_CLKS, +static struct clk_hw *sm1_audio_hw_clks[] =3D { + [AUD_CLKID_DDR_ARB] =3D &ddr_arb.hw, + [AUD_CLKID_PDM] =3D &pdm.hw, + [AUD_CLKID_TDMIN_A] =3D &tdmin_a.hw, + [AUD_CLKID_TDMIN_B] =3D &tdmin_b.hw, + [AUD_CLKID_TDMIN_C] =3D &tdmin_c.hw, + [AUD_CLKID_TDMIN_LB] =3D &tdmin_lb.hw, + [AUD_CLKID_TDMOUT_A] =3D &tdmout_a.hw, + [AUD_CLKID_TDMOUT_B] =3D &tdmout_b.hw, + [AUD_CLKID_TDMOUT_C] =3D &tdmout_c.hw, + [AUD_CLKID_FRDDR_A] =3D &frddr_a.hw, + [AUD_CLKID_FRDDR_B] =3D &frddr_b.hw, + [AUD_CLKID_FRDDR_C] =3D &frddr_c.hw, + [AUD_CLKID_TODDR_A] =3D &toddr_a.hw, + [AUD_CLKID_TODDR_B] =3D &toddr_b.hw, + [AUD_CLKID_TODDR_C] =3D &toddr_c.hw, + [AUD_CLKID_LOOPBACK] =3D &loopback.hw, + [AUD_CLKID_SPDIFIN] =3D &spdifin.hw, + [AUD_CLKID_SPDIFOUT] =3D &spdifout.hw, + [AUD_CLKID_RESAMPLE] =3D &resample.hw, + [AUD_CLKID_SPDIFOUT_B] =3D &spdifout_b.hw, + [AUD_CLKID_MST_A_MCLK_SEL] =3D &sm1_mst_a_mclk_sel.hw, + [AUD_CLKID_MST_B_MCLK_SEL] =3D &sm1_mst_b_mclk_sel.hw, + [AUD_CLKID_MST_C_MCLK_SEL] =3D &sm1_mst_c_mclk_sel.hw, + [AUD_CLKID_MST_D_MCLK_SEL] =3D &sm1_mst_d_mclk_sel.hw, + [AUD_CLKID_MST_E_MCLK_SEL] =3D &sm1_mst_e_mclk_sel.hw, + [AUD_CLKID_MST_F_MCLK_SEL] =3D &sm1_mst_f_mclk_sel.hw, + [AUD_CLKID_MST_A_MCLK_DIV] =3D &sm1_mst_a_mclk_div.hw, + [AUD_CLKID_MST_B_MCLK_DIV] =3D &sm1_mst_b_mclk_div.hw, + [AUD_CLKID_MST_C_MCLK_DIV] =3D &sm1_mst_c_mclk_div.hw, + [AUD_CLKID_MST_D_MCLK_DIV] =3D &sm1_mst_d_mclk_div.hw, + [AUD_CLKID_MST_E_MCLK_DIV] =3D &sm1_mst_e_mclk_div.hw, + [AUD_CLKID_MST_F_MCLK_DIV] =3D &sm1_mst_f_mclk_div.hw, + [AUD_CLKID_MST_A_MCLK] =3D &sm1_mst_a_mclk.hw, + [AUD_CLKID_MST_B_MCLK] =3D &sm1_mst_b_mclk.hw, + [AUD_CLKID_MST_C_MCLK] =3D &sm1_mst_c_mclk.hw, + [AUD_CLKID_MST_D_MCLK] =3D &sm1_mst_d_mclk.hw, + [AUD_CLKID_MST_E_MCLK] =3D &sm1_mst_e_mclk.hw, + [AUD_CLKID_MST_F_MCLK] =3D &sm1_mst_f_mclk.hw, + [AUD_CLKID_SPDIFOUT_CLK_SEL] =3D &spdifout_clk_sel.hw, + [AUD_CLKID_SPDIFOUT_CLK_DIV] =3D &spdifout_clk_div.hw, + [AUD_CLKID_SPDIFOUT_CLK] =3D &spdifout_clk.hw, + [AUD_CLKID_SPDIFOUT_B_CLK_SEL] =3D &spdifout_b_clk_sel.hw, + [AUD_CLKID_SPDIFOUT_B_CLK_DIV] =3D &spdifout_b_clk_div.hw, + [AUD_CLKID_SPDIFOUT_B_CLK] =3D &spdifout_b_clk.hw, + [AUD_CLKID_SPDIFIN_CLK_SEL] =3D &spdifin_clk_sel.hw, + [AUD_CLKID_SPDIFIN_CLK_DIV] =3D &spdifin_clk_div.hw, + [AUD_CLKID_SPDIFIN_CLK] =3D &spdifin_clk.hw, + [AUD_CLKID_PDM_DCLK_SEL] =3D &pdm_dclk_sel.hw, + [AUD_CLKID_PDM_DCLK_DIV] =3D &pdm_dclk_div.hw, + [AUD_CLKID_PDM_DCLK] =3D &pdm_dclk.hw, + [AUD_CLKID_PDM_SYSCLK_SEL] =3D &pdm_sysclk_sel.hw, + [AUD_CLKID_PDM_SYSCLK_DIV] =3D &pdm_sysclk_div.hw, + [AUD_CLKID_PDM_SYSCLK] =3D &pdm_sysclk.hw, + [AUD_CLKID_MST_A_SCLK_PRE_EN] =3D &mst_a_sclk_pre_en.hw, + [AUD_CLKID_MST_B_SCLK_PRE_EN] =3D &mst_b_sclk_pre_en.hw, + [AUD_CLKID_MST_C_SCLK_PRE_EN] =3D &mst_c_sclk_pre_en.hw, + [AUD_CLKID_MST_D_SCLK_PRE_EN] =3D &mst_d_sclk_pre_en.hw, + [AUD_CLKID_MST_E_SCLK_PRE_EN] =3D &mst_e_sclk_pre_en.hw, + [AUD_CLKID_MST_F_SCLK_PRE_EN] =3D &mst_f_sclk_pre_en.hw, + [AUD_CLKID_MST_A_SCLK_DIV] =3D &mst_a_sclk_div.hw, + [AUD_CLKID_MST_B_SCLK_DIV] =3D &mst_b_sclk_div.hw, + [AUD_CLKID_MST_C_SCLK_DIV] =3D &mst_c_sclk_div.hw, + [AUD_CLKID_MST_D_SCLK_DIV] =3D &mst_d_sclk_div.hw, + [AUD_CLKID_MST_E_SCLK_DIV] =3D &mst_e_sclk_div.hw, + [AUD_CLKID_MST_F_SCLK_DIV] =3D &mst_f_sclk_div.hw, + [AUD_CLKID_MST_A_SCLK_POST_EN] =3D &mst_a_sclk_post_en.hw, + [AUD_CLKID_MST_B_SCLK_POST_EN] =3D &mst_b_sclk_post_en.hw, + [AUD_CLKID_MST_C_SCLK_POST_EN] =3D &mst_c_sclk_post_en.hw, + [AUD_CLKID_MST_D_SCLK_POST_EN] =3D &mst_d_sclk_post_en.hw, + [AUD_CLKID_MST_E_SCLK_POST_EN] =3D &mst_e_sclk_post_en.hw, + [AUD_CLKID_MST_F_SCLK_POST_EN] =3D &mst_f_sclk_post_en.hw, + [AUD_CLKID_MST_A_SCLK] =3D &mst_a_sclk.hw, + [AUD_CLKID_MST_B_SCLK] =3D &mst_b_sclk.hw, + [AUD_CLKID_MST_C_SCLK] =3D &mst_c_sclk.hw, + [AUD_CLKID_MST_D_SCLK] =3D &mst_d_sclk.hw, + [AUD_CLKID_MST_E_SCLK] =3D &mst_e_sclk.hw, + [AUD_CLKID_MST_F_SCLK] =3D &mst_f_sclk.hw, + [AUD_CLKID_MST_A_LRCLK_DIV] =3D &mst_a_lrclk_div.hw, + [AUD_CLKID_MST_B_LRCLK_DIV] =3D &mst_b_lrclk_div.hw, + [AUD_CLKID_MST_C_LRCLK_DIV] =3D &mst_c_lrclk_div.hw, + [AUD_CLKID_MST_D_LRCLK_DIV] =3D &mst_d_lrclk_div.hw, + [AUD_CLKID_MST_E_LRCLK_DIV] =3D &mst_e_lrclk_div.hw, + [AUD_CLKID_MST_F_LRCLK_DIV] =3D &mst_f_lrclk_div.hw, + [AUD_CLKID_MST_A_LRCLK] =3D &mst_a_lrclk.hw, + [AUD_CLKID_MST_B_LRCLK] =3D &mst_b_lrclk.hw, + [AUD_CLKID_MST_C_LRCLK] =3D &mst_c_lrclk.hw, + [AUD_CLKID_MST_D_LRCLK] =3D &mst_d_lrclk.hw, + [AUD_CLKID_MST_E_LRCLK] =3D &mst_e_lrclk.hw, + [AUD_CLKID_MST_F_LRCLK] =3D &mst_f_lrclk.hw, + [AUD_CLKID_TDMIN_A_SCLK_SEL] =3D &tdmin_a_sclk_sel.hw, + [AUD_CLKID_TDMIN_B_SCLK_SEL] =3D &tdmin_b_sclk_sel.hw, + [AUD_CLKID_TDMIN_C_SCLK_SEL] =3D &tdmin_c_sclk_sel.hw, + [AUD_CLKID_TDMIN_LB_SCLK_SEL] =3D &tdmin_lb_sclk_sel.hw, + [AUD_CLKID_TDMOUT_A_SCLK_SEL] =3D &tdmout_a_sclk_sel.hw, + [AUD_CLKID_TDMOUT_B_SCLK_SEL] =3D &tdmout_b_sclk_sel.hw, + [AUD_CLKID_TDMOUT_C_SCLK_SEL] =3D &tdmout_c_sclk_sel.hw, + [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] =3D &tdmin_a_sclk_pre_en.hw, + [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] =3D &tdmin_b_sclk_pre_en.hw, + [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] =3D &tdmin_c_sclk_pre_en.hw, + [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] =3D &tdmin_lb_sclk_pre_en.hw, + [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] =3D &tdmout_a_sclk_pre_en.hw, + [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] =3D &tdmout_b_sclk_pre_en.hw, + [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] =3D &tdmout_c_sclk_pre_en.hw, + [AUD_CLKID_TDMIN_A_SCLK_POST_EN] =3D &tdmin_a_sclk_post_en.hw, + [AUD_CLKID_TDMIN_B_SCLK_POST_EN] =3D &tdmin_b_sclk_post_en.hw, + [AUD_CLKID_TDMIN_C_SCLK_POST_EN] =3D &tdmin_c_sclk_post_en.hw, + [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] =3D &tdmin_lb_sclk_post_en.hw, + [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] =3D &tdmout_a_sclk_post_en.hw, + [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] =3D &tdmout_b_sclk_post_en.hw, + [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] =3D &tdmout_c_sclk_post_en.hw, + [AUD_CLKID_TDMIN_A_SCLK] =3D &tdmin_a_sclk.hw, + [AUD_CLKID_TDMIN_B_SCLK] =3D &tdmin_b_sclk.hw, + [AUD_CLKID_TDMIN_C_SCLK] =3D &tdmin_c_sclk.hw, + [AUD_CLKID_TDMIN_LB_SCLK] =3D &tdmin_lb_sclk.hw, + [AUD_CLKID_TDMOUT_A_SCLK] =3D &g12a_tdmout_a_sclk.hw, + [AUD_CLKID_TDMOUT_B_SCLK] =3D &g12a_tdmout_b_sclk.hw, + [AUD_CLKID_TDMOUT_C_SCLK] =3D &g12a_tdmout_c_sclk.hw, + [AUD_CLKID_TDMIN_A_LRCLK] =3D &tdmin_a_lrclk.hw, + [AUD_CLKID_TDMIN_B_LRCLK] =3D &tdmin_b_lrclk.hw, + [AUD_CLKID_TDMIN_C_LRCLK] =3D &tdmin_c_lrclk.hw, + [AUD_CLKID_TDMIN_LB_LRCLK] =3D &tdmin_lb_lrclk.hw, + [AUD_CLKID_TDMOUT_A_LRCLK] =3D &tdmout_a_lrclk.hw, + [AUD_CLKID_TDMOUT_B_LRCLK] =3D &tdmout_b_lrclk.hw, + [AUD_CLKID_TDMOUT_C_LRCLK] =3D &tdmout_c_lrclk.hw, + [AUD_CLKID_TDM_MCLK_PAD0] =3D &sm1_tdm_mclk_pad_0.hw, + [AUD_CLKID_TDM_MCLK_PAD1] =3D &sm1_tdm_mclk_pad_1.hw, + [AUD_CLKID_TDM_LRCLK_PAD0] =3D &sm1_tdm_lrclk_pad_0.hw, + [AUD_CLKID_TDM_LRCLK_PAD1] =3D &sm1_tdm_lrclk_pad_1.hw, + [AUD_CLKID_TDM_LRCLK_PAD2] =3D &sm1_tdm_lrclk_pad_2.hw, + [AUD_CLKID_TDM_SCLK_PAD0] =3D &sm1_tdm_sclk_pad_0.hw, + [AUD_CLKID_TDM_SCLK_PAD1] =3D &sm1_tdm_sclk_pad_1.hw, + [AUD_CLKID_TDM_SCLK_PAD2] =3D &sm1_tdm_sclk_pad_2.hw, + [AUD_CLKID_TOP] =3D &sm1_aud_top.hw, + [AUD_CLKID_TORAM] =3D &toram.hw, + [AUD_CLKID_EQDRC] =3D &eqdrc.hw, + [AUD_CLKID_RESAMPLE_B] =3D &resample_b.hw, + [AUD_CLKID_TOVAD] =3D &tovad.hw, + [AUD_CLKID_LOCKER] =3D &locker.hw, + [AUD_CLKID_SPDIFIN_LB] =3D &spdifin_lb.hw, + [AUD_CLKID_FRDDR_D] =3D &frddr_d.hw, + [AUD_CLKID_TODDR_D] =3D &toddr_d.hw, + [AUD_CLKID_LOOPBACK_B] =3D &loopback_b.hw, + [AUD_CLKID_CLK81_EN] =3D &sm1_clk81_en.hw, + [AUD_CLKID_SYSCLK_A_DIV] =3D &sm1_sysclk_a_div.hw, + [AUD_CLKID_SYSCLK_A_EN] =3D &sm1_sysclk_a_en.hw, + [AUD_CLKID_SYSCLK_B_DIV] =3D &sm1_sysclk_b_div.hw, + [AUD_CLKID_SYSCLK_B_EN] =3D &sm1_sysclk_b_en.hw, }; =20 =20 @@ -1745,7 +1734,7 @@ static const struct regmap_config axg_audio_regmap_cf= g =3D { struct audioclk_data { struct clk_regmap *const *regmap_clks; unsigned int regmap_clk_num; - struct clk_hw_onecell_data *hw_onecell_data; + struct meson_clk_hw_data hw_clks; unsigned int reset_offset; unsigned int reset_num; }; @@ -1791,10 +1780,10 @@ static int axg_audio_clkc_probe(struct platform_dev= ice *pdev) data->regmap_clks[i]->map =3D map; =20 /* Take care to skip the registered input clocks */ - for (i =3D AUD_CLKID_DDR_ARB; i < data->hw_onecell_data->num; i++) { + for (i =3D AUD_CLKID_DDR_ARB; i < data->hw_clks.num; i++) { const char *name; =20 - hw =3D data->hw_onecell_data->hws[i]; + hw =3D data->hw_clks.hws[i]; /* array might be sparse */ if (!hw) continue; @@ -1808,8 +1797,7 @@ static int axg_audio_clkc_probe(struct platform_devic= e *pdev) } } =20 - ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, - data->hw_onecell_data); + ret =3D devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data-= >hw_clks); if (ret) return ret; =20 @@ -1834,13 +1822,19 @@ static int axg_audio_clkc_probe(struct platform_dev= ice *pdev) static const struct audioclk_data axg_audioclk_data =3D { .regmap_clks =3D axg_clk_regmaps, .regmap_clk_num =3D ARRAY_SIZE(axg_clk_regmaps), - .hw_onecell_data =3D &axg_audio_hw_onecell_data, + .hw_clks =3D { + .hws =3D axg_audio_hw_clks, + .num =3D ARRAY_SIZE(axg_audio_hw_clks), + }, }; =20 static const struct audioclk_data g12a_audioclk_data =3D { .regmap_clks =3D g12a_clk_regmaps, .regmap_clk_num =3D ARRAY_SIZE(g12a_clk_regmaps), - .hw_onecell_data =3D &g12a_audio_hw_onecell_data, + .hw_clks =3D { + .hws =3D g12a_audio_hw_clks, + .num =3D ARRAY_SIZE(g12a_audio_hw_clks), + }, .reset_offset =3D AUDIO_SW_RESET, .reset_num =3D 26, }; @@ -1848,7 +1842,10 @@ static const struct audioclk_data g12a_audioclk_data= =3D { static const struct audioclk_data sm1_audioclk_data =3D { .regmap_clks =3D sm1_clk_regmaps, .regmap_clk_num =3D ARRAY_SIZE(sm1_clk_regmaps), - .hw_onecell_data =3D &sm1_audio_hw_onecell_data, + .hw_clks =3D { + .hws =3D sm1_audio_hw_clks, + .num =3D ARRAY_SIZE(sm1_audio_hw_clks), + }, .reset_offset =3D AUDIO_SM1_SW_RESET0, .reset_num =3D 39, }; diff --git a/drivers/clk/meson/axg-audio.h b/drivers/clk/meson/axg-audio.h index fd65a7d0704b..d6ed27c77729 100644 --- a/drivers/clk/meson/axg-audio.h +++ b/drivers/clk/meson/axg-audio.h @@ -138,6 +138,4 @@ /* include the CLKIDs which are part of the DT bindings */ #include =20 -#define NR_CLKS 178 - #endif /*__AXG_AUDIO_CLKC_H */ --=20 2.34.1