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Mon, 12 Jun 2023 02:57:36 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id f25-20020a7bcd19000000b003f7ff520a14sm10829525wmj.22.2023.06.12.02.57.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jun 2023 02:57:35 -0700 (PDT) From: Neil Armstrong Date: Mon, 12 Jun 2023 11:57:19 +0200 Subject: [PATCH v2 02/19] clk: meson: migrate meson-eeclk out of hw_onecell_data to drop NR_CLKS MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230607-topic-amlogic-upstream-clkid-public-migration-v2-2-38172d17c27a@linaro.org> References: <20230607-topic-amlogic-upstream-clkid-public-migration-v2-0-38172d17c27a@linaro.org> In-Reply-To: <20230607-topic-amlogic-upstream-clkid-public-migration-v2-0-38172d17c27a@linaro.org> To: Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The way hw_onecell_data is declared: struct clk_hw_onecell_data { unsigned int num; struct clk_hw *hws[]; }; makes it impossible to have the clk_hw table declared outside while using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible array member. Completely move out of hw_onecell_data and add a custom devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw from the meson_eeclkc_data struct to finally get rid on the NR_CLKS define. Signed-off-by: Neil Armstrong --- drivers/clk/meson/Kconfig | 1 + drivers/clk/meson/axg.c | 283 ++++---- drivers/clk/meson/axg.h | 2 - drivers/clk/meson/g12a.c | 1487 +++++++++++++++++++----------------= ---- drivers/clk/meson/g12a.h | 2 - drivers/clk/meson/gxbb.c | 846 +++++++++++----------- drivers/clk/meson/gxbb.h | 2 - drivers/clk/meson/meson-eeclk.c | 9 +- drivers/clk/meson/meson-eeclk.h | 3 +- 9 files changed, 1312 insertions(+), 1323 deletions(-) diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index d03adad31318..5bf901da8a63 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -41,6 +41,7 @@ config COMMON_CLK_MESON_AO_CLKC config COMMON_CLK_MESON_EE_CLKC tristate select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_CLKC_UTILS =20 config COMMON_CLK_MESON_CPU_DYNDIV tristate diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 2ad3801398dc..75f0912a9805 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -1890,147 +1890,143 @@ static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4); =20 /* Array of all clocks provided by this provider */ =20 -static struct clk_hw_onecell_data axg_hw_onecell_data =3D { - .hws =3D { - [CLKID_SYS_PLL] =3D &axg_sys_pll.hw, - [CLKID_FIXED_PLL] =3D &axg_fixed_pll.hw, - [CLKID_FCLK_DIV2] =3D &axg_fclk_div2.hw, - [CLKID_FCLK_DIV3] =3D &axg_fclk_div3.hw, - [CLKID_FCLK_DIV4] =3D &axg_fclk_div4.hw, - [CLKID_FCLK_DIV5] =3D &axg_fclk_div5.hw, - [CLKID_FCLK_DIV7] =3D &axg_fclk_div7.hw, - [CLKID_GP0_PLL] =3D &axg_gp0_pll.hw, - [CLKID_MPEG_SEL] =3D &axg_mpeg_clk_sel.hw, - [CLKID_MPEG_DIV] =3D &axg_mpeg_clk_div.hw, - [CLKID_CLK81] =3D &axg_clk81.hw, - [CLKID_MPLL0] =3D &axg_mpll0.hw, - [CLKID_MPLL1] =3D &axg_mpll1.hw, - [CLKID_MPLL2] =3D &axg_mpll2.hw, - [CLKID_MPLL3] =3D &axg_mpll3.hw, - [CLKID_DDR] =3D &axg_ddr.hw, - [CLKID_AUDIO_LOCKER] =3D &axg_audio_locker.hw, - [CLKID_MIPI_DSI_HOST] =3D &axg_mipi_dsi_host.hw, - [CLKID_ISA] =3D &axg_isa.hw, - [CLKID_PL301] =3D &axg_pl301.hw, - [CLKID_PERIPHS] =3D &axg_periphs.hw, - [CLKID_SPICC0] =3D &axg_spicc_0.hw, - [CLKID_I2C] =3D &axg_i2c.hw, - [CLKID_RNG0] =3D &axg_rng0.hw, - [CLKID_UART0] =3D &axg_uart0.hw, - [CLKID_MIPI_DSI_PHY] =3D &axg_mipi_dsi_phy.hw, - [CLKID_SPICC1] =3D &axg_spicc_1.hw, - [CLKID_PCIE_A] =3D &axg_pcie_a.hw, - [CLKID_PCIE_B] =3D &axg_pcie_b.hw, - [CLKID_HIU_IFACE] =3D &axg_hiu_reg.hw, - [CLKID_ASSIST_MISC] =3D &axg_assist_misc.hw, - [CLKID_SD_EMMC_B] =3D &axg_emmc_b.hw, - [CLKID_SD_EMMC_C] =3D &axg_emmc_c.hw, - [CLKID_DMA] =3D &axg_dma.hw, - [CLKID_SPI] =3D &axg_spi.hw, - [CLKID_AUDIO] =3D &axg_audio.hw, - [CLKID_ETH] =3D &axg_eth_core.hw, - [CLKID_UART1] =3D &axg_uart1.hw, - [CLKID_G2D] =3D &axg_g2d.hw, - [CLKID_USB0] =3D &axg_usb0.hw, - [CLKID_USB1] =3D &axg_usb1.hw, - [CLKID_RESET] =3D &axg_reset.hw, - [CLKID_USB] =3D &axg_usb_general.hw, - [CLKID_AHB_ARB0] =3D &axg_ahb_arb0.hw, - [CLKID_EFUSE] =3D &axg_efuse.hw, - [CLKID_BOOT_ROM] =3D &axg_boot_rom.hw, - [CLKID_AHB_DATA_BUS] =3D &axg_ahb_data_bus.hw, - [CLKID_AHB_CTRL_BUS] =3D &axg_ahb_ctrl_bus.hw, - [CLKID_USB1_DDR_BRIDGE] =3D &axg_usb1_to_ddr.hw, - [CLKID_USB0_DDR_BRIDGE] =3D &axg_usb0_to_ddr.hw, - [CLKID_MMC_PCLK] =3D &axg_mmc_pclk.hw, - [CLKID_VPU_INTR] =3D &axg_vpu_intr.hw, - [CLKID_SEC_AHB_AHB3_BRIDGE] =3D &axg_sec_ahb_ahb3_bridge.hw, - [CLKID_GIC] =3D &axg_gic.hw, - [CLKID_AO_MEDIA_CPU] =3D &axg_ao_media_cpu.hw, - [CLKID_AO_AHB_SRAM] =3D &axg_ao_ahb_sram.hw, - [CLKID_AO_AHB_BUS] =3D &axg_ao_ahb_bus.hw, - [CLKID_AO_IFACE] =3D &axg_ao_iface.hw, - [CLKID_AO_I2C] =3D &axg_ao_i2c.hw, - [CLKID_SD_EMMC_B_CLK0_SEL] =3D &axg_sd_emmc_b_clk0_sel.hw, - [CLKID_SD_EMMC_B_CLK0_DIV] =3D &axg_sd_emmc_b_clk0_div.hw, - [CLKID_SD_EMMC_B_CLK0] =3D &axg_sd_emmc_b_clk0.hw, - [CLKID_SD_EMMC_C_CLK0_SEL] =3D &axg_sd_emmc_c_clk0_sel.hw, - [CLKID_SD_EMMC_C_CLK0_DIV] =3D &axg_sd_emmc_c_clk0_div.hw, - [CLKID_SD_EMMC_C_CLK0] =3D &axg_sd_emmc_c_clk0.hw, - [CLKID_MPLL0_DIV] =3D &axg_mpll0_div.hw, - [CLKID_MPLL1_DIV] =3D &axg_mpll1_div.hw, - [CLKID_MPLL2_DIV] =3D &axg_mpll2_div.hw, - [CLKID_MPLL3_DIV] =3D &axg_mpll3_div.hw, - [CLKID_HIFI_PLL] =3D &axg_hifi_pll.hw, - [CLKID_MPLL_PREDIV] =3D &axg_mpll_prediv.hw, - [CLKID_FCLK_DIV2_DIV] =3D &axg_fclk_div2_div.hw, - [CLKID_FCLK_DIV3_DIV] =3D &axg_fclk_div3_div.hw, - [CLKID_FCLK_DIV4_DIV] =3D &axg_fclk_div4_div.hw, - [CLKID_FCLK_DIV5_DIV] =3D &axg_fclk_div5_div.hw, - [CLKID_FCLK_DIV7_DIV] =3D &axg_fclk_div7_div.hw, - [CLKID_PCIE_PLL] =3D &axg_pcie_pll.hw, - [CLKID_PCIE_MUX] =3D &axg_pcie_mux.hw, - [CLKID_PCIE_REF] =3D &axg_pcie_ref.hw, - [CLKID_PCIE_CML_EN0] =3D &axg_pcie_cml_en0.hw, - [CLKID_PCIE_CML_EN1] =3D &axg_pcie_cml_en1.hw, - [CLKID_GEN_CLK_SEL] =3D &axg_gen_clk_sel.hw, - [CLKID_GEN_CLK_DIV] =3D &axg_gen_clk_div.hw, - [CLKID_GEN_CLK] =3D &axg_gen_clk.hw, - [CLKID_SYS_PLL_DCO] =3D &axg_sys_pll_dco.hw, - [CLKID_FIXED_PLL_DCO] =3D &axg_fixed_pll_dco.hw, - [CLKID_GP0_PLL_DCO] =3D &axg_gp0_pll_dco.hw, - [CLKID_HIFI_PLL_DCO] =3D &axg_hifi_pll_dco.hw, - [CLKID_PCIE_PLL_DCO] =3D &axg_pcie_pll_dco.hw, - [CLKID_PCIE_PLL_OD] =3D &axg_pcie_pll_od.hw, - [CLKID_VPU_0_DIV] =3D &axg_vpu_0_div.hw, - [CLKID_VPU_0_SEL] =3D &axg_vpu_0_sel.hw, - [CLKID_VPU_0] =3D &axg_vpu_0.hw, - [CLKID_VPU_1_DIV] =3D &axg_vpu_1_div.hw, - [CLKID_VPU_1_SEL] =3D &axg_vpu_1_sel.hw, - [CLKID_VPU_1] =3D &axg_vpu_1.hw, - [CLKID_VPU] =3D &axg_vpu.hw, - [CLKID_VAPB_0_DIV] =3D &axg_vapb_0_div.hw, - [CLKID_VAPB_0_SEL] =3D &axg_vapb_0_sel.hw, - [CLKID_VAPB_0] =3D &axg_vapb_0.hw, - [CLKID_VAPB_1_DIV] =3D &axg_vapb_1_div.hw, - [CLKID_VAPB_1_SEL] =3D &axg_vapb_1_sel.hw, - [CLKID_VAPB_1] =3D &axg_vapb_1.hw, - [CLKID_VAPB_SEL] =3D &axg_vapb_sel.hw, - [CLKID_VAPB] =3D &axg_vapb.hw, - [CLKID_VCLK] =3D &axg_vclk.hw, - [CLKID_VCLK2] =3D &axg_vclk2.hw, - [CLKID_VCLK_SEL] =3D &axg_vclk_sel.hw, - [CLKID_VCLK2_SEL] =3D &axg_vclk2_sel.hw, - [CLKID_VCLK_INPUT] =3D &axg_vclk_input.hw, - [CLKID_VCLK2_INPUT] =3D &axg_vclk2_input.hw, - [CLKID_VCLK_DIV] =3D &axg_vclk_div.hw, - [CLKID_VCLK2_DIV] =3D &axg_vclk2_div.hw, - [CLKID_VCLK_DIV2_EN] =3D &axg_vclk_div2_en.hw, - [CLKID_VCLK_DIV4_EN] =3D &axg_vclk_div4_en.hw, - [CLKID_VCLK_DIV6_EN] =3D &axg_vclk_div6_en.hw, - [CLKID_VCLK_DIV12_EN] =3D &axg_vclk_div12_en.hw, - [CLKID_VCLK2_DIV2_EN] =3D &axg_vclk2_div2_en.hw, - [CLKID_VCLK2_DIV4_EN] =3D &axg_vclk2_div4_en.hw, - [CLKID_VCLK2_DIV6_EN] =3D &axg_vclk2_div6_en.hw, - [CLKID_VCLK2_DIV12_EN] =3D &axg_vclk2_div12_en.hw, - [CLKID_VCLK_DIV1] =3D &axg_vclk_div1.hw, - [CLKID_VCLK_DIV2] =3D &axg_vclk_div2.hw, - [CLKID_VCLK_DIV4] =3D &axg_vclk_div4.hw, - [CLKID_VCLK_DIV6] =3D &axg_vclk_div6.hw, - [CLKID_VCLK_DIV12] =3D &axg_vclk_div12.hw, - [CLKID_VCLK2_DIV1] =3D &axg_vclk2_div1.hw, - [CLKID_VCLK2_DIV2] =3D &axg_vclk2_div2.hw, - [CLKID_VCLK2_DIV4] =3D &axg_vclk2_div4.hw, - [CLKID_VCLK2_DIV6] =3D &axg_vclk2_div6.hw, - [CLKID_VCLK2_DIV12] =3D &axg_vclk2_div12.hw, - [CLKID_CTS_ENCL_SEL] =3D &axg_cts_encl_sel.hw, - [CLKID_CTS_ENCL] =3D &axg_cts_encl.hw, - [CLKID_VDIN_MEAS_SEL] =3D &axg_vdin_meas_sel.hw, - [CLKID_VDIN_MEAS_DIV] =3D &axg_vdin_meas_div.hw, - [CLKID_VDIN_MEAS] =3D &axg_vdin_meas.hw, - [NR_CLKS] =3D NULL, - }, - .num =3D NR_CLKS, +static struct clk_hw *axg_hw_clks[] =3D { + [CLKID_SYS_PLL] =3D &axg_sys_pll.hw, + [CLKID_FIXED_PLL] =3D &axg_fixed_pll.hw, + [CLKID_FCLK_DIV2] =3D &axg_fclk_div2.hw, + [CLKID_FCLK_DIV3] =3D &axg_fclk_div3.hw, + [CLKID_FCLK_DIV4] =3D &axg_fclk_div4.hw, + [CLKID_FCLK_DIV5] =3D &axg_fclk_div5.hw, + [CLKID_FCLK_DIV7] =3D &axg_fclk_div7.hw, + [CLKID_GP0_PLL] =3D &axg_gp0_pll.hw, + [CLKID_MPEG_SEL] =3D &axg_mpeg_clk_sel.hw, + [CLKID_MPEG_DIV] =3D &axg_mpeg_clk_div.hw, + [CLKID_CLK81] =3D &axg_clk81.hw, + [CLKID_MPLL0] =3D &axg_mpll0.hw, + [CLKID_MPLL1] =3D &axg_mpll1.hw, + [CLKID_MPLL2] =3D &axg_mpll2.hw, + [CLKID_MPLL3] =3D &axg_mpll3.hw, + [CLKID_DDR] =3D &axg_ddr.hw, + [CLKID_AUDIO_LOCKER] =3D &axg_audio_locker.hw, + [CLKID_MIPI_DSI_HOST] =3D &axg_mipi_dsi_host.hw, + [CLKID_ISA] =3D &axg_isa.hw, + [CLKID_PL301] =3D &axg_pl301.hw, + [CLKID_PERIPHS] =3D &axg_periphs.hw, + [CLKID_SPICC0] =3D &axg_spicc_0.hw, + [CLKID_I2C] =3D &axg_i2c.hw, + [CLKID_RNG0] =3D &axg_rng0.hw, + [CLKID_UART0] =3D &axg_uart0.hw, + [CLKID_MIPI_DSI_PHY] =3D &axg_mipi_dsi_phy.hw, + [CLKID_SPICC1] =3D &axg_spicc_1.hw, + [CLKID_PCIE_A] =3D &axg_pcie_a.hw, + [CLKID_PCIE_B] =3D &axg_pcie_b.hw, + [CLKID_HIU_IFACE] =3D &axg_hiu_reg.hw, + [CLKID_ASSIST_MISC] =3D &axg_assist_misc.hw, + [CLKID_SD_EMMC_B] =3D &axg_emmc_b.hw, + [CLKID_SD_EMMC_C] =3D &axg_emmc_c.hw, + [CLKID_DMA] =3D &axg_dma.hw, + [CLKID_SPI] =3D &axg_spi.hw, + [CLKID_AUDIO] =3D &axg_audio.hw, + [CLKID_ETH] =3D &axg_eth_core.hw, + [CLKID_UART1] =3D &axg_uart1.hw, + [CLKID_G2D] =3D &axg_g2d.hw, + [CLKID_USB0] =3D &axg_usb0.hw, + [CLKID_USB1] =3D &axg_usb1.hw, + [CLKID_RESET] =3D &axg_reset.hw, + [CLKID_USB] =3D &axg_usb_general.hw, + [CLKID_AHB_ARB0] =3D &axg_ahb_arb0.hw, + [CLKID_EFUSE] =3D &axg_efuse.hw, + [CLKID_BOOT_ROM] =3D &axg_boot_rom.hw, + [CLKID_AHB_DATA_BUS] =3D &axg_ahb_data_bus.hw, + [CLKID_AHB_CTRL_BUS] =3D &axg_ahb_ctrl_bus.hw, + [CLKID_USB1_DDR_BRIDGE] =3D &axg_usb1_to_ddr.hw, + [CLKID_USB0_DDR_BRIDGE] =3D &axg_usb0_to_ddr.hw, + [CLKID_MMC_PCLK] =3D &axg_mmc_pclk.hw, + [CLKID_VPU_INTR] =3D &axg_vpu_intr.hw, + [CLKID_SEC_AHB_AHB3_BRIDGE] =3D &axg_sec_ahb_ahb3_bridge.hw, + [CLKID_GIC] =3D &axg_gic.hw, + [CLKID_AO_MEDIA_CPU] =3D &axg_ao_media_cpu.hw, + [CLKID_AO_AHB_SRAM] =3D &axg_ao_ahb_sram.hw, + [CLKID_AO_AHB_BUS] =3D &axg_ao_ahb_bus.hw, + [CLKID_AO_IFACE] =3D &axg_ao_iface.hw, + [CLKID_AO_I2C] =3D &axg_ao_i2c.hw, + [CLKID_SD_EMMC_B_CLK0_SEL] =3D &axg_sd_emmc_b_clk0_sel.hw, + [CLKID_SD_EMMC_B_CLK0_DIV] =3D &axg_sd_emmc_b_clk0_div.hw, + [CLKID_SD_EMMC_B_CLK0] =3D &axg_sd_emmc_b_clk0.hw, + [CLKID_SD_EMMC_C_CLK0_SEL] =3D &axg_sd_emmc_c_clk0_sel.hw, + [CLKID_SD_EMMC_C_CLK0_DIV] =3D &axg_sd_emmc_c_clk0_div.hw, + [CLKID_SD_EMMC_C_CLK0] =3D &axg_sd_emmc_c_clk0.hw, + [CLKID_MPLL0_DIV] =3D &axg_mpll0_div.hw, + [CLKID_MPLL1_DIV] =3D &axg_mpll1_div.hw, + [CLKID_MPLL2_DIV] =3D &axg_mpll2_div.hw, + [CLKID_MPLL3_DIV] =3D &axg_mpll3_div.hw, + [CLKID_HIFI_PLL] =3D &axg_hifi_pll.hw, + [CLKID_MPLL_PREDIV] =3D &axg_mpll_prediv.hw, + [CLKID_FCLK_DIV2_DIV] =3D &axg_fclk_div2_div.hw, + [CLKID_FCLK_DIV3_DIV] =3D &axg_fclk_div3_div.hw, + [CLKID_FCLK_DIV4_DIV] =3D &axg_fclk_div4_div.hw, + [CLKID_FCLK_DIV5_DIV] =3D &axg_fclk_div5_div.hw, + [CLKID_FCLK_DIV7_DIV] =3D &axg_fclk_div7_div.hw, + [CLKID_PCIE_PLL] =3D &axg_pcie_pll.hw, + [CLKID_PCIE_MUX] =3D &axg_pcie_mux.hw, + [CLKID_PCIE_REF] =3D &axg_pcie_ref.hw, + [CLKID_PCIE_CML_EN0] =3D &axg_pcie_cml_en0.hw, + [CLKID_PCIE_CML_EN1] =3D &axg_pcie_cml_en1.hw, + [CLKID_GEN_CLK_SEL] =3D &axg_gen_clk_sel.hw, + [CLKID_GEN_CLK_DIV] =3D &axg_gen_clk_div.hw, + [CLKID_GEN_CLK] =3D &axg_gen_clk.hw, + [CLKID_SYS_PLL_DCO] =3D &axg_sys_pll_dco.hw, + [CLKID_FIXED_PLL_DCO] =3D &axg_fixed_pll_dco.hw, + [CLKID_GP0_PLL_DCO] =3D &axg_gp0_pll_dco.hw, + [CLKID_HIFI_PLL_DCO] =3D &axg_hifi_pll_dco.hw, + [CLKID_PCIE_PLL_DCO] =3D &axg_pcie_pll_dco.hw, + [CLKID_PCIE_PLL_OD] =3D &axg_pcie_pll_od.hw, + [CLKID_VPU_0_DIV] =3D &axg_vpu_0_div.hw, + [CLKID_VPU_0_SEL] =3D &axg_vpu_0_sel.hw, + [CLKID_VPU_0] =3D &axg_vpu_0.hw, + [CLKID_VPU_1_DIV] =3D &axg_vpu_1_div.hw, + [CLKID_VPU_1_SEL] =3D &axg_vpu_1_sel.hw, + [CLKID_VPU_1] =3D &axg_vpu_1.hw, + [CLKID_VPU] =3D &axg_vpu.hw, + [CLKID_VAPB_0_DIV] =3D &axg_vapb_0_div.hw, + [CLKID_VAPB_0_SEL] =3D &axg_vapb_0_sel.hw, + [CLKID_VAPB_0] =3D &axg_vapb_0.hw, + [CLKID_VAPB_1_DIV] =3D &axg_vapb_1_div.hw, + [CLKID_VAPB_1_SEL] =3D &axg_vapb_1_sel.hw, + [CLKID_VAPB_1] =3D &axg_vapb_1.hw, + [CLKID_VAPB_SEL] =3D &axg_vapb_sel.hw, + [CLKID_VAPB] =3D &axg_vapb.hw, + [CLKID_VCLK] =3D &axg_vclk.hw, + [CLKID_VCLK2] =3D &axg_vclk2.hw, + [CLKID_VCLK_SEL] =3D &axg_vclk_sel.hw, + [CLKID_VCLK2_SEL] =3D &axg_vclk2_sel.hw, + [CLKID_VCLK_INPUT] =3D &axg_vclk_input.hw, + [CLKID_VCLK2_INPUT] =3D &axg_vclk2_input.hw, + [CLKID_VCLK_DIV] =3D &axg_vclk_div.hw, + [CLKID_VCLK2_DIV] =3D &axg_vclk2_div.hw, + [CLKID_VCLK_DIV2_EN] =3D &axg_vclk_div2_en.hw, + [CLKID_VCLK_DIV4_EN] =3D &axg_vclk_div4_en.hw, + [CLKID_VCLK_DIV6_EN] =3D &axg_vclk_div6_en.hw, + [CLKID_VCLK_DIV12_EN] =3D &axg_vclk_div12_en.hw, + [CLKID_VCLK2_DIV2_EN] =3D &axg_vclk2_div2_en.hw, + [CLKID_VCLK2_DIV4_EN] =3D &axg_vclk2_div4_en.hw, + [CLKID_VCLK2_DIV6_EN] =3D &axg_vclk2_div6_en.hw, + [CLKID_VCLK2_DIV12_EN] =3D &axg_vclk2_div12_en.hw, + [CLKID_VCLK_DIV1] =3D &axg_vclk_div1.hw, + [CLKID_VCLK_DIV2] =3D &axg_vclk_div2.hw, + [CLKID_VCLK_DIV4] =3D &axg_vclk_div4.hw, + [CLKID_VCLK_DIV6] =3D &axg_vclk_div6.hw, + [CLKID_VCLK_DIV12] =3D &axg_vclk_div12.hw, + [CLKID_VCLK2_DIV1] =3D &axg_vclk2_div1.hw, + [CLKID_VCLK2_DIV2] =3D &axg_vclk2_div2.hw, + [CLKID_VCLK2_DIV4] =3D &axg_vclk2_div4.hw, + [CLKID_VCLK2_DIV6] =3D &axg_vclk2_div6.hw, + [CLKID_VCLK2_DIV12] =3D &axg_vclk2_div12.hw, + [CLKID_CTS_ENCL_SEL] =3D &axg_cts_encl_sel.hw, + [CLKID_CTS_ENCL] =3D &axg_cts_encl.hw, + [CLKID_VDIN_MEAS_SEL] =3D &axg_vdin_meas_sel.hw, + [CLKID_VDIN_MEAS_DIV] =3D &axg_vdin_meas_div.hw, + [CLKID_VDIN_MEAS] =3D &axg_vdin_meas.hw, }; =20 /* Convenience table to populate regmap in .probe */ @@ -2163,7 +2159,10 @@ static struct clk_regmap *const axg_clk_regmaps[] = =3D { static const struct meson_eeclkc_data axg_clkc_data =3D { .regmap_clks =3D axg_clk_regmaps, .regmap_clk_num =3D ARRAY_SIZE(axg_clk_regmaps), - .hw_onecell_data =3D &axg_hw_onecell_data, + .hw_clks =3D { + .hws =3D axg_hw_clks, + .num =3D ARRAY_SIZE(axg_hw_clks), + }, }; =20 =20 diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h index 23ea87964af2..39f9e2db82bd 100644 --- a/drivers/clk/meson/axg.h +++ b/drivers/clk/meson/axg.h @@ -160,8 +160,6 @@ #define CLKID_VDIN_MEAS_SEL 134 #define CLKID_VDIN_MEAS_DIV 135 =20 -#define NR_CLKS 137 - /* include the CLKIDs that have been made part of the DT binding */ #include =20 diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 310accf94830..e0e295645c9e 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -4244,746 +4244,734 @@ static MESON_GATE_RO(g12a_reset_sec, HHI_GCLK_OT= HER2, 3); static MESON_GATE_RO(g12a_sec_ahb_apb3, HHI_GCLK_OTHER2, 4); =20 /* Array of all clocks provided by this provider */ -static struct clk_hw_onecell_data g12a_hw_onecell_data =3D { - .hws =3D { - [CLKID_SYS_PLL] =3D &g12a_sys_pll.hw, - [CLKID_FIXED_PLL] =3D &g12a_fixed_pll.hw, - [CLKID_FCLK_DIV2] =3D &g12a_fclk_div2.hw, - [CLKID_FCLK_DIV3] =3D &g12a_fclk_div3.hw, - [CLKID_FCLK_DIV4] =3D &g12a_fclk_div4.hw, - [CLKID_FCLK_DIV5] =3D &g12a_fclk_div5.hw, - [CLKID_FCLK_DIV7] =3D &g12a_fclk_div7.hw, - [CLKID_FCLK_DIV2P5] =3D &g12a_fclk_div2p5.hw, - [CLKID_GP0_PLL] =3D &g12a_gp0_pll.hw, - [CLKID_MPEG_SEL] =3D &g12a_mpeg_clk_sel.hw, - [CLKID_MPEG_DIV] =3D &g12a_mpeg_clk_div.hw, - [CLKID_CLK81] =3D &g12a_clk81.hw, - [CLKID_MPLL0] =3D &g12a_mpll0.hw, - [CLKID_MPLL1] =3D &g12a_mpll1.hw, - [CLKID_MPLL2] =3D &g12a_mpll2.hw, - [CLKID_MPLL3] =3D &g12a_mpll3.hw, - [CLKID_DDR] =3D &g12a_ddr.hw, - [CLKID_DOS] =3D &g12a_dos.hw, - [CLKID_AUDIO_LOCKER] =3D &g12a_audio_locker.hw, - [CLKID_MIPI_DSI_HOST] =3D &g12a_mipi_dsi_host.hw, - [CLKID_ETH_PHY] =3D &g12a_eth_phy.hw, - [CLKID_ISA] =3D &g12a_isa.hw, - [CLKID_PL301] =3D &g12a_pl301.hw, - [CLKID_PERIPHS] =3D &g12a_periphs.hw, - [CLKID_SPICC0] =3D &g12a_spicc_0.hw, - [CLKID_I2C] =3D &g12a_i2c.hw, - [CLKID_SANA] =3D &g12a_sana.hw, - [CLKID_SD] =3D &g12a_sd.hw, - [CLKID_RNG0] =3D &g12a_rng0.hw, - [CLKID_UART0] =3D &g12a_uart0.hw, - [CLKID_SPICC1] =3D &g12a_spicc_1.hw, - [CLKID_HIU_IFACE] =3D &g12a_hiu_reg.hw, - [CLKID_MIPI_DSI_PHY] =3D &g12a_mipi_dsi_phy.hw, - [CLKID_ASSIST_MISC] =3D &g12a_assist_misc.hw, - [CLKID_SD_EMMC_A] =3D &g12a_emmc_a.hw, - [CLKID_SD_EMMC_B] =3D &g12a_emmc_b.hw, - [CLKID_SD_EMMC_C] =3D &g12a_emmc_c.hw, - [CLKID_AUDIO_CODEC] =3D &g12a_audio_codec.hw, - [CLKID_AUDIO] =3D &g12a_audio.hw, - [CLKID_ETH] =3D &g12a_eth_core.hw, - [CLKID_DEMUX] =3D &g12a_demux.hw, - [CLKID_AUDIO_IFIFO] =3D &g12a_audio_ififo.hw, - [CLKID_ADC] =3D &g12a_adc.hw, - [CLKID_UART1] =3D &g12a_uart1.hw, - [CLKID_G2D] =3D &g12a_g2d.hw, - [CLKID_RESET] =3D &g12a_reset.hw, - [CLKID_PCIE_COMB] =3D &g12a_pcie_comb.hw, - [CLKID_PARSER] =3D &g12a_parser.hw, - [CLKID_USB] =3D &g12a_usb_general.hw, - [CLKID_PCIE_PHY] =3D &g12a_pcie_phy.hw, - [CLKID_AHB_ARB0] =3D &g12a_ahb_arb0.hw, - [CLKID_AHB_DATA_BUS] =3D &g12a_ahb_data_bus.hw, - [CLKID_AHB_CTRL_BUS] =3D &g12a_ahb_ctrl_bus.hw, - [CLKID_HTX_HDCP22] =3D &g12a_htx_hdcp22.hw, - [CLKID_HTX_PCLK] =3D &g12a_htx_pclk.hw, - [CLKID_BT656] =3D &g12a_bt656.hw, - [CLKID_USB1_DDR_BRIDGE] =3D &g12a_usb1_to_ddr.hw, - [CLKID_MMC_PCLK] =3D &g12a_mmc_pclk.hw, - [CLKID_UART2] =3D &g12a_uart2.hw, - [CLKID_VPU_INTR] =3D &g12a_vpu_intr.hw, - [CLKID_GIC] =3D &g12a_gic.hw, - [CLKID_SD_EMMC_A_CLK0_SEL] =3D &g12a_sd_emmc_a_clk0_sel.hw, - [CLKID_SD_EMMC_A_CLK0_DIV] =3D &g12a_sd_emmc_a_clk0_div.hw, - [CLKID_SD_EMMC_A_CLK0] =3D &g12a_sd_emmc_a_clk0.hw, - [CLKID_SD_EMMC_B_CLK0_SEL] =3D &g12a_sd_emmc_b_clk0_sel.hw, - [CLKID_SD_EMMC_B_CLK0_DIV] =3D &g12a_sd_emmc_b_clk0_div.hw, - [CLKID_SD_EMMC_B_CLK0] =3D &g12a_sd_emmc_b_clk0.hw, - [CLKID_SD_EMMC_C_CLK0_SEL] =3D &g12a_sd_emmc_c_clk0_sel.hw, - [CLKID_SD_EMMC_C_CLK0_DIV] =3D &g12a_sd_emmc_c_clk0_div.hw, - [CLKID_SD_EMMC_C_CLK0] =3D &g12a_sd_emmc_c_clk0.hw, - [CLKID_MPLL0_DIV] =3D &g12a_mpll0_div.hw, - [CLKID_MPLL1_DIV] =3D &g12a_mpll1_div.hw, - [CLKID_MPLL2_DIV] =3D &g12a_mpll2_div.hw, - [CLKID_MPLL3_DIV] =3D &g12a_mpll3_div.hw, - [CLKID_FCLK_DIV2_DIV] =3D &g12a_fclk_div2_div.hw, - [CLKID_FCLK_DIV3_DIV] =3D &g12a_fclk_div3_div.hw, - [CLKID_FCLK_DIV4_DIV] =3D &g12a_fclk_div4_div.hw, - [CLKID_FCLK_DIV5_DIV] =3D &g12a_fclk_div5_div.hw, - [CLKID_FCLK_DIV7_DIV] =3D &g12a_fclk_div7_div.hw, - [CLKID_FCLK_DIV2P5_DIV] =3D &g12a_fclk_div2p5_div.hw, - [CLKID_HIFI_PLL] =3D &g12a_hifi_pll.hw, - [CLKID_VCLK2_VENCI0] =3D &g12a_vclk2_venci0.hw, - [CLKID_VCLK2_VENCI1] =3D &g12a_vclk2_venci1.hw, - [CLKID_VCLK2_VENCP0] =3D &g12a_vclk2_vencp0.hw, - [CLKID_VCLK2_VENCP1] =3D &g12a_vclk2_vencp1.hw, - [CLKID_VCLK2_VENCT0] =3D &g12a_vclk2_venct0.hw, - [CLKID_VCLK2_VENCT1] =3D &g12a_vclk2_venct1.hw, - [CLKID_VCLK2_OTHER] =3D &g12a_vclk2_other.hw, - [CLKID_VCLK2_ENCI] =3D &g12a_vclk2_enci.hw, - [CLKID_VCLK2_ENCP] =3D &g12a_vclk2_encp.hw, - [CLKID_DAC_CLK] =3D &g12a_dac_clk.hw, - [CLKID_AOCLK] =3D &g12a_aoclk_gate.hw, - [CLKID_IEC958] =3D &g12a_iec958_gate.hw, - [CLKID_ENC480P] =3D &g12a_enc480p.hw, - [CLKID_RNG1] =3D &g12a_rng1.hw, - [CLKID_VCLK2_ENCT] =3D &g12a_vclk2_enct.hw, - [CLKID_VCLK2_ENCL] =3D &g12a_vclk2_encl.hw, - [CLKID_VCLK2_VENCLMMC] =3D &g12a_vclk2_venclmmc.hw, - [CLKID_VCLK2_VENCL] =3D &g12a_vclk2_vencl.hw, - [CLKID_VCLK2_OTHER1] =3D &g12a_vclk2_other1.hw, - [CLKID_FIXED_PLL_DCO] =3D &g12a_fixed_pll_dco.hw, - [CLKID_SYS_PLL_DCO] =3D &g12a_sys_pll_dco.hw, - [CLKID_GP0_PLL_DCO] =3D &g12a_gp0_pll_dco.hw, - [CLKID_HIFI_PLL_DCO] =3D &g12a_hifi_pll_dco.hw, - [CLKID_DMA] =3D &g12a_dma.hw, - [CLKID_EFUSE] =3D &g12a_efuse.hw, - [CLKID_ROM_BOOT] =3D &g12a_rom_boot.hw, - [CLKID_RESET_SEC] =3D &g12a_reset_sec.hw, - [CLKID_SEC_AHB_APB3] =3D &g12a_sec_ahb_apb3.hw, - [CLKID_MPLL_PREDIV] =3D &g12a_mpll_prediv.hw, - [CLKID_VPU_0_SEL] =3D &g12a_vpu_0_sel.hw, - [CLKID_VPU_0_DIV] =3D &g12a_vpu_0_div.hw, - [CLKID_VPU_0] =3D &g12a_vpu_0.hw, - [CLKID_VPU_1_SEL] =3D &g12a_vpu_1_sel.hw, - [CLKID_VPU_1_DIV] =3D &g12a_vpu_1_div.hw, - [CLKID_VPU_1] =3D &g12a_vpu_1.hw, - [CLKID_VPU] =3D &g12a_vpu.hw, - [CLKID_VAPB_0_SEL] =3D &g12a_vapb_0_sel.hw, - [CLKID_VAPB_0_DIV] =3D &g12a_vapb_0_div.hw, - [CLKID_VAPB_0] =3D &g12a_vapb_0.hw, - [CLKID_VAPB_1_SEL] =3D &g12a_vapb_1_sel.hw, - [CLKID_VAPB_1_DIV] =3D &g12a_vapb_1_div.hw, - [CLKID_VAPB_1] =3D &g12a_vapb_1.hw, - [CLKID_VAPB_SEL] =3D &g12a_vapb_sel.hw, - [CLKID_VAPB] =3D &g12a_vapb.hw, - [CLKID_HDMI_PLL_DCO] =3D &g12a_hdmi_pll_dco.hw, - [CLKID_HDMI_PLL_OD] =3D &g12a_hdmi_pll_od.hw, - [CLKID_HDMI_PLL_OD2] =3D &g12a_hdmi_pll_od2.hw, - [CLKID_HDMI_PLL] =3D &g12a_hdmi_pll.hw, - [CLKID_VID_PLL] =3D &g12a_vid_pll_div.hw, - [CLKID_VID_PLL_SEL] =3D &g12a_vid_pll_sel.hw, - [CLKID_VID_PLL_DIV] =3D &g12a_vid_pll.hw, - [CLKID_VCLK_SEL] =3D &g12a_vclk_sel.hw, - [CLKID_VCLK2_SEL] =3D &g12a_vclk2_sel.hw, - [CLKID_VCLK_INPUT] =3D &g12a_vclk_input.hw, - [CLKID_VCLK2_INPUT] =3D &g12a_vclk2_input.hw, - [CLKID_VCLK_DIV] =3D &g12a_vclk_div.hw, - [CLKID_VCLK2_DIV] =3D &g12a_vclk2_div.hw, - [CLKID_VCLK] =3D &g12a_vclk.hw, - [CLKID_VCLK2] =3D &g12a_vclk2.hw, - [CLKID_VCLK_DIV1] =3D &g12a_vclk_div1.hw, - [CLKID_VCLK_DIV2_EN] =3D &g12a_vclk_div2_en.hw, - [CLKID_VCLK_DIV4_EN] =3D &g12a_vclk_div4_en.hw, - [CLKID_VCLK_DIV6_EN] =3D &g12a_vclk_div6_en.hw, - [CLKID_VCLK_DIV12_EN] =3D &g12a_vclk_div12_en.hw, - [CLKID_VCLK2_DIV1] =3D &g12a_vclk2_div1.hw, - [CLKID_VCLK2_DIV2_EN] =3D &g12a_vclk2_div2_en.hw, - [CLKID_VCLK2_DIV4_EN] =3D &g12a_vclk2_div4_en.hw, - [CLKID_VCLK2_DIV6_EN] =3D &g12a_vclk2_div6_en.hw, - [CLKID_VCLK2_DIV12_EN] =3D &g12a_vclk2_div12_en.hw, - [CLKID_VCLK_DIV2] =3D &g12a_vclk_div2.hw, - [CLKID_VCLK_DIV4] =3D &g12a_vclk_div4.hw, - [CLKID_VCLK_DIV6] =3D &g12a_vclk_div6.hw, - [CLKID_VCLK_DIV12] =3D &g12a_vclk_div12.hw, - [CLKID_VCLK2_DIV2] =3D &g12a_vclk2_div2.hw, - [CLKID_VCLK2_DIV4] =3D &g12a_vclk2_div4.hw, - [CLKID_VCLK2_DIV6] =3D &g12a_vclk2_div6.hw, - [CLKID_VCLK2_DIV12] =3D &g12a_vclk2_div12.hw, - [CLKID_CTS_ENCI_SEL] =3D &g12a_cts_enci_sel.hw, - [CLKID_CTS_ENCP_SEL] =3D &g12a_cts_encp_sel.hw, - [CLKID_CTS_VDAC_SEL] =3D &g12a_cts_vdac_sel.hw, - [CLKID_HDMI_TX_SEL] =3D &g12a_hdmi_tx_sel.hw, - [CLKID_CTS_ENCI] =3D &g12a_cts_enci.hw, - [CLKID_CTS_ENCP] =3D &g12a_cts_encp.hw, - [CLKID_CTS_VDAC] =3D &g12a_cts_vdac.hw, - [CLKID_HDMI_TX] =3D &g12a_hdmi_tx.hw, - [CLKID_HDMI_SEL] =3D &g12a_hdmi_sel.hw, - [CLKID_HDMI_DIV] =3D &g12a_hdmi_div.hw, - [CLKID_HDMI] =3D &g12a_hdmi.hw, - [CLKID_MALI_0_SEL] =3D &g12a_mali_0_sel.hw, - [CLKID_MALI_0_DIV] =3D &g12a_mali_0_div.hw, - [CLKID_MALI_0] =3D &g12a_mali_0.hw, - [CLKID_MALI_1_SEL] =3D &g12a_mali_1_sel.hw, - [CLKID_MALI_1_DIV] =3D &g12a_mali_1_div.hw, - [CLKID_MALI_1] =3D &g12a_mali_1.hw, - [CLKID_MALI] =3D &g12a_mali.hw, - [CLKID_MPLL_50M_DIV] =3D &g12a_mpll_50m_div.hw, - [CLKID_MPLL_50M] =3D &g12a_mpll_50m.hw, - [CLKID_SYS_PLL_DIV16_EN] =3D &g12a_sys_pll_div16_en.hw, - [CLKID_SYS_PLL_DIV16] =3D &g12a_sys_pll_div16.hw, - [CLKID_CPU_CLK_DYN0_SEL] =3D &g12a_cpu_clk_premux0.hw, - [CLKID_CPU_CLK_DYN0_DIV] =3D &g12a_cpu_clk_mux0_div.hw, - [CLKID_CPU_CLK_DYN0] =3D &g12a_cpu_clk_postmux0.hw, - [CLKID_CPU_CLK_DYN1_SEL] =3D &g12a_cpu_clk_premux1.hw, - [CLKID_CPU_CLK_DYN1_DIV] =3D &g12a_cpu_clk_mux1_div.hw, - [CLKID_CPU_CLK_DYN1] =3D &g12a_cpu_clk_postmux1.hw, - [CLKID_CPU_CLK_DYN] =3D &g12a_cpu_clk_dyn.hw, - [CLKID_CPU_CLK] =3D &g12a_cpu_clk.hw, - [CLKID_CPU_CLK_DIV16_EN] =3D &g12a_cpu_clk_div16_en.hw, - [CLKID_CPU_CLK_DIV16] =3D &g12a_cpu_clk_div16.hw, - [CLKID_CPU_CLK_APB_DIV] =3D &g12a_cpu_clk_apb_div.hw, - [CLKID_CPU_CLK_APB] =3D &g12a_cpu_clk_apb.hw, - [CLKID_CPU_CLK_ATB_DIV] =3D &g12a_cpu_clk_atb_div.hw, - [CLKID_CPU_CLK_ATB] =3D &g12a_cpu_clk_atb.hw, - [CLKID_CPU_CLK_AXI_DIV] =3D &g12a_cpu_clk_axi_div.hw, - [CLKID_CPU_CLK_AXI] =3D &g12a_cpu_clk_axi.hw, - [CLKID_CPU_CLK_TRACE_DIV] =3D &g12a_cpu_clk_trace_div.hw, - [CLKID_CPU_CLK_TRACE] =3D &g12a_cpu_clk_trace.hw, - [CLKID_PCIE_PLL_DCO] =3D &g12a_pcie_pll_dco.hw, - [CLKID_PCIE_PLL_DCO_DIV2] =3D &g12a_pcie_pll_dco_div2.hw, - [CLKID_PCIE_PLL_OD] =3D &g12a_pcie_pll_od.hw, - [CLKID_PCIE_PLL] =3D &g12a_pcie_pll.hw, - [CLKID_VDEC_1_SEL] =3D &g12a_vdec_1_sel.hw, - [CLKID_VDEC_1_DIV] =3D &g12a_vdec_1_div.hw, - [CLKID_VDEC_1] =3D &g12a_vdec_1.hw, - [CLKID_VDEC_HEVC_SEL] =3D &g12a_vdec_hevc_sel.hw, - [CLKID_VDEC_HEVC_DIV] =3D &g12a_vdec_hevc_div.hw, - [CLKID_VDEC_HEVC] =3D &g12a_vdec_hevc.hw, - [CLKID_VDEC_HEVCF_SEL] =3D &g12a_vdec_hevcf_sel.hw, - [CLKID_VDEC_HEVCF_DIV] =3D &g12a_vdec_hevcf_div.hw, - [CLKID_VDEC_HEVCF] =3D &g12a_vdec_hevcf.hw, - [CLKID_TS_DIV] =3D &g12a_ts_div.hw, - [CLKID_TS] =3D &g12a_ts.hw, - [CLKID_SPICC0_SCLK_SEL] =3D &g12a_spicc0_sclk_sel.hw, - [CLKID_SPICC0_SCLK_DIV] =3D &g12a_spicc0_sclk_div.hw, - [CLKID_SPICC0_SCLK] =3D &g12a_spicc0_sclk.hw, - [CLKID_SPICC1_SCLK_SEL] =3D &g12a_spicc1_sclk_sel.hw, - [CLKID_SPICC1_SCLK_DIV] =3D &g12a_spicc1_sclk_div.hw, - [CLKID_SPICC1_SCLK] =3D &g12a_spicc1_sclk.hw, - [CLKID_MIPI_DSI_PXCLK_SEL] =3D &g12a_mipi_dsi_pxclk_sel.hw, - [CLKID_MIPI_DSI_PXCLK_DIV] =3D &g12a_mipi_dsi_pxclk_div.hw, - [CLKID_MIPI_DSI_PXCLK] =3D &g12a_mipi_dsi_pxclk.hw, - [NR_CLKS] =3D NULL, - }, - .num =3D NR_CLKS, -}; - -static struct clk_hw_onecell_data g12b_hw_onecell_data =3D { - .hws =3D { - [CLKID_SYS_PLL] =3D &g12a_sys_pll.hw, - [CLKID_FIXED_PLL] =3D &g12a_fixed_pll.hw, - [CLKID_FCLK_DIV2] =3D &g12a_fclk_div2.hw, - [CLKID_FCLK_DIV3] =3D &g12a_fclk_div3.hw, - [CLKID_FCLK_DIV4] =3D &g12a_fclk_div4.hw, - [CLKID_FCLK_DIV5] =3D &g12a_fclk_div5.hw, - [CLKID_FCLK_DIV7] =3D &g12a_fclk_div7.hw, - [CLKID_FCLK_DIV2P5] =3D &g12a_fclk_div2p5.hw, - [CLKID_GP0_PLL] =3D &g12a_gp0_pll.hw, - [CLKID_MPEG_SEL] =3D &g12a_mpeg_clk_sel.hw, - [CLKID_MPEG_DIV] =3D &g12a_mpeg_clk_div.hw, - [CLKID_CLK81] =3D &g12a_clk81.hw, - [CLKID_MPLL0] =3D &g12a_mpll0.hw, - [CLKID_MPLL1] =3D &g12a_mpll1.hw, - [CLKID_MPLL2] =3D &g12a_mpll2.hw, - [CLKID_MPLL3] =3D &g12a_mpll3.hw, - [CLKID_DDR] =3D &g12a_ddr.hw, - [CLKID_DOS] =3D &g12a_dos.hw, - [CLKID_AUDIO_LOCKER] =3D &g12a_audio_locker.hw, - [CLKID_MIPI_DSI_HOST] =3D &g12a_mipi_dsi_host.hw, - [CLKID_ETH_PHY] =3D &g12a_eth_phy.hw, - [CLKID_ISA] =3D &g12a_isa.hw, - [CLKID_PL301] =3D &g12a_pl301.hw, - [CLKID_PERIPHS] =3D &g12a_periphs.hw, - [CLKID_SPICC0] =3D &g12a_spicc_0.hw, - [CLKID_I2C] =3D &g12a_i2c.hw, - [CLKID_SANA] =3D &g12a_sana.hw, - [CLKID_SD] =3D &g12a_sd.hw, - [CLKID_RNG0] =3D &g12a_rng0.hw, - [CLKID_UART0] =3D &g12a_uart0.hw, - [CLKID_SPICC1] =3D &g12a_spicc_1.hw, - [CLKID_HIU_IFACE] =3D &g12a_hiu_reg.hw, - [CLKID_MIPI_DSI_PHY] =3D &g12a_mipi_dsi_phy.hw, - [CLKID_ASSIST_MISC] =3D &g12a_assist_misc.hw, - [CLKID_SD_EMMC_A] =3D &g12a_emmc_a.hw, - [CLKID_SD_EMMC_B] =3D &g12a_emmc_b.hw, - [CLKID_SD_EMMC_C] =3D &g12a_emmc_c.hw, - [CLKID_AUDIO_CODEC] =3D &g12a_audio_codec.hw, - [CLKID_AUDIO] =3D &g12a_audio.hw, - [CLKID_ETH] =3D &g12a_eth_core.hw, - [CLKID_DEMUX] =3D &g12a_demux.hw, - [CLKID_AUDIO_IFIFO] =3D &g12a_audio_ififo.hw, - [CLKID_ADC] =3D &g12a_adc.hw, - [CLKID_UART1] =3D &g12a_uart1.hw, - [CLKID_G2D] =3D &g12a_g2d.hw, - [CLKID_RESET] =3D &g12a_reset.hw, - [CLKID_PCIE_COMB] =3D &g12a_pcie_comb.hw, - [CLKID_PARSER] =3D &g12a_parser.hw, - [CLKID_USB] =3D &g12a_usb_general.hw, - [CLKID_PCIE_PHY] =3D &g12a_pcie_phy.hw, - [CLKID_AHB_ARB0] =3D &g12a_ahb_arb0.hw, - [CLKID_AHB_DATA_BUS] =3D &g12a_ahb_data_bus.hw, - [CLKID_AHB_CTRL_BUS] =3D &g12a_ahb_ctrl_bus.hw, - [CLKID_HTX_HDCP22] =3D &g12a_htx_hdcp22.hw, - [CLKID_HTX_PCLK] =3D &g12a_htx_pclk.hw, - [CLKID_BT656] =3D &g12a_bt656.hw, - [CLKID_USB1_DDR_BRIDGE] =3D &g12a_usb1_to_ddr.hw, - [CLKID_MMC_PCLK] =3D &g12a_mmc_pclk.hw, - [CLKID_UART2] =3D &g12a_uart2.hw, - [CLKID_VPU_INTR] =3D &g12a_vpu_intr.hw, - [CLKID_GIC] =3D &g12a_gic.hw, - [CLKID_SD_EMMC_A_CLK0_SEL] =3D &g12a_sd_emmc_a_clk0_sel.hw, - [CLKID_SD_EMMC_A_CLK0_DIV] =3D &g12a_sd_emmc_a_clk0_div.hw, - [CLKID_SD_EMMC_A_CLK0] =3D &g12a_sd_emmc_a_clk0.hw, - [CLKID_SD_EMMC_B_CLK0_SEL] =3D &g12a_sd_emmc_b_clk0_sel.hw, - [CLKID_SD_EMMC_B_CLK0_DIV] =3D &g12a_sd_emmc_b_clk0_div.hw, - [CLKID_SD_EMMC_B_CLK0] =3D &g12a_sd_emmc_b_clk0.hw, - [CLKID_SD_EMMC_C_CLK0_SEL] =3D &g12a_sd_emmc_c_clk0_sel.hw, - [CLKID_SD_EMMC_C_CLK0_DIV] =3D &g12a_sd_emmc_c_clk0_div.hw, - [CLKID_SD_EMMC_C_CLK0] =3D &g12a_sd_emmc_c_clk0.hw, - [CLKID_MPLL0_DIV] =3D &g12a_mpll0_div.hw, - [CLKID_MPLL1_DIV] =3D &g12a_mpll1_div.hw, - [CLKID_MPLL2_DIV] =3D &g12a_mpll2_div.hw, - [CLKID_MPLL3_DIV] =3D &g12a_mpll3_div.hw, - [CLKID_FCLK_DIV2_DIV] =3D &g12a_fclk_div2_div.hw, - [CLKID_FCLK_DIV3_DIV] =3D &g12a_fclk_div3_div.hw, - [CLKID_FCLK_DIV4_DIV] =3D &g12a_fclk_div4_div.hw, - [CLKID_FCLK_DIV5_DIV] =3D &g12a_fclk_div5_div.hw, - [CLKID_FCLK_DIV7_DIV] =3D &g12a_fclk_div7_div.hw, - [CLKID_FCLK_DIV2P5_DIV] =3D &g12a_fclk_div2p5_div.hw, - [CLKID_HIFI_PLL] =3D &g12a_hifi_pll.hw, - [CLKID_VCLK2_VENCI0] =3D &g12a_vclk2_venci0.hw, - [CLKID_VCLK2_VENCI1] =3D &g12a_vclk2_venci1.hw, - [CLKID_VCLK2_VENCP0] =3D &g12a_vclk2_vencp0.hw, - [CLKID_VCLK2_VENCP1] =3D &g12a_vclk2_vencp1.hw, - [CLKID_VCLK2_VENCT0] =3D &g12a_vclk2_venct0.hw, - [CLKID_VCLK2_VENCT1] =3D &g12a_vclk2_venct1.hw, - [CLKID_VCLK2_OTHER] =3D &g12a_vclk2_other.hw, - [CLKID_VCLK2_ENCI] =3D &g12a_vclk2_enci.hw, - [CLKID_VCLK2_ENCP] =3D &g12a_vclk2_encp.hw, - [CLKID_DAC_CLK] =3D &g12a_dac_clk.hw, - [CLKID_AOCLK] =3D &g12a_aoclk_gate.hw, - [CLKID_IEC958] =3D &g12a_iec958_gate.hw, - [CLKID_ENC480P] =3D &g12a_enc480p.hw, - [CLKID_RNG1] =3D &g12a_rng1.hw, - [CLKID_VCLK2_ENCT] =3D &g12a_vclk2_enct.hw, - [CLKID_VCLK2_ENCL] =3D &g12a_vclk2_encl.hw, - [CLKID_VCLK2_VENCLMMC] =3D &g12a_vclk2_venclmmc.hw, - [CLKID_VCLK2_VENCL] =3D &g12a_vclk2_vencl.hw, - [CLKID_VCLK2_OTHER1] =3D &g12a_vclk2_other1.hw, - [CLKID_FIXED_PLL_DCO] =3D &g12a_fixed_pll_dco.hw, - [CLKID_SYS_PLL_DCO] =3D &g12a_sys_pll_dco.hw, - [CLKID_GP0_PLL_DCO] =3D &g12a_gp0_pll_dco.hw, - [CLKID_HIFI_PLL_DCO] =3D &g12a_hifi_pll_dco.hw, - [CLKID_DMA] =3D &g12a_dma.hw, - [CLKID_EFUSE] =3D &g12a_efuse.hw, - [CLKID_ROM_BOOT] =3D &g12a_rom_boot.hw, - [CLKID_RESET_SEC] =3D &g12a_reset_sec.hw, - [CLKID_SEC_AHB_APB3] =3D &g12a_sec_ahb_apb3.hw, - [CLKID_MPLL_PREDIV] =3D &g12a_mpll_prediv.hw, - [CLKID_VPU_0_SEL] =3D &g12a_vpu_0_sel.hw, - [CLKID_VPU_0_DIV] =3D &g12a_vpu_0_div.hw, - [CLKID_VPU_0] =3D &g12a_vpu_0.hw, - [CLKID_VPU_1_SEL] =3D &g12a_vpu_1_sel.hw, - [CLKID_VPU_1_DIV] =3D &g12a_vpu_1_div.hw, - [CLKID_VPU_1] =3D &g12a_vpu_1.hw, - [CLKID_VPU] =3D &g12a_vpu.hw, - [CLKID_VAPB_0_SEL] =3D &g12a_vapb_0_sel.hw, - [CLKID_VAPB_0_DIV] =3D &g12a_vapb_0_div.hw, - [CLKID_VAPB_0] =3D &g12a_vapb_0.hw, - [CLKID_VAPB_1_SEL] =3D &g12a_vapb_1_sel.hw, - [CLKID_VAPB_1_DIV] =3D &g12a_vapb_1_div.hw, - [CLKID_VAPB_1] =3D &g12a_vapb_1.hw, - [CLKID_VAPB_SEL] =3D &g12a_vapb_sel.hw, - [CLKID_VAPB] =3D &g12a_vapb.hw, - [CLKID_HDMI_PLL_DCO] =3D &g12a_hdmi_pll_dco.hw, - [CLKID_HDMI_PLL_OD] =3D &g12a_hdmi_pll_od.hw, - [CLKID_HDMI_PLL_OD2] =3D &g12a_hdmi_pll_od2.hw, - [CLKID_HDMI_PLL] =3D &g12a_hdmi_pll.hw, - [CLKID_VID_PLL] =3D &g12a_vid_pll_div.hw, - [CLKID_VID_PLL_SEL] =3D &g12a_vid_pll_sel.hw, - [CLKID_VID_PLL_DIV] =3D &g12a_vid_pll.hw, - [CLKID_VCLK_SEL] =3D &g12a_vclk_sel.hw, - [CLKID_VCLK2_SEL] =3D &g12a_vclk2_sel.hw, - [CLKID_VCLK_INPUT] =3D &g12a_vclk_input.hw, - [CLKID_VCLK2_INPUT] =3D &g12a_vclk2_input.hw, - [CLKID_VCLK_DIV] =3D &g12a_vclk_div.hw, - [CLKID_VCLK2_DIV] =3D &g12a_vclk2_div.hw, - [CLKID_VCLK] =3D &g12a_vclk.hw, - [CLKID_VCLK2] =3D &g12a_vclk2.hw, - [CLKID_VCLK_DIV1] =3D &g12a_vclk_div1.hw, - [CLKID_VCLK_DIV2_EN] =3D &g12a_vclk_div2_en.hw, - [CLKID_VCLK_DIV4_EN] =3D &g12a_vclk_div4_en.hw, - [CLKID_VCLK_DIV6_EN] =3D &g12a_vclk_div6_en.hw, - [CLKID_VCLK_DIV12_EN] =3D &g12a_vclk_div12_en.hw, - [CLKID_VCLK2_DIV1] =3D &g12a_vclk2_div1.hw, - [CLKID_VCLK2_DIV2_EN] =3D &g12a_vclk2_div2_en.hw, - [CLKID_VCLK2_DIV4_EN] =3D &g12a_vclk2_div4_en.hw, - [CLKID_VCLK2_DIV6_EN] =3D &g12a_vclk2_div6_en.hw, - [CLKID_VCLK2_DIV12_EN] =3D &g12a_vclk2_div12_en.hw, - [CLKID_VCLK_DIV2] =3D &g12a_vclk_div2.hw, - [CLKID_VCLK_DIV4] =3D &g12a_vclk_div4.hw, - [CLKID_VCLK_DIV6] =3D &g12a_vclk_div6.hw, - [CLKID_VCLK_DIV12] =3D &g12a_vclk_div12.hw, - [CLKID_VCLK2_DIV2] =3D &g12a_vclk2_div2.hw, - [CLKID_VCLK2_DIV4] =3D &g12a_vclk2_div4.hw, - [CLKID_VCLK2_DIV6] =3D &g12a_vclk2_div6.hw, - [CLKID_VCLK2_DIV12] =3D &g12a_vclk2_div12.hw, - [CLKID_CTS_ENCI_SEL] =3D &g12a_cts_enci_sel.hw, - [CLKID_CTS_ENCP_SEL] =3D &g12a_cts_encp_sel.hw, - [CLKID_CTS_VDAC_SEL] =3D &g12a_cts_vdac_sel.hw, - [CLKID_HDMI_TX_SEL] =3D &g12a_hdmi_tx_sel.hw, - [CLKID_CTS_ENCI] =3D &g12a_cts_enci.hw, - [CLKID_CTS_ENCP] =3D &g12a_cts_encp.hw, - [CLKID_CTS_VDAC] =3D &g12a_cts_vdac.hw, - [CLKID_HDMI_TX] =3D &g12a_hdmi_tx.hw, - [CLKID_HDMI_SEL] =3D &g12a_hdmi_sel.hw, - [CLKID_HDMI_DIV] =3D &g12a_hdmi_div.hw, - [CLKID_HDMI] =3D &g12a_hdmi.hw, - [CLKID_MALI_0_SEL] =3D &g12a_mali_0_sel.hw, - [CLKID_MALI_0_DIV] =3D &g12a_mali_0_div.hw, - [CLKID_MALI_0] =3D &g12a_mali_0.hw, - [CLKID_MALI_1_SEL] =3D &g12a_mali_1_sel.hw, - [CLKID_MALI_1_DIV] =3D &g12a_mali_1_div.hw, - [CLKID_MALI_1] =3D &g12a_mali_1.hw, - [CLKID_MALI] =3D &g12a_mali.hw, - [CLKID_MPLL_50M_DIV] =3D &g12a_mpll_50m_div.hw, - [CLKID_MPLL_50M] =3D &g12a_mpll_50m.hw, - [CLKID_SYS_PLL_DIV16_EN] =3D &g12a_sys_pll_div16_en.hw, - [CLKID_SYS_PLL_DIV16] =3D &g12a_sys_pll_div16.hw, - [CLKID_CPU_CLK_DYN0_SEL] =3D &g12a_cpu_clk_premux0.hw, - [CLKID_CPU_CLK_DYN0_DIV] =3D &g12a_cpu_clk_mux0_div.hw, - [CLKID_CPU_CLK_DYN0] =3D &g12a_cpu_clk_postmux0.hw, - [CLKID_CPU_CLK_DYN1_SEL] =3D &g12a_cpu_clk_premux1.hw, - [CLKID_CPU_CLK_DYN1_DIV] =3D &g12a_cpu_clk_mux1_div.hw, - [CLKID_CPU_CLK_DYN1] =3D &g12a_cpu_clk_postmux1.hw, - [CLKID_CPU_CLK_DYN] =3D &g12a_cpu_clk_dyn.hw, - [CLKID_CPU_CLK] =3D &g12b_cpu_clk.hw, - [CLKID_CPU_CLK_DIV16_EN] =3D &g12a_cpu_clk_div16_en.hw, - [CLKID_CPU_CLK_DIV16] =3D &g12a_cpu_clk_div16.hw, - [CLKID_CPU_CLK_APB_DIV] =3D &g12a_cpu_clk_apb_div.hw, - [CLKID_CPU_CLK_APB] =3D &g12a_cpu_clk_apb.hw, - [CLKID_CPU_CLK_ATB_DIV] =3D &g12a_cpu_clk_atb_div.hw, - [CLKID_CPU_CLK_ATB] =3D &g12a_cpu_clk_atb.hw, - [CLKID_CPU_CLK_AXI_DIV] =3D &g12a_cpu_clk_axi_div.hw, - [CLKID_CPU_CLK_AXI] =3D &g12a_cpu_clk_axi.hw, - [CLKID_CPU_CLK_TRACE_DIV] =3D &g12a_cpu_clk_trace_div.hw, - [CLKID_CPU_CLK_TRACE] =3D &g12a_cpu_clk_trace.hw, - [CLKID_PCIE_PLL_DCO] =3D &g12a_pcie_pll_dco.hw, - [CLKID_PCIE_PLL_DCO_DIV2] =3D &g12a_pcie_pll_dco_div2.hw, - [CLKID_PCIE_PLL_OD] =3D &g12a_pcie_pll_od.hw, - [CLKID_PCIE_PLL] =3D &g12a_pcie_pll.hw, - [CLKID_VDEC_1_SEL] =3D &g12a_vdec_1_sel.hw, - [CLKID_VDEC_1_DIV] =3D &g12a_vdec_1_div.hw, - [CLKID_VDEC_1] =3D &g12a_vdec_1.hw, - [CLKID_VDEC_HEVC_SEL] =3D &g12a_vdec_hevc_sel.hw, - [CLKID_VDEC_HEVC_DIV] =3D &g12a_vdec_hevc_div.hw, - [CLKID_VDEC_HEVC] =3D &g12a_vdec_hevc.hw, - [CLKID_VDEC_HEVCF_SEL] =3D &g12a_vdec_hevcf_sel.hw, - [CLKID_VDEC_HEVCF_DIV] =3D &g12a_vdec_hevcf_div.hw, - [CLKID_VDEC_HEVCF] =3D &g12a_vdec_hevcf.hw, - [CLKID_TS_DIV] =3D &g12a_ts_div.hw, - [CLKID_TS] =3D &g12a_ts.hw, - [CLKID_SYS1_PLL_DCO] =3D &g12b_sys1_pll_dco.hw, - [CLKID_SYS1_PLL] =3D &g12b_sys1_pll.hw, - [CLKID_SYS1_PLL_DIV16_EN] =3D &g12b_sys1_pll_div16_en.hw, - [CLKID_SYS1_PLL_DIV16] =3D &g12b_sys1_pll_div16.hw, - [CLKID_CPUB_CLK_DYN0_SEL] =3D &g12b_cpub_clk_premux0.hw, - [CLKID_CPUB_CLK_DYN0_DIV] =3D &g12b_cpub_clk_mux0_div.hw, - [CLKID_CPUB_CLK_DYN0] =3D &g12b_cpub_clk_postmux0.hw, - [CLKID_CPUB_CLK_DYN1_SEL] =3D &g12b_cpub_clk_premux1.hw, - [CLKID_CPUB_CLK_DYN1_DIV] =3D &g12b_cpub_clk_mux1_div.hw, - [CLKID_CPUB_CLK_DYN1] =3D &g12b_cpub_clk_postmux1.hw, - [CLKID_CPUB_CLK_DYN] =3D &g12b_cpub_clk_dyn.hw, - [CLKID_CPUB_CLK] =3D &g12b_cpub_clk.hw, - [CLKID_CPUB_CLK_DIV16_EN] =3D &g12b_cpub_clk_div16_en.hw, - [CLKID_CPUB_CLK_DIV16] =3D &g12b_cpub_clk_div16.hw, - [CLKID_CPUB_CLK_DIV2] =3D &g12b_cpub_clk_div2.hw, - [CLKID_CPUB_CLK_DIV3] =3D &g12b_cpub_clk_div3.hw, - [CLKID_CPUB_CLK_DIV4] =3D &g12b_cpub_clk_div4.hw, - [CLKID_CPUB_CLK_DIV5] =3D &g12b_cpub_clk_div5.hw, - [CLKID_CPUB_CLK_DIV6] =3D &g12b_cpub_clk_div6.hw, - [CLKID_CPUB_CLK_DIV7] =3D &g12b_cpub_clk_div7.hw, - [CLKID_CPUB_CLK_DIV8] =3D &g12b_cpub_clk_div8.hw, - [CLKID_CPUB_CLK_APB_SEL] =3D &g12b_cpub_clk_apb_sel.hw, - [CLKID_CPUB_CLK_APB] =3D &g12b_cpub_clk_apb.hw, - [CLKID_CPUB_CLK_ATB_SEL] =3D &g12b_cpub_clk_atb_sel.hw, - [CLKID_CPUB_CLK_ATB] =3D &g12b_cpub_clk_atb.hw, - [CLKID_CPUB_CLK_AXI_SEL] =3D &g12b_cpub_clk_axi_sel.hw, - [CLKID_CPUB_CLK_AXI] =3D &g12b_cpub_clk_axi.hw, - [CLKID_CPUB_CLK_TRACE_SEL] =3D &g12b_cpub_clk_trace_sel.hw, - [CLKID_CPUB_CLK_TRACE] =3D &g12b_cpub_clk_trace.hw, - [CLKID_SPICC0_SCLK_SEL] =3D &g12a_spicc0_sclk_sel.hw, - [CLKID_SPICC0_SCLK_DIV] =3D &g12a_spicc0_sclk_div.hw, - [CLKID_SPICC0_SCLK] =3D &g12a_spicc0_sclk.hw, - [CLKID_SPICC1_SCLK_SEL] =3D &g12a_spicc1_sclk_sel.hw, - [CLKID_SPICC1_SCLK_DIV] =3D &g12a_spicc1_sclk_div.hw, - [CLKID_SPICC1_SCLK] =3D &g12a_spicc1_sclk.hw, - [CLKID_NNA_AXI_CLK_SEL] =3D &sm1_nna_axi_clk_sel.hw, - [CLKID_NNA_AXI_CLK_DIV] =3D &sm1_nna_axi_clk_div.hw, - [CLKID_NNA_AXI_CLK] =3D &sm1_nna_axi_clk.hw, - [CLKID_NNA_CORE_CLK_SEL] =3D &sm1_nna_core_clk_sel.hw, - [CLKID_NNA_CORE_CLK_DIV] =3D &sm1_nna_core_clk_div.hw, - [CLKID_NNA_CORE_CLK] =3D &sm1_nna_core_clk.hw, - [CLKID_MIPI_DSI_PXCLK_SEL] =3D &g12a_mipi_dsi_pxclk_sel.hw, - [CLKID_MIPI_DSI_PXCLK_DIV] =3D &g12a_mipi_dsi_pxclk_div.hw, - [CLKID_MIPI_DSI_PXCLK] =3D &g12a_mipi_dsi_pxclk.hw, - [NR_CLKS] =3D NULL, - }, - .num =3D NR_CLKS, -}; - -static struct clk_hw_onecell_data sm1_hw_onecell_data =3D { - .hws =3D { - [CLKID_SYS_PLL] =3D &g12a_sys_pll.hw, - [CLKID_FIXED_PLL] =3D &g12a_fixed_pll.hw, - [CLKID_FCLK_DIV2] =3D &g12a_fclk_div2.hw, - [CLKID_FCLK_DIV3] =3D &g12a_fclk_div3.hw, - [CLKID_FCLK_DIV4] =3D &g12a_fclk_div4.hw, - [CLKID_FCLK_DIV5] =3D &g12a_fclk_div5.hw, - [CLKID_FCLK_DIV7] =3D &g12a_fclk_div7.hw, - [CLKID_FCLK_DIV2P5] =3D &g12a_fclk_div2p5.hw, - [CLKID_GP0_PLL] =3D &g12a_gp0_pll.hw, - [CLKID_MPEG_SEL] =3D &g12a_mpeg_clk_sel.hw, - [CLKID_MPEG_DIV] =3D &g12a_mpeg_clk_div.hw, - [CLKID_CLK81] =3D &g12a_clk81.hw, - [CLKID_MPLL0] =3D &g12a_mpll0.hw, - [CLKID_MPLL1] =3D &g12a_mpll1.hw, - [CLKID_MPLL2] =3D &g12a_mpll2.hw, - [CLKID_MPLL3] =3D &g12a_mpll3.hw, - [CLKID_DDR] =3D &g12a_ddr.hw, - [CLKID_DOS] =3D &g12a_dos.hw, - [CLKID_AUDIO_LOCKER] =3D &g12a_audio_locker.hw, - [CLKID_MIPI_DSI_HOST] =3D &g12a_mipi_dsi_host.hw, - [CLKID_ETH_PHY] =3D &g12a_eth_phy.hw, - [CLKID_ISA] =3D &g12a_isa.hw, - [CLKID_PL301] =3D &g12a_pl301.hw, - [CLKID_PERIPHS] =3D &g12a_periphs.hw, - [CLKID_SPICC0] =3D &g12a_spicc_0.hw, - [CLKID_I2C] =3D &g12a_i2c.hw, - [CLKID_SANA] =3D &g12a_sana.hw, - [CLKID_SD] =3D &g12a_sd.hw, - [CLKID_RNG0] =3D &g12a_rng0.hw, - [CLKID_UART0] =3D &g12a_uart0.hw, - [CLKID_SPICC1] =3D &g12a_spicc_1.hw, - [CLKID_HIU_IFACE] =3D &g12a_hiu_reg.hw, - [CLKID_MIPI_DSI_PHY] =3D &g12a_mipi_dsi_phy.hw, - [CLKID_ASSIST_MISC] =3D &g12a_assist_misc.hw, - [CLKID_SD_EMMC_A] =3D &g12a_emmc_a.hw, - [CLKID_SD_EMMC_B] =3D &g12a_emmc_b.hw, - [CLKID_SD_EMMC_C] =3D &g12a_emmc_c.hw, - [CLKID_AUDIO_CODEC] =3D &g12a_audio_codec.hw, - [CLKID_AUDIO] =3D &g12a_audio.hw, - [CLKID_ETH] =3D &g12a_eth_core.hw, - [CLKID_DEMUX] =3D &g12a_demux.hw, - [CLKID_AUDIO_IFIFO] =3D &g12a_audio_ififo.hw, - [CLKID_ADC] =3D &g12a_adc.hw, - [CLKID_UART1] =3D &g12a_uart1.hw, - [CLKID_G2D] =3D &g12a_g2d.hw, - [CLKID_RESET] =3D &g12a_reset.hw, - [CLKID_PCIE_COMB] =3D &g12a_pcie_comb.hw, - [CLKID_PARSER] =3D &g12a_parser.hw, - [CLKID_USB] =3D &g12a_usb_general.hw, - [CLKID_PCIE_PHY] =3D &g12a_pcie_phy.hw, - [CLKID_AHB_ARB0] =3D &g12a_ahb_arb0.hw, - [CLKID_AHB_DATA_BUS] =3D &g12a_ahb_data_bus.hw, - [CLKID_AHB_CTRL_BUS] =3D &g12a_ahb_ctrl_bus.hw, - [CLKID_HTX_HDCP22] =3D &g12a_htx_hdcp22.hw, - [CLKID_HTX_PCLK] =3D &g12a_htx_pclk.hw, - [CLKID_BT656] =3D &g12a_bt656.hw, - [CLKID_USB1_DDR_BRIDGE] =3D &g12a_usb1_to_ddr.hw, - [CLKID_MMC_PCLK] =3D &g12a_mmc_pclk.hw, - [CLKID_UART2] =3D &g12a_uart2.hw, - [CLKID_VPU_INTR] =3D &g12a_vpu_intr.hw, - [CLKID_GIC] =3D &g12a_gic.hw, - [CLKID_SD_EMMC_A_CLK0_SEL] =3D &g12a_sd_emmc_a_clk0_sel.hw, - [CLKID_SD_EMMC_A_CLK0_DIV] =3D &g12a_sd_emmc_a_clk0_div.hw, - [CLKID_SD_EMMC_A_CLK0] =3D &g12a_sd_emmc_a_clk0.hw, - [CLKID_SD_EMMC_B_CLK0_SEL] =3D &g12a_sd_emmc_b_clk0_sel.hw, - [CLKID_SD_EMMC_B_CLK0_DIV] =3D &g12a_sd_emmc_b_clk0_div.hw, - [CLKID_SD_EMMC_B_CLK0] =3D &g12a_sd_emmc_b_clk0.hw, - [CLKID_SD_EMMC_C_CLK0_SEL] =3D &g12a_sd_emmc_c_clk0_sel.hw, - [CLKID_SD_EMMC_C_CLK0_DIV] =3D &g12a_sd_emmc_c_clk0_div.hw, - [CLKID_SD_EMMC_C_CLK0] =3D &g12a_sd_emmc_c_clk0.hw, - [CLKID_MPLL0_DIV] =3D &g12a_mpll0_div.hw, - [CLKID_MPLL1_DIV] =3D &g12a_mpll1_div.hw, - [CLKID_MPLL2_DIV] =3D &g12a_mpll2_div.hw, - [CLKID_MPLL3_DIV] =3D &g12a_mpll3_div.hw, - [CLKID_FCLK_DIV2_DIV] =3D &g12a_fclk_div2_div.hw, - [CLKID_FCLK_DIV3_DIV] =3D &g12a_fclk_div3_div.hw, - [CLKID_FCLK_DIV4_DIV] =3D &g12a_fclk_div4_div.hw, - [CLKID_FCLK_DIV5_DIV] =3D &g12a_fclk_div5_div.hw, - [CLKID_FCLK_DIV7_DIV] =3D &g12a_fclk_div7_div.hw, - [CLKID_FCLK_DIV2P5_DIV] =3D &g12a_fclk_div2p5_div.hw, - [CLKID_HIFI_PLL] =3D &g12a_hifi_pll.hw, - [CLKID_VCLK2_VENCI0] =3D &g12a_vclk2_venci0.hw, - [CLKID_VCLK2_VENCI1] =3D &g12a_vclk2_venci1.hw, - [CLKID_VCLK2_VENCP0] =3D &g12a_vclk2_vencp0.hw, - [CLKID_VCLK2_VENCP1] =3D &g12a_vclk2_vencp1.hw, - [CLKID_VCLK2_VENCT0] =3D &g12a_vclk2_venct0.hw, - [CLKID_VCLK2_VENCT1] =3D &g12a_vclk2_venct1.hw, - [CLKID_VCLK2_OTHER] =3D &g12a_vclk2_other.hw, - [CLKID_VCLK2_ENCI] =3D &g12a_vclk2_enci.hw, - [CLKID_VCLK2_ENCP] =3D &g12a_vclk2_encp.hw, - [CLKID_DAC_CLK] =3D &g12a_dac_clk.hw, - [CLKID_AOCLK] =3D &g12a_aoclk_gate.hw, - [CLKID_IEC958] =3D &g12a_iec958_gate.hw, - [CLKID_ENC480P] =3D &g12a_enc480p.hw, - [CLKID_RNG1] =3D &g12a_rng1.hw, - [CLKID_VCLK2_ENCT] =3D &g12a_vclk2_enct.hw, - [CLKID_VCLK2_ENCL] =3D &g12a_vclk2_encl.hw, - [CLKID_VCLK2_VENCLMMC] =3D &g12a_vclk2_venclmmc.hw, - [CLKID_VCLK2_VENCL] =3D &g12a_vclk2_vencl.hw, - [CLKID_VCLK2_OTHER1] =3D &g12a_vclk2_other1.hw, - [CLKID_FIXED_PLL_DCO] =3D &g12a_fixed_pll_dco.hw, - [CLKID_SYS_PLL_DCO] =3D &g12a_sys_pll_dco.hw, - [CLKID_GP0_PLL_DCO] =3D &g12a_gp0_pll_dco.hw, - [CLKID_HIFI_PLL_DCO] =3D &g12a_hifi_pll_dco.hw, - [CLKID_DMA] =3D &g12a_dma.hw, - [CLKID_EFUSE] =3D &g12a_efuse.hw, - [CLKID_ROM_BOOT] =3D &g12a_rom_boot.hw, - [CLKID_RESET_SEC] =3D &g12a_reset_sec.hw, - [CLKID_SEC_AHB_APB3] =3D &g12a_sec_ahb_apb3.hw, - [CLKID_MPLL_PREDIV] =3D &g12a_mpll_prediv.hw, - [CLKID_VPU_0_SEL] =3D &g12a_vpu_0_sel.hw, - [CLKID_VPU_0_DIV] =3D &g12a_vpu_0_div.hw, - [CLKID_VPU_0] =3D &g12a_vpu_0.hw, - [CLKID_VPU_1_SEL] =3D &g12a_vpu_1_sel.hw, - [CLKID_VPU_1_DIV] =3D &g12a_vpu_1_div.hw, - [CLKID_VPU_1] =3D &g12a_vpu_1.hw, - [CLKID_VPU] =3D &g12a_vpu.hw, - [CLKID_VAPB_0_SEL] =3D &g12a_vapb_0_sel.hw, - [CLKID_VAPB_0_DIV] =3D &g12a_vapb_0_div.hw, - [CLKID_VAPB_0] =3D &g12a_vapb_0.hw, - [CLKID_VAPB_1_SEL] =3D &g12a_vapb_1_sel.hw, - [CLKID_VAPB_1_DIV] =3D &g12a_vapb_1_div.hw, - [CLKID_VAPB_1] =3D &g12a_vapb_1.hw, - [CLKID_VAPB_SEL] =3D &g12a_vapb_sel.hw, - [CLKID_VAPB] =3D &g12a_vapb.hw, - [CLKID_HDMI_PLL_DCO] =3D &g12a_hdmi_pll_dco.hw, - [CLKID_HDMI_PLL_OD] =3D &g12a_hdmi_pll_od.hw, - [CLKID_HDMI_PLL_OD2] =3D &g12a_hdmi_pll_od2.hw, - [CLKID_HDMI_PLL] =3D &g12a_hdmi_pll.hw, - [CLKID_VID_PLL] =3D &g12a_vid_pll_div.hw, - [CLKID_VID_PLL_SEL] =3D &g12a_vid_pll_sel.hw, - [CLKID_VID_PLL_DIV] =3D &g12a_vid_pll.hw, - [CLKID_VCLK_SEL] =3D &g12a_vclk_sel.hw, - [CLKID_VCLK2_SEL] =3D &g12a_vclk2_sel.hw, - [CLKID_VCLK_INPUT] =3D &g12a_vclk_input.hw, - [CLKID_VCLK2_INPUT] =3D &g12a_vclk2_input.hw, - [CLKID_VCLK_DIV] =3D &g12a_vclk_div.hw, - [CLKID_VCLK2_DIV] =3D &g12a_vclk2_div.hw, - [CLKID_VCLK] =3D &g12a_vclk.hw, - [CLKID_VCLK2] =3D &g12a_vclk2.hw, - [CLKID_VCLK_DIV1] =3D &g12a_vclk_div1.hw, - [CLKID_VCLK_DIV2_EN] =3D &g12a_vclk_div2_en.hw, - [CLKID_VCLK_DIV4_EN] =3D &g12a_vclk_div4_en.hw, - [CLKID_VCLK_DIV6_EN] =3D &g12a_vclk_div6_en.hw, - [CLKID_VCLK_DIV12_EN] =3D &g12a_vclk_div12_en.hw, - [CLKID_VCLK2_DIV1] =3D &g12a_vclk2_div1.hw, - [CLKID_VCLK2_DIV2_EN] =3D &g12a_vclk2_div2_en.hw, - [CLKID_VCLK2_DIV4_EN] =3D &g12a_vclk2_div4_en.hw, - [CLKID_VCLK2_DIV6_EN] =3D &g12a_vclk2_div6_en.hw, - [CLKID_VCLK2_DIV12_EN] =3D &g12a_vclk2_div12_en.hw, - [CLKID_VCLK_DIV2] =3D &g12a_vclk_div2.hw, - [CLKID_VCLK_DIV4] =3D &g12a_vclk_div4.hw, - [CLKID_VCLK_DIV6] =3D &g12a_vclk_div6.hw, - [CLKID_VCLK_DIV12] =3D &g12a_vclk_div12.hw, - [CLKID_VCLK2_DIV2] =3D &g12a_vclk2_div2.hw, - [CLKID_VCLK2_DIV4] =3D &g12a_vclk2_div4.hw, - [CLKID_VCLK2_DIV6] =3D &g12a_vclk2_div6.hw, - [CLKID_VCLK2_DIV12] =3D &g12a_vclk2_div12.hw, - [CLKID_CTS_ENCI_SEL] =3D &g12a_cts_enci_sel.hw, - [CLKID_CTS_ENCP_SEL] =3D &g12a_cts_encp_sel.hw, - [CLKID_CTS_VDAC_SEL] =3D &g12a_cts_vdac_sel.hw, - [CLKID_HDMI_TX_SEL] =3D &g12a_hdmi_tx_sel.hw, - [CLKID_CTS_ENCI] =3D &g12a_cts_enci.hw, - [CLKID_CTS_ENCP] =3D &g12a_cts_encp.hw, - [CLKID_CTS_VDAC] =3D &g12a_cts_vdac.hw, - [CLKID_HDMI_TX] =3D &g12a_hdmi_tx.hw, - [CLKID_HDMI_SEL] =3D &g12a_hdmi_sel.hw, - [CLKID_HDMI_DIV] =3D &g12a_hdmi_div.hw, - [CLKID_HDMI] =3D &g12a_hdmi.hw, - [CLKID_MALI_0_SEL] =3D &g12a_mali_0_sel.hw, - [CLKID_MALI_0_DIV] =3D &g12a_mali_0_div.hw, - [CLKID_MALI_0] =3D &g12a_mali_0.hw, - [CLKID_MALI_1_SEL] =3D &g12a_mali_1_sel.hw, - [CLKID_MALI_1_DIV] =3D &g12a_mali_1_div.hw, - [CLKID_MALI_1] =3D &g12a_mali_1.hw, - [CLKID_MALI] =3D &g12a_mali.hw, - [CLKID_MPLL_50M_DIV] =3D &g12a_mpll_50m_div.hw, - [CLKID_MPLL_50M] =3D &g12a_mpll_50m.hw, - [CLKID_SYS_PLL_DIV16_EN] =3D &g12a_sys_pll_div16_en.hw, - [CLKID_SYS_PLL_DIV16] =3D &g12a_sys_pll_div16.hw, - [CLKID_CPU_CLK_DYN0_SEL] =3D &g12a_cpu_clk_premux0.hw, - [CLKID_CPU_CLK_DYN0_DIV] =3D &g12a_cpu_clk_mux0_div.hw, - [CLKID_CPU_CLK_DYN0] =3D &g12a_cpu_clk_postmux0.hw, - [CLKID_CPU_CLK_DYN1_SEL] =3D &g12a_cpu_clk_premux1.hw, - [CLKID_CPU_CLK_DYN1_DIV] =3D &g12a_cpu_clk_mux1_div.hw, - [CLKID_CPU_CLK_DYN1] =3D &g12a_cpu_clk_postmux1.hw, - [CLKID_CPU_CLK_DYN] =3D &g12a_cpu_clk_dyn.hw, - [CLKID_CPU_CLK] =3D &g12a_cpu_clk.hw, - [CLKID_CPU_CLK_DIV16_EN] =3D &g12a_cpu_clk_div16_en.hw, - [CLKID_CPU_CLK_DIV16] =3D &g12a_cpu_clk_div16.hw, - [CLKID_CPU_CLK_APB_DIV] =3D &g12a_cpu_clk_apb_div.hw, - [CLKID_CPU_CLK_APB] =3D &g12a_cpu_clk_apb.hw, - [CLKID_CPU_CLK_ATB_DIV] =3D &g12a_cpu_clk_atb_div.hw, - [CLKID_CPU_CLK_ATB] =3D &g12a_cpu_clk_atb.hw, - [CLKID_CPU_CLK_AXI_DIV] =3D &g12a_cpu_clk_axi_div.hw, - [CLKID_CPU_CLK_AXI] =3D &g12a_cpu_clk_axi.hw, - [CLKID_CPU_CLK_TRACE_DIV] =3D &g12a_cpu_clk_trace_div.hw, - [CLKID_CPU_CLK_TRACE] =3D &g12a_cpu_clk_trace.hw, - [CLKID_PCIE_PLL_DCO] =3D &g12a_pcie_pll_dco.hw, - [CLKID_PCIE_PLL_DCO_DIV2] =3D &g12a_pcie_pll_dco_div2.hw, - [CLKID_PCIE_PLL_OD] =3D &g12a_pcie_pll_od.hw, - [CLKID_PCIE_PLL] =3D &g12a_pcie_pll.hw, - [CLKID_VDEC_1_SEL] =3D &g12a_vdec_1_sel.hw, - [CLKID_VDEC_1_DIV] =3D &g12a_vdec_1_div.hw, - [CLKID_VDEC_1] =3D &g12a_vdec_1.hw, - [CLKID_VDEC_HEVC_SEL] =3D &g12a_vdec_hevc_sel.hw, - [CLKID_VDEC_HEVC_DIV] =3D &g12a_vdec_hevc_div.hw, - [CLKID_VDEC_HEVC] =3D &g12a_vdec_hevc.hw, - [CLKID_VDEC_HEVCF_SEL] =3D &g12a_vdec_hevcf_sel.hw, - [CLKID_VDEC_HEVCF_DIV] =3D &g12a_vdec_hevcf_div.hw, - [CLKID_VDEC_HEVCF] =3D &g12a_vdec_hevcf.hw, - [CLKID_TS_DIV] =3D &g12a_ts_div.hw, - [CLKID_TS] =3D &g12a_ts.hw, - [CLKID_GP1_PLL_DCO] =3D &sm1_gp1_pll_dco.hw, - [CLKID_GP1_PLL] =3D &sm1_gp1_pll.hw, - [CLKID_DSU_CLK_DYN0_SEL] =3D &sm1_dsu_clk_premux0.hw, - [CLKID_DSU_CLK_DYN0_DIV] =3D &sm1_dsu_clk_premux1.hw, - [CLKID_DSU_CLK_DYN0] =3D &sm1_dsu_clk_mux0_div.hw, - [CLKID_DSU_CLK_DYN1_SEL] =3D &sm1_dsu_clk_postmux0.hw, - [CLKID_DSU_CLK_DYN1_DIV] =3D &sm1_dsu_clk_mux1_div.hw, - [CLKID_DSU_CLK_DYN1] =3D &sm1_dsu_clk_postmux1.hw, - [CLKID_DSU_CLK_DYN] =3D &sm1_dsu_clk_dyn.hw, - [CLKID_DSU_CLK_FINAL] =3D &sm1_dsu_final_clk.hw, - [CLKID_DSU_CLK] =3D &sm1_dsu_clk.hw, - [CLKID_CPU1_CLK] =3D &sm1_cpu1_clk.hw, - [CLKID_CPU2_CLK] =3D &sm1_cpu2_clk.hw, - [CLKID_CPU3_CLK] =3D &sm1_cpu3_clk.hw, - [CLKID_SPICC0_SCLK_SEL] =3D &g12a_spicc0_sclk_sel.hw, - [CLKID_SPICC0_SCLK_DIV] =3D &g12a_spicc0_sclk_div.hw, - [CLKID_SPICC0_SCLK] =3D &g12a_spicc0_sclk.hw, - [CLKID_SPICC1_SCLK_SEL] =3D &g12a_spicc1_sclk_sel.hw, - [CLKID_SPICC1_SCLK_DIV] =3D &g12a_spicc1_sclk_div.hw, - [CLKID_SPICC1_SCLK] =3D &g12a_spicc1_sclk.hw, - [CLKID_NNA_AXI_CLK_SEL] =3D &sm1_nna_axi_clk_sel.hw, - [CLKID_NNA_AXI_CLK_DIV] =3D &sm1_nna_axi_clk_div.hw, - [CLKID_NNA_AXI_CLK] =3D &sm1_nna_axi_clk.hw, - [CLKID_NNA_CORE_CLK_SEL] =3D &sm1_nna_core_clk_sel.hw, - [CLKID_NNA_CORE_CLK_DIV] =3D &sm1_nna_core_clk_div.hw, - [CLKID_NNA_CORE_CLK] =3D &sm1_nna_core_clk.hw, - [CLKID_MIPI_DSI_PXCLK_SEL] =3D &g12a_mipi_dsi_pxclk_sel.hw, - [CLKID_MIPI_DSI_PXCLK_DIV] =3D &g12a_mipi_dsi_pxclk_div.hw, - [CLKID_MIPI_DSI_PXCLK] =3D &g12a_mipi_dsi_pxclk.hw, - [NR_CLKS] =3D NULL, - }, - .num =3D NR_CLKS, +static struct clk_hw *g12a_hw_clks[] =3D { + [CLKID_SYS_PLL] =3D &g12a_sys_pll.hw, + [CLKID_FIXED_PLL] =3D &g12a_fixed_pll.hw, + [CLKID_FCLK_DIV2] =3D &g12a_fclk_div2.hw, + [CLKID_FCLK_DIV3] =3D &g12a_fclk_div3.hw, + [CLKID_FCLK_DIV4] =3D &g12a_fclk_div4.hw, + [CLKID_FCLK_DIV5] =3D &g12a_fclk_div5.hw, + [CLKID_FCLK_DIV7] =3D &g12a_fclk_div7.hw, + [CLKID_FCLK_DIV2P5] =3D &g12a_fclk_div2p5.hw, + [CLKID_GP0_PLL] =3D &g12a_gp0_pll.hw, + [CLKID_MPEG_SEL] =3D &g12a_mpeg_clk_sel.hw, + [CLKID_MPEG_DIV] =3D &g12a_mpeg_clk_div.hw, + [CLKID_CLK81] =3D &g12a_clk81.hw, + [CLKID_MPLL0] =3D &g12a_mpll0.hw, + [CLKID_MPLL1] =3D &g12a_mpll1.hw, + [CLKID_MPLL2] =3D &g12a_mpll2.hw, + [CLKID_MPLL3] =3D &g12a_mpll3.hw, + [CLKID_DDR] =3D &g12a_ddr.hw, + [CLKID_DOS] =3D &g12a_dos.hw, + [CLKID_AUDIO_LOCKER] =3D &g12a_audio_locker.hw, + [CLKID_MIPI_DSI_HOST] =3D &g12a_mipi_dsi_host.hw, + [CLKID_ETH_PHY] =3D &g12a_eth_phy.hw, + [CLKID_ISA] =3D &g12a_isa.hw, + [CLKID_PL301] =3D &g12a_pl301.hw, + [CLKID_PERIPHS] =3D &g12a_periphs.hw, + [CLKID_SPICC0] =3D &g12a_spicc_0.hw, + [CLKID_I2C] =3D &g12a_i2c.hw, + [CLKID_SANA] =3D &g12a_sana.hw, + [CLKID_SD] =3D &g12a_sd.hw, + [CLKID_RNG0] =3D &g12a_rng0.hw, + [CLKID_UART0] =3D &g12a_uart0.hw, + [CLKID_SPICC1] =3D &g12a_spicc_1.hw, + [CLKID_HIU_IFACE] =3D &g12a_hiu_reg.hw, + [CLKID_MIPI_DSI_PHY] =3D &g12a_mipi_dsi_phy.hw, + [CLKID_ASSIST_MISC] =3D &g12a_assist_misc.hw, + [CLKID_SD_EMMC_A] =3D &g12a_emmc_a.hw, + [CLKID_SD_EMMC_B] =3D &g12a_emmc_b.hw, + [CLKID_SD_EMMC_C] =3D &g12a_emmc_c.hw, + [CLKID_AUDIO_CODEC] =3D &g12a_audio_codec.hw, + [CLKID_AUDIO] =3D &g12a_audio.hw, + [CLKID_ETH] =3D &g12a_eth_core.hw, + [CLKID_DEMUX] =3D &g12a_demux.hw, + [CLKID_AUDIO_IFIFO] =3D &g12a_audio_ififo.hw, + [CLKID_ADC] =3D &g12a_adc.hw, + [CLKID_UART1] =3D &g12a_uart1.hw, + [CLKID_G2D] =3D &g12a_g2d.hw, + [CLKID_RESET] =3D &g12a_reset.hw, + [CLKID_PCIE_COMB] =3D &g12a_pcie_comb.hw, + [CLKID_PARSER] =3D &g12a_parser.hw, + [CLKID_USB] =3D &g12a_usb_general.hw, + [CLKID_PCIE_PHY] =3D &g12a_pcie_phy.hw, + [CLKID_AHB_ARB0] =3D &g12a_ahb_arb0.hw, + [CLKID_AHB_DATA_BUS] =3D &g12a_ahb_data_bus.hw, + [CLKID_AHB_CTRL_BUS] =3D &g12a_ahb_ctrl_bus.hw, + [CLKID_HTX_HDCP22] =3D &g12a_htx_hdcp22.hw, + [CLKID_HTX_PCLK] =3D &g12a_htx_pclk.hw, + [CLKID_BT656] =3D &g12a_bt656.hw, + [CLKID_USB1_DDR_BRIDGE] =3D &g12a_usb1_to_ddr.hw, + [CLKID_MMC_PCLK] =3D &g12a_mmc_pclk.hw, + [CLKID_UART2] =3D &g12a_uart2.hw, + [CLKID_VPU_INTR] =3D &g12a_vpu_intr.hw, + [CLKID_GIC] =3D &g12a_gic.hw, + [CLKID_SD_EMMC_A_CLK0_SEL] =3D &g12a_sd_emmc_a_clk0_sel.hw, + [CLKID_SD_EMMC_A_CLK0_DIV] =3D &g12a_sd_emmc_a_clk0_div.hw, + [CLKID_SD_EMMC_A_CLK0] =3D &g12a_sd_emmc_a_clk0.hw, + [CLKID_SD_EMMC_B_CLK0_SEL] =3D &g12a_sd_emmc_b_clk0_sel.hw, + [CLKID_SD_EMMC_B_CLK0_DIV] =3D &g12a_sd_emmc_b_clk0_div.hw, + [CLKID_SD_EMMC_B_CLK0] =3D &g12a_sd_emmc_b_clk0.hw, + [CLKID_SD_EMMC_C_CLK0_SEL] =3D &g12a_sd_emmc_c_clk0_sel.hw, + [CLKID_SD_EMMC_C_CLK0_DIV] =3D &g12a_sd_emmc_c_clk0_div.hw, + [CLKID_SD_EMMC_C_CLK0] =3D &g12a_sd_emmc_c_clk0.hw, + [CLKID_MPLL0_DIV] =3D &g12a_mpll0_div.hw, + [CLKID_MPLL1_DIV] =3D &g12a_mpll1_div.hw, + [CLKID_MPLL2_DIV] =3D &g12a_mpll2_div.hw, + [CLKID_MPLL3_DIV] =3D &g12a_mpll3_div.hw, + [CLKID_FCLK_DIV2_DIV] =3D &g12a_fclk_div2_div.hw, + [CLKID_FCLK_DIV3_DIV] =3D &g12a_fclk_div3_div.hw, + [CLKID_FCLK_DIV4_DIV] =3D &g12a_fclk_div4_div.hw, + [CLKID_FCLK_DIV5_DIV] =3D &g12a_fclk_div5_div.hw, + [CLKID_FCLK_DIV7_DIV] =3D &g12a_fclk_div7_div.hw, + [CLKID_FCLK_DIV2P5_DIV] =3D &g12a_fclk_div2p5_div.hw, + [CLKID_HIFI_PLL] =3D &g12a_hifi_pll.hw, + [CLKID_VCLK2_VENCI0] =3D &g12a_vclk2_venci0.hw, + [CLKID_VCLK2_VENCI1] =3D &g12a_vclk2_venci1.hw, + [CLKID_VCLK2_VENCP0] =3D &g12a_vclk2_vencp0.hw, + [CLKID_VCLK2_VENCP1] =3D &g12a_vclk2_vencp1.hw, + [CLKID_VCLK2_VENCT0] =3D &g12a_vclk2_venct0.hw, + [CLKID_VCLK2_VENCT1] =3D &g12a_vclk2_venct1.hw, + [CLKID_VCLK2_OTHER] =3D &g12a_vclk2_other.hw, + [CLKID_VCLK2_ENCI] =3D &g12a_vclk2_enci.hw, + [CLKID_VCLK2_ENCP] =3D &g12a_vclk2_encp.hw, + [CLKID_DAC_CLK] =3D &g12a_dac_clk.hw, + [CLKID_AOCLK] =3D &g12a_aoclk_gate.hw, + [CLKID_IEC958] =3D &g12a_iec958_gate.hw, + [CLKID_ENC480P] =3D &g12a_enc480p.hw, + [CLKID_RNG1] =3D &g12a_rng1.hw, + [CLKID_VCLK2_ENCT] =3D &g12a_vclk2_enct.hw, + [CLKID_VCLK2_ENCL] =3D &g12a_vclk2_encl.hw, + [CLKID_VCLK2_VENCLMMC] =3D &g12a_vclk2_venclmmc.hw, + [CLKID_VCLK2_VENCL] =3D &g12a_vclk2_vencl.hw, + [CLKID_VCLK2_OTHER1] =3D &g12a_vclk2_other1.hw, + [CLKID_FIXED_PLL_DCO] =3D &g12a_fixed_pll_dco.hw, + [CLKID_SYS_PLL_DCO] =3D &g12a_sys_pll_dco.hw, + [CLKID_GP0_PLL_DCO] =3D &g12a_gp0_pll_dco.hw, + [CLKID_HIFI_PLL_DCO] =3D &g12a_hifi_pll_dco.hw, + [CLKID_DMA] =3D &g12a_dma.hw, + [CLKID_EFUSE] =3D &g12a_efuse.hw, + [CLKID_ROM_BOOT] =3D &g12a_rom_boot.hw, + [CLKID_RESET_SEC] =3D &g12a_reset_sec.hw, + [CLKID_SEC_AHB_APB3] =3D &g12a_sec_ahb_apb3.hw, + [CLKID_MPLL_PREDIV] =3D &g12a_mpll_prediv.hw, + [CLKID_VPU_0_SEL] =3D &g12a_vpu_0_sel.hw, + [CLKID_VPU_0_DIV] =3D &g12a_vpu_0_div.hw, + [CLKID_VPU_0] =3D &g12a_vpu_0.hw, + [CLKID_VPU_1_SEL] =3D &g12a_vpu_1_sel.hw, + [CLKID_VPU_1_DIV] =3D &g12a_vpu_1_div.hw, + [CLKID_VPU_1] =3D &g12a_vpu_1.hw, + [CLKID_VPU] =3D &g12a_vpu.hw, + [CLKID_VAPB_0_SEL] =3D &g12a_vapb_0_sel.hw, + [CLKID_VAPB_0_DIV] =3D &g12a_vapb_0_div.hw, + [CLKID_VAPB_0] =3D &g12a_vapb_0.hw, + [CLKID_VAPB_1_SEL] =3D &g12a_vapb_1_sel.hw, + [CLKID_VAPB_1_DIV] =3D &g12a_vapb_1_div.hw, + [CLKID_VAPB_1] =3D &g12a_vapb_1.hw, + [CLKID_VAPB_SEL] =3D &g12a_vapb_sel.hw, + [CLKID_VAPB] =3D &g12a_vapb.hw, + [CLKID_HDMI_PLL_DCO] =3D &g12a_hdmi_pll_dco.hw, + [CLKID_HDMI_PLL_OD] =3D &g12a_hdmi_pll_od.hw, + [CLKID_HDMI_PLL_OD2] =3D &g12a_hdmi_pll_od2.hw, + [CLKID_HDMI_PLL] =3D &g12a_hdmi_pll.hw, + [CLKID_VID_PLL] =3D &g12a_vid_pll_div.hw, + [CLKID_VID_PLL_SEL] =3D &g12a_vid_pll_sel.hw, + [CLKID_VID_PLL_DIV] =3D &g12a_vid_pll.hw, + [CLKID_VCLK_SEL] =3D &g12a_vclk_sel.hw, + [CLKID_VCLK2_SEL] =3D &g12a_vclk2_sel.hw, + [CLKID_VCLK_INPUT] =3D &g12a_vclk_input.hw, + [CLKID_VCLK2_INPUT] =3D &g12a_vclk2_input.hw, + [CLKID_VCLK_DIV] =3D &g12a_vclk_div.hw, + [CLKID_VCLK2_DIV] =3D &g12a_vclk2_div.hw, + [CLKID_VCLK] =3D &g12a_vclk.hw, + [CLKID_VCLK2] =3D &g12a_vclk2.hw, + [CLKID_VCLK_DIV1] =3D &g12a_vclk_div1.hw, + [CLKID_VCLK_DIV2_EN] =3D &g12a_vclk_div2_en.hw, + [CLKID_VCLK_DIV4_EN] =3D &g12a_vclk_div4_en.hw, + [CLKID_VCLK_DIV6_EN] =3D &g12a_vclk_div6_en.hw, + [CLKID_VCLK_DIV12_EN] =3D &g12a_vclk_div12_en.hw, + [CLKID_VCLK2_DIV1] =3D &g12a_vclk2_div1.hw, + [CLKID_VCLK2_DIV2_EN] =3D &g12a_vclk2_div2_en.hw, + [CLKID_VCLK2_DIV4_EN] =3D &g12a_vclk2_div4_en.hw, + [CLKID_VCLK2_DIV6_EN] =3D &g12a_vclk2_div6_en.hw, + [CLKID_VCLK2_DIV12_EN] =3D &g12a_vclk2_div12_en.hw, + [CLKID_VCLK_DIV2] =3D &g12a_vclk_div2.hw, + [CLKID_VCLK_DIV4] =3D &g12a_vclk_div4.hw, + [CLKID_VCLK_DIV6] =3D &g12a_vclk_div6.hw, + [CLKID_VCLK_DIV12] =3D &g12a_vclk_div12.hw, + [CLKID_VCLK2_DIV2] =3D &g12a_vclk2_div2.hw, + [CLKID_VCLK2_DIV4] =3D &g12a_vclk2_div4.hw, + [CLKID_VCLK2_DIV6] =3D &g12a_vclk2_div6.hw, + [CLKID_VCLK2_DIV12] =3D &g12a_vclk2_div12.hw, + [CLKID_CTS_ENCI_SEL] =3D &g12a_cts_enci_sel.hw, + [CLKID_CTS_ENCP_SEL] =3D &g12a_cts_encp_sel.hw, + [CLKID_CTS_VDAC_SEL] =3D &g12a_cts_vdac_sel.hw, + [CLKID_HDMI_TX_SEL] =3D &g12a_hdmi_tx_sel.hw, + [CLKID_CTS_ENCI] =3D &g12a_cts_enci.hw, + [CLKID_CTS_ENCP] =3D &g12a_cts_encp.hw, + [CLKID_CTS_VDAC] =3D &g12a_cts_vdac.hw, + [CLKID_HDMI_TX] =3D &g12a_hdmi_tx.hw, + [CLKID_HDMI_SEL] =3D &g12a_hdmi_sel.hw, + [CLKID_HDMI_DIV] =3D &g12a_hdmi_div.hw, + [CLKID_HDMI] =3D &g12a_hdmi.hw, + [CLKID_MALI_0_SEL] =3D &g12a_mali_0_sel.hw, + [CLKID_MALI_0_DIV] =3D &g12a_mali_0_div.hw, + [CLKID_MALI_0] =3D &g12a_mali_0.hw, + [CLKID_MALI_1_SEL] =3D &g12a_mali_1_sel.hw, + [CLKID_MALI_1_DIV] =3D &g12a_mali_1_div.hw, + [CLKID_MALI_1] =3D &g12a_mali_1.hw, + [CLKID_MALI] =3D &g12a_mali.hw, + [CLKID_MPLL_50M_DIV] =3D &g12a_mpll_50m_div.hw, + [CLKID_MPLL_50M] =3D &g12a_mpll_50m.hw, + [CLKID_SYS_PLL_DIV16_EN] =3D &g12a_sys_pll_div16_en.hw, + [CLKID_SYS_PLL_DIV16] =3D &g12a_sys_pll_div16.hw, + [CLKID_CPU_CLK_DYN0_SEL] =3D &g12a_cpu_clk_premux0.hw, + [CLKID_CPU_CLK_DYN0_DIV] =3D &g12a_cpu_clk_mux0_div.hw, + [CLKID_CPU_CLK_DYN0] =3D &g12a_cpu_clk_postmux0.hw, + [CLKID_CPU_CLK_DYN1_SEL] =3D &g12a_cpu_clk_premux1.hw, + [CLKID_CPU_CLK_DYN1_DIV] =3D &g12a_cpu_clk_mux1_div.hw, + [CLKID_CPU_CLK_DYN1] =3D &g12a_cpu_clk_postmux1.hw, + [CLKID_CPU_CLK_DYN] =3D &g12a_cpu_clk_dyn.hw, + [CLKID_CPU_CLK] =3D &g12a_cpu_clk.hw, + [CLKID_CPU_CLK_DIV16_EN] =3D &g12a_cpu_clk_div16_en.hw, + [CLKID_CPU_CLK_DIV16] =3D &g12a_cpu_clk_div16.hw, + [CLKID_CPU_CLK_APB_DIV] =3D &g12a_cpu_clk_apb_div.hw, + [CLKID_CPU_CLK_APB] =3D &g12a_cpu_clk_apb.hw, + [CLKID_CPU_CLK_ATB_DIV] =3D &g12a_cpu_clk_atb_div.hw, + [CLKID_CPU_CLK_ATB] =3D &g12a_cpu_clk_atb.hw, + [CLKID_CPU_CLK_AXI_DIV] =3D &g12a_cpu_clk_axi_div.hw, + [CLKID_CPU_CLK_AXI] =3D &g12a_cpu_clk_axi.hw, + [CLKID_CPU_CLK_TRACE_DIV] =3D &g12a_cpu_clk_trace_div.hw, + [CLKID_CPU_CLK_TRACE] =3D &g12a_cpu_clk_trace.hw, + [CLKID_PCIE_PLL_DCO] =3D &g12a_pcie_pll_dco.hw, + [CLKID_PCIE_PLL_DCO_DIV2] =3D &g12a_pcie_pll_dco_div2.hw, + [CLKID_PCIE_PLL_OD] =3D &g12a_pcie_pll_od.hw, + [CLKID_PCIE_PLL] =3D &g12a_pcie_pll.hw, + [CLKID_VDEC_1_SEL] =3D &g12a_vdec_1_sel.hw, + [CLKID_VDEC_1_DIV] =3D &g12a_vdec_1_div.hw, + [CLKID_VDEC_1] =3D &g12a_vdec_1.hw, + [CLKID_VDEC_HEVC_SEL] =3D &g12a_vdec_hevc_sel.hw, + [CLKID_VDEC_HEVC_DIV] =3D &g12a_vdec_hevc_div.hw, + [CLKID_VDEC_HEVC] =3D &g12a_vdec_hevc.hw, + [CLKID_VDEC_HEVCF_SEL] =3D &g12a_vdec_hevcf_sel.hw, + [CLKID_VDEC_HEVCF_DIV] =3D &g12a_vdec_hevcf_div.hw, + [CLKID_VDEC_HEVCF] =3D &g12a_vdec_hevcf.hw, + [CLKID_TS_DIV] =3D &g12a_ts_div.hw, + [CLKID_TS] =3D &g12a_ts.hw, + [CLKID_SPICC0_SCLK_SEL] =3D &g12a_spicc0_sclk_sel.hw, + [CLKID_SPICC0_SCLK_DIV] =3D &g12a_spicc0_sclk_div.hw, + [CLKID_SPICC0_SCLK] =3D &g12a_spicc0_sclk.hw, + [CLKID_SPICC1_SCLK_SEL] =3D &g12a_spicc1_sclk_sel.hw, + [CLKID_SPICC1_SCLK_DIV] =3D &g12a_spicc1_sclk_div.hw, + [CLKID_SPICC1_SCLK] =3D &g12a_spicc1_sclk.hw, + [CLKID_MIPI_DSI_PXCLK_SEL] =3D &g12a_mipi_dsi_pxclk_sel.hw, + [CLKID_MIPI_DSI_PXCLK_DIV] =3D &g12a_mipi_dsi_pxclk_div.hw, + [CLKID_MIPI_DSI_PXCLK] =3D &g12a_mipi_dsi_pxclk.hw, +}; + +static struct clk_hw *g12b_hw_clks[] =3D { + [CLKID_SYS_PLL] =3D &g12a_sys_pll.hw, + [CLKID_FIXED_PLL] =3D &g12a_fixed_pll.hw, + [CLKID_FCLK_DIV2] =3D &g12a_fclk_div2.hw, + [CLKID_FCLK_DIV3] =3D &g12a_fclk_div3.hw, + [CLKID_FCLK_DIV4] =3D &g12a_fclk_div4.hw, + [CLKID_FCLK_DIV5] =3D &g12a_fclk_div5.hw, + [CLKID_FCLK_DIV7] =3D &g12a_fclk_div7.hw, + [CLKID_FCLK_DIV2P5] =3D &g12a_fclk_div2p5.hw, + [CLKID_GP0_PLL] =3D &g12a_gp0_pll.hw, + [CLKID_MPEG_SEL] =3D &g12a_mpeg_clk_sel.hw, + [CLKID_MPEG_DIV] =3D &g12a_mpeg_clk_div.hw, + [CLKID_CLK81] =3D &g12a_clk81.hw, + [CLKID_MPLL0] =3D &g12a_mpll0.hw, + [CLKID_MPLL1] =3D &g12a_mpll1.hw, + [CLKID_MPLL2] =3D &g12a_mpll2.hw, + [CLKID_MPLL3] =3D &g12a_mpll3.hw, + [CLKID_DDR] =3D &g12a_ddr.hw, + [CLKID_DOS] =3D &g12a_dos.hw, + [CLKID_AUDIO_LOCKER] =3D &g12a_audio_locker.hw, + [CLKID_MIPI_DSI_HOST] =3D &g12a_mipi_dsi_host.hw, + [CLKID_ETH_PHY] =3D &g12a_eth_phy.hw, + [CLKID_ISA] =3D &g12a_isa.hw, + [CLKID_PL301] =3D &g12a_pl301.hw, + [CLKID_PERIPHS] =3D &g12a_periphs.hw, + [CLKID_SPICC0] =3D &g12a_spicc_0.hw, + [CLKID_I2C] =3D &g12a_i2c.hw, + [CLKID_SANA] =3D &g12a_sana.hw, + [CLKID_SD] =3D &g12a_sd.hw, + [CLKID_RNG0] =3D &g12a_rng0.hw, + [CLKID_UART0] =3D &g12a_uart0.hw, + [CLKID_SPICC1] =3D &g12a_spicc_1.hw, + [CLKID_HIU_IFACE] =3D &g12a_hiu_reg.hw, + [CLKID_MIPI_DSI_PHY] =3D &g12a_mipi_dsi_phy.hw, + [CLKID_ASSIST_MISC] =3D &g12a_assist_misc.hw, + [CLKID_SD_EMMC_A] =3D &g12a_emmc_a.hw, + [CLKID_SD_EMMC_B] =3D &g12a_emmc_b.hw, + [CLKID_SD_EMMC_C] =3D &g12a_emmc_c.hw, + [CLKID_AUDIO_CODEC] =3D &g12a_audio_codec.hw, + [CLKID_AUDIO] =3D &g12a_audio.hw, + [CLKID_ETH] =3D &g12a_eth_core.hw, + [CLKID_DEMUX] =3D &g12a_demux.hw, + [CLKID_AUDIO_IFIFO] =3D &g12a_audio_ififo.hw, + [CLKID_ADC] =3D &g12a_adc.hw, + [CLKID_UART1] =3D &g12a_uart1.hw, + [CLKID_G2D] =3D &g12a_g2d.hw, + [CLKID_RESET] =3D &g12a_reset.hw, + [CLKID_PCIE_COMB] =3D &g12a_pcie_comb.hw, + [CLKID_PARSER] =3D &g12a_parser.hw, + [CLKID_USB] =3D &g12a_usb_general.hw, + [CLKID_PCIE_PHY] =3D &g12a_pcie_phy.hw, + [CLKID_AHB_ARB0] =3D &g12a_ahb_arb0.hw, + [CLKID_AHB_DATA_BUS] =3D &g12a_ahb_data_bus.hw, + [CLKID_AHB_CTRL_BUS] =3D &g12a_ahb_ctrl_bus.hw, + [CLKID_HTX_HDCP22] =3D &g12a_htx_hdcp22.hw, + [CLKID_HTX_PCLK] =3D &g12a_htx_pclk.hw, + [CLKID_BT656] =3D &g12a_bt656.hw, + [CLKID_USB1_DDR_BRIDGE] =3D &g12a_usb1_to_ddr.hw, + [CLKID_MMC_PCLK] =3D &g12a_mmc_pclk.hw, + [CLKID_UART2] =3D &g12a_uart2.hw, + [CLKID_VPU_INTR] =3D &g12a_vpu_intr.hw, + [CLKID_GIC] =3D &g12a_gic.hw, + [CLKID_SD_EMMC_A_CLK0_SEL] =3D &g12a_sd_emmc_a_clk0_sel.hw, + [CLKID_SD_EMMC_A_CLK0_DIV] =3D &g12a_sd_emmc_a_clk0_div.hw, + [CLKID_SD_EMMC_A_CLK0] =3D &g12a_sd_emmc_a_clk0.hw, + [CLKID_SD_EMMC_B_CLK0_SEL] =3D &g12a_sd_emmc_b_clk0_sel.hw, + [CLKID_SD_EMMC_B_CLK0_DIV] =3D &g12a_sd_emmc_b_clk0_div.hw, + [CLKID_SD_EMMC_B_CLK0] =3D &g12a_sd_emmc_b_clk0.hw, + [CLKID_SD_EMMC_C_CLK0_SEL] =3D &g12a_sd_emmc_c_clk0_sel.hw, + [CLKID_SD_EMMC_C_CLK0_DIV] =3D &g12a_sd_emmc_c_clk0_div.hw, + [CLKID_SD_EMMC_C_CLK0] =3D &g12a_sd_emmc_c_clk0.hw, + [CLKID_MPLL0_DIV] =3D &g12a_mpll0_div.hw, + [CLKID_MPLL1_DIV] =3D &g12a_mpll1_div.hw, + [CLKID_MPLL2_DIV] =3D &g12a_mpll2_div.hw, + [CLKID_MPLL3_DIV] =3D &g12a_mpll3_div.hw, + [CLKID_FCLK_DIV2_DIV] =3D &g12a_fclk_div2_div.hw, + [CLKID_FCLK_DIV3_DIV] =3D &g12a_fclk_div3_div.hw, + [CLKID_FCLK_DIV4_DIV] =3D &g12a_fclk_div4_div.hw, + [CLKID_FCLK_DIV5_DIV] =3D &g12a_fclk_div5_div.hw, + [CLKID_FCLK_DIV7_DIV] =3D &g12a_fclk_div7_div.hw, + [CLKID_FCLK_DIV2P5_DIV] =3D &g12a_fclk_div2p5_div.hw, + [CLKID_HIFI_PLL] =3D &g12a_hifi_pll.hw, + [CLKID_VCLK2_VENCI0] =3D &g12a_vclk2_venci0.hw, + [CLKID_VCLK2_VENCI1] =3D &g12a_vclk2_venci1.hw, + [CLKID_VCLK2_VENCP0] =3D &g12a_vclk2_vencp0.hw, + [CLKID_VCLK2_VENCP1] =3D &g12a_vclk2_vencp1.hw, + [CLKID_VCLK2_VENCT0] =3D &g12a_vclk2_venct0.hw, + [CLKID_VCLK2_VENCT1] =3D &g12a_vclk2_venct1.hw, + [CLKID_VCLK2_OTHER] =3D &g12a_vclk2_other.hw, + [CLKID_VCLK2_ENCI] =3D &g12a_vclk2_enci.hw, + [CLKID_VCLK2_ENCP] =3D &g12a_vclk2_encp.hw, + [CLKID_DAC_CLK] =3D &g12a_dac_clk.hw, + [CLKID_AOCLK] =3D &g12a_aoclk_gate.hw, + [CLKID_IEC958] =3D &g12a_iec958_gate.hw, + [CLKID_ENC480P] =3D &g12a_enc480p.hw, + [CLKID_RNG1] =3D &g12a_rng1.hw, + [CLKID_VCLK2_ENCT] =3D &g12a_vclk2_enct.hw, + [CLKID_VCLK2_ENCL] =3D &g12a_vclk2_encl.hw, + [CLKID_VCLK2_VENCLMMC] =3D &g12a_vclk2_venclmmc.hw, + [CLKID_VCLK2_VENCL] =3D &g12a_vclk2_vencl.hw, + [CLKID_VCLK2_OTHER1] =3D &g12a_vclk2_other1.hw, + [CLKID_FIXED_PLL_DCO] =3D &g12a_fixed_pll_dco.hw, + [CLKID_SYS_PLL_DCO] =3D &g12a_sys_pll_dco.hw, + [CLKID_GP0_PLL_DCO] =3D &g12a_gp0_pll_dco.hw, + [CLKID_HIFI_PLL_DCO] =3D &g12a_hifi_pll_dco.hw, + [CLKID_DMA] =3D &g12a_dma.hw, + [CLKID_EFUSE] =3D &g12a_efuse.hw, + [CLKID_ROM_BOOT] =3D &g12a_rom_boot.hw, + [CLKID_RESET_SEC] =3D &g12a_reset_sec.hw, + [CLKID_SEC_AHB_APB3] =3D &g12a_sec_ahb_apb3.hw, + [CLKID_MPLL_PREDIV] =3D &g12a_mpll_prediv.hw, + [CLKID_VPU_0_SEL] =3D &g12a_vpu_0_sel.hw, + [CLKID_VPU_0_DIV] =3D &g12a_vpu_0_div.hw, + [CLKID_VPU_0] =3D &g12a_vpu_0.hw, + [CLKID_VPU_1_SEL] =3D &g12a_vpu_1_sel.hw, + [CLKID_VPU_1_DIV] =3D &g12a_vpu_1_div.hw, + [CLKID_VPU_1] =3D &g12a_vpu_1.hw, + [CLKID_VPU] =3D &g12a_vpu.hw, + [CLKID_VAPB_0_SEL] =3D &g12a_vapb_0_sel.hw, + [CLKID_VAPB_0_DIV] =3D &g12a_vapb_0_div.hw, + [CLKID_VAPB_0] =3D &g12a_vapb_0.hw, + [CLKID_VAPB_1_SEL] =3D &g12a_vapb_1_sel.hw, + [CLKID_VAPB_1_DIV] =3D &g12a_vapb_1_div.hw, + [CLKID_VAPB_1] =3D &g12a_vapb_1.hw, + [CLKID_VAPB_SEL] =3D &g12a_vapb_sel.hw, + [CLKID_VAPB] =3D &g12a_vapb.hw, + [CLKID_HDMI_PLL_DCO] =3D &g12a_hdmi_pll_dco.hw, + [CLKID_HDMI_PLL_OD] =3D &g12a_hdmi_pll_od.hw, + [CLKID_HDMI_PLL_OD2] =3D &g12a_hdmi_pll_od2.hw, + [CLKID_HDMI_PLL] =3D &g12a_hdmi_pll.hw, + [CLKID_VID_PLL] =3D &g12a_vid_pll_div.hw, + [CLKID_VID_PLL_SEL] =3D &g12a_vid_pll_sel.hw, + [CLKID_VID_PLL_DIV] =3D &g12a_vid_pll.hw, + [CLKID_VCLK_SEL] =3D &g12a_vclk_sel.hw, + [CLKID_VCLK2_SEL] =3D &g12a_vclk2_sel.hw, + [CLKID_VCLK_INPUT] =3D &g12a_vclk_input.hw, + [CLKID_VCLK2_INPUT] =3D &g12a_vclk2_input.hw, + [CLKID_VCLK_DIV] =3D &g12a_vclk_div.hw, + [CLKID_VCLK2_DIV] =3D &g12a_vclk2_div.hw, + [CLKID_VCLK] =3D &g12a_vclk.hw, + [CLKID_VCLK2] =3D &g12a_vclk2.hw, + [CLKID_VCLK_DIV1] =3D &g12a_vclk_div1.hw, + [CLKID_VCLK_DIV2_EN] =3D &g12a_vclk_div2_en.hw, + [CLKID_VCLK_DIV4_EN] =3D &g12a_vclk_div4_en.hw, + [CLKID_VCLK_DIV6_EN] =3D &g12a_vclk_div6_en.hw, + [CLKID_VCLK_DIV12_EN] =3D &g12a_vclk_div12_en.hw, + [CLKID_VCLK2_DIV1] =3D &g12a_vclk2_div1.hw, + [CLKID_VCLK2_DIV2_EN] =3D &g12a_vclk2_div2_en.hw, + [CLKID_VCLK2_DIV4_EN] =3D &g12a_vclk2_div4_en.hw, + [CLKID_VCLK2_DIV6_EN] =3D &g12a_vclk2_div6_en.hw, + [CLKID_VCLK2_DIV12_EN] =3D &g12a_vclk2_div12_en.hw, + [CLKID_VCLK_DIV2] =3D &g12a_vclk_div2.hw, + [CLKID_VCLK_DIV4] =3D &g12a_vclk_div4.hw, + [CLKID_VCLK_DIV6] =3D &g12a_vclk_div6.hw, + [CLKID_VCLK_DIV12] =3D &g12a_vclk_div12.hw, + [CLKID_VCLK2_DIV2] =3D &g12a_vclk2_div2.hw, + [CLKID_VCLK2_DIV4] =3D &g12a_vclk2_div4.hw, + [CLKID_VCLK2_DIV6] =3D &g12a_vclk2_div6.hw, + [CLKID_VCLK2_DIV12] =3D &g12a_vclk2_div12.hw, + [CLKID_CTS_ENCI_SEL] =3D &g12a_cts_enci_sel.hw, + [CLKID_CTS_ENCP_SEL] =3D &g12a_cts_encp_sel.hw, + [CLKID_CTS_VDAC_SEL] =3D &g12a_cts_vdac_sel.hw, + [CLKID_HDMI_TX_SEL] =3D &g12a_hdmi_tx_sel.hw, + [CLKID_CTS_ENCI] =3D &g12a_cts_enci.hw, + [CLKID_CTS_ENCP] =3D &g12a_cts_encp.hw, + [CLKID_CTS_VDAC] =3D &g12a_cts_vdac.hw, + [CLKID_HDMI_TX] =3D &g12a_hdmi_tx.hw, + [CLKID_HDMI_SEL] =3D &g12a_hdmi_sel.hw, + [CLKID_HDMI_DIV] =3D &g12a_hdmi_div.hw, + [CLKID_HDMI] =3D &g12a_hdmi.hw, + [CLKID_MALI_0_SEL] =3D &g12a_mali_0_sel.hw, + [CLKID_MALI_0_DIV] =3D &g12a_mali_0_div.hw, + [CLKID_MALI_0] =3D &g12a_mali_0.hw, + [CLKID_MALI_1_SEL] =3D &g12a_mali_1_sel.hw, + [CLKID_MALI_1_DIV] =3D &g12a_mali_1_div.hw, + [CLKID_MALI_1] =3D &g12a_mali_1.hw, + [CLKID_MALI] =3D &g12a_mali.hw, + [CLKID_MPLL_50M_DIV] =3D &g12a_mpll_50m_div.hw, + [CLKID_MPLL_50M] =3D &g12a_mpll_50m.hw, + [CLKID_SYS_PLL_DIV16_EN] =3D &g12a_sys_pll_div16_en.hw, + [CLKID_SYS_PLL_DIV16] =3D &g12a_sys_pll_div16.hw, + [CLKID_CPU_CLK_DYN0_SEL] =3D &g12a_cpu_clk_premux0.hw, + [CLKID_CPU_CLK_DYN0_DIV] =3D &g12a_cpu_clk_mux0_div.hw, + [CLKID_CPU_CLK_DYN0] =3D &g12a_cpu_clk_postmux0.hw, + [CLKID_CPU_CLK_DYN1_SEL] =3D &g12a_cpu_clk_premux1.hw, + [CLKID_CPU_CLK_DYN1_DIV] =3D &g12a_cpu_clk_mux1_div.hw, + [CLKID_CPU_CLK_DYN1] =3D &g12a_cpu_clk_postmux1.hw, + [CLKID_CPU_CLK_DYN] =3D &g12a_cpu_clk_dyn.hw, + [CLKID_CPU_CLK] =3D &g12b_cpu_clk.hw, + [CLKID_CPU_CLK_DIV16_EN] =3D &g12a_cpu_clk_div16_en.hw, + [CLKID_CPU_CLK_DIV16] =3D &g12a_cpu_clk_div16.hw, + [CLKID_CPU_CLK_APB_DIV] =3D &g12a_cpu_clk_apb_div.hw, + [CLKID_CPU_CLK_APB] =3D &g12a_cpu_clk_apb.hw, + [CLKID_CPU_CLK_ATB_DIV] =3D &g12a_cpu_clk_atb_div.hw, + [CLKID_CPU_CLK_ATB] =3D &g12a_cpu_clk_atb.hw, + [CLKID_CPU_CLK_AXI_DIV] =3D &g12a_cpu_clk_axi_div.hw, + [CLKID_CPU_CLK_AXI] =3D &g12a_cpu_clk_axi.hw, + [CLKID_CPU_CLK_TRACE_DIV] =3D &g12a_cpu_clk_trace_div.hw, + [CLKID_CPU_CLK_TRACE] =3D &g12a_cpu_clk_trace.hw, + [CLKID_PCIE_PLL_DCO] =3D &g12a_pcie_pll_dco.hw, + [CLKID_PCIE_PLL_DCO_DIV2] =3D &g12a_pcie_pll_dco_div2.hw, + [CLKID_PCIE_PLL_OD] =3D &g12a_pcie_pll_od.hw, + [CLKID_PCIE_PLL] =3D &g12a_pcie_pll.hw, + [CLKID_VDEC_1_SEL] =3D &g12a_vdec_1_sel.hw, + [CLKID_VDEC_1_DIV] =3D &g12a_vdec_1_div.hw, + [CLKID_VDEC_1] =3D &g12a_vdec_1.hw, + [CLKID_VDEC_HEVC_SEL] =3D &g12a_vdec_hevc_sel.hw, + [CLKID_VDEC_HEVC_DIV] =3D &g12a_vdec_hevc_div.hw, + [CLKID_VDEC_HEVC] =3D &g12a_vdec_hevc.hw, + [CLKID_VDEC_HEVCF_SEL] =3D &g12a_vdec_hevcf_sel.hw, + [CLKID_VDEC_HEVCF_DIV] =3D &g12a_vdec_hevcf_div.hw, + [CLKID_VDEC_HEVCF] =3D &g12a_vdec_hevcf.hw, + [CLKID_TS_DIV] =3D &g12a_ts_div.hw, + [CLKID_TS] =3D &g12a_ts.hw, + [CLKID_SYS1_PLL_DCO] =3D &g12b_sys1_pll_dco.hw, + [CLKID_SYS1_PLL] =3D &g12b_sys1_pll.hw, + [CLKID_SYS1_PLL_DIV16_EN] =3D &g12b_sys1_pll_div16_en.hw, + [CLKID_SYS1_PLL_DIV16] =3D &g12b_sys1_pll_div16.hw, + [CLKID_CPUB_CLK_DYN0_SEL] =3D &g12b_cpub_clk_premux0.hw, + [CLKID_CPUB_CLK_DYN0_DIV] =3D &g12b_cpub_clk_mux0_div.hw, + [CLKID_CPUB_CLK_DYN0] =3D &g12b_cpub_clk_postmux0.hw, + [CLKID_CPUB_CLK_DYN1_SEL] =3D &g12b_cpub_clk_premux1.hw, + [CLKID_CPUB_CLK_DYN1_DIV] =3D &g12b_cpub_clk_mux1_div.hw, + [CLKID_CPUB_CLK_DYN1] =3D &g12b_cpub_clk_postmux1.hw, + [CLKID_CPUB_CLK_DYN] =3D &g12b_cpub_clk_dyn.hw, + [CLKID_CPUB_CLK] =3D &g12b_cpub_clk.hw, + [CLKID_CPUB_CLK_DIV16_EN] =3D &g12b_cpub_clk_div16_en.hw, + [CLKID_CPUB_CLK_DIV16] =3D &g12b_cpub_clk_div16.hw, + [CLKID_CPUB_CLK_DIV2] =3D &g12b_cpub_clk_div2.hw, + [CLKID_CPUB_CLK_DIV3] =3D &g12b_cpub_clk_div3.hw, + [CLKID_CPUB_CLK_DIV4] =3D &g12b_cpub_clk_div4.hw, + [CLKID_CPUB_CLK_DIV5] =3D &g12b_cpub_clk_div5.hw, + [CLKID_CPUB_CLK_DIV6] =3D &g12b_cpub_clk_div6.hw, + [CLKID_CPUB_CLK_DIV7] =3D &g12b_cpub_clk_div7.hw, + [CLKID_CPUB_CLK_DIV8] =3D &g12b_cpub_clk_div8.hw, + [CLKID_CPUB_CLK_APB_SEL] =3D &g12b_cpub_clk_apb_sel.hw, + [CLKID_CPUB_CLK_APB] =3D &g12b_cpub_clk_apb.hw, + [CLKID_CPUB_CLK_ATB_SEL] =3D &g12b_cpub_clk_atb_sel.hw, + [CLKID_CPUB_CLK_ATB] =3D &g12b_cpub_clk_atb.hw, + [CLKID_CPUB_CLK_AXI_SEL] =3D &g12b_cpub_clk_axi_sel.hw, + [CLKID_CPUB_CLK_AXI] =3D &g12b_cpub_clk_axi.hw, + [CLKID_CPUB_CLK_TRACE_SEL] =3D &g12b_cpub_clk_trace_sel.hw, + [CLKID_CPUB_CLK_TRACE] =3D &g12b_cpub_clk_trace.hw, + [CLKID_SPICC0_SCLK_SEL] =3D &g12a_spicc0_sclk_sel.hw, + [CLKID_SPICC0_SCLK_DIV] =3D &g12a_spicc0_sclk_div.hw, + [CLKID_SPICC0_SCLK] =3D &g12a_spicc0_sclk.hw, + [CLKID_SPICC1_SCLK_SEL] =3D &g12a_spicc1_sclk_sel.hw, + [CLKID_SPICC1_SCLK_DIV] =3D &g12a_spicc1_sclk_div.hw, + [CLKID_SPICC1_SCLK] =3D &g12a_spicc1_sclk.hw, + [CLKID_NNA_AXI_CLK_SEL] =3D &sm1_nna_axi_clk_sel.hw, + [CLKID_NNA_AXI_CLK_DIV] =3D &sm1_nna_axi_clk_div.hw, + [CLKID_NNA_AXI_CLK] =3D &sm1_nna_axi_clk.hw, + [CLKID_NNA_CORE_CLK_SEL] =3D &sm1_nna_core_clk_sel.hw, + [CLKID_NNA_CORE_CLK_DIV] =3D &sm1_nna_core_clk_div.hw, + [CLKID_NNA_CORE_CLK] =3D &sm1_nna_core_clk.hw, + [CLKID_MIPI_DSI_PXCLK_SEL] =3D &g12a_mipi_dsi_pxclk_sel.hw, + [CLKID_MIPI_DSI_PXCLK_DIV] =3D &g12a_mipi_dsi_pxclk_div.hw, + [CLKID_MIPI_DSI_PXCLK] =3D &g12a_mipi_dsi_pxclk.hw, +}; + +static struct clk_hw *sm1_hw_clks[] =3D { + [CLKID_SYS_PLL] =3D &g12a_sys_pll.hw, + [CLKID_FIXED_PLL] =3D &g12a_fixed_pll.hw, + [CLKID_FCLK_DIV2] =3D &g12a_fclk_div2.hw, + [CLKID_FCLK_DIV3] =3D &g12a_fclk_div3.hw, + [CLKID_FCLK_DIV4] =3D &g12a_fclk_div4.hw, + [CLKID_FCLK_DIV5] =3D &g12a_fclk_div5.hw, + [CLKID_FCLK_DIV7] =3D &g12a_fclk_div7.hw, + [CLKID_FCLK_DIV2P5] =3D &g12a_fclk_div2p5.hw, + [CLKID_GP0_PLL] =3D &g12a_gp0_pll.hw, + [CLKID_MPEG_SEL] =3D &g12a_mpeg_clk_sel.hw, + [CLKID_MPEG_DIV] =3D &g12a_mpeg_clk_div.hw, + [CLKID_CLK81] =3D &g12a_clk81.hw, + [CLKID_MPLL0] =3D &g12a_mpll0.hw, + [CLKID_MPLL1] =3D &g12a_mpll1.hw, + [CLKID_MPLL2] =3D &g12a_mpll2.hw, + [CLKID_MPLL3] =3D &g12a_mpll3.hw, + [CLKID_DDR] =3D &g12a_ddr.hw, + [CLKID_DOS] =3D &g12a_dos.hw, + [CLKID_AUDIO_LOCKER] =3D &g12a_audio_locker.hw, + [CLKID_MIPI_DSI_HOST] =3D &g12a_mipi_dsi_host.hw, + [CLKID_ETH_PHY] =3D &g12a_eth_phy.hw, + [CLKID_ISA] =3D &g12a_isa.hw, + [CLKID_PL301] =3D &g12a_pl301.hw, + [CLKID_PERIPHS] =3D &g12a_periphs.hw, + [CLKID_SPICC0] =3D &g12a_spicc_0.hw, + [CLKID_I2C] =3D &g12a_i2c.hw, + [CLKID_SANA] =3D &g12a_sana.hw, + [CLKID_SD] =3D &g12a_sd.hw, + [CLKID_RNG0] =3D &g12a_rng0.hw, + [CLKID_UART0] =3D &g12a_uart0.hw, + [CLKID_SPICC1] =3D &g12a_spicc_1.hw, + [CLKID_HIU_IFACE] =3D &g12a_hiu_reg.hw, + [CLKID_MIPI_DSI_PHY] =3D &g12a_mipi_dsi_phy.hw, + [CLKID_ASSIST_MISC] =3D &g12a_assist_misc.hw, + [CLKID_SD_EMMC_A] =3D &g12a_emmc_a.hw, + [CLKID_SD_EMMC_B] =3D &g12a_emmc_b.hw, + [CLKID_SD_EMMC_C] =3D &g12a_emmc_c.hw, + [CLKID_AUDIO_CODEC] =3D &g12a_audio_codec.hw, + [CLKID_AUDIO] =3D &g12a_audio.hw, + [CLKID_ETH] =3D &g12a_eth_core.hw, + [CLKID_DEMUX] =3D &g12a_demux.hw, + [CLKID_AUDIO_IFIFO] =3D &g12a_audio_ififo.hw, + [CLKID_ADC] =3D &g12a_adc.hw, + [CLKID_UART1] =3D &g12a_uart1.hw, + [CLKID_G2D] =3D &g12a_g2d.hw, + [CLKID_RESET] =3D &g12a_reset.hw, + [CLKID_PCIE_COMB] =3D &g12a_pcie_comb.hw, + [CLKID_PARSER] =3D &g12a_parser.hw, + [CLKID_USB] =3D &g12a_usb_general.hw, + [CLKID_PCIE_PHY] =3D &g12a_pcie_phy.hw, + [CLKID_AHB_ARB0] =3D &g12a_ahb_arb0.hw, + [CLKID_AHB_DATA_BUS] =3D &g12a_ahb_data_bus.hw, + [CLKID_AHB_CTRL_BUS] =3D &g12a_ahb_ctrl_bus.hw, + [CLKID_HTX_HDCP22] =3D &g12a_htx_hdcp22.hw, + [CLKID_HTX_PCLK] =3D &g12a_htx_pclk.hw, + [CLKID_BT656] =3D &g12a_bt656.hw, + [CLKID_USB1_DDR_BRIDGE] =3D &g12a_usb1_to_ddr.hw, + [CLKID_MMC_PCLK] =3D &g12a_mmc_pclk.hw, + [CLKID_UART2] =3D &g12a_uart2.hw, + [CLKID_VPU_INTR] =3D &g12a_vpu_intr.hw, + [CLKID_GIC] =3D &g12a_gic.hw, + [CLKID_SD_EMMC_A_CLK0_SEL] =3D &g12a_sd_emmc_a_clk0_sel.hw, + [CLKID_SD_EMMC_A_CLK0_DIV] =3D &g12a_sd_emmc_a_clk0_div.hw, + [CLKID_SD_EMMC_A_CLK0] =3D &g12a_sd_emmc_a_clk0.hw, + [CLKID_SD_EMMC_B_CLK0_SEL] =3D &g12a_sd_emmc_b_clk0_sel.hw, + [CLKID_SD_EMMC_B_CLK0_DIV] =3D &g12a_sd_emmc_b_clk0_div.hw, + [CLKID_SD_EMMC_B_CLK0] =3D &g12a_sd_emmc_b_clk0.hw, + [CLKID_SD_EMMC_C_CLK0_SEL] =3D &g12a_sd_emmc_c_clk0_sel.hw, + [CLKID_SD_EMMC_C_CLK0_DIV] =3D &g12a_sd_emmc_c_clk0_div.hw, + [CLKID_SD_EMMC_C_CLK0] =3D &g12a_sd_emmc_c_clk0.hw, + [CLKID_MPLL0_DIV] =3D &g12a_mpll0_div.hw, + [CLKID_MPLL1_DIV] =3D &g12a_mpll1_div.hw, + [CLKID_MPLL2_DIV] =3D &g12a_mpll2_div.hw, + [CLKID_MPLL3_DIV] =3D &g12a_mpll3_div.hw, + [CLKID_FCLK_DIV2_DIV] =3D &g12a_fclk_div2_div.hw, + [CLKID_FCLK_DIV3_DIV] =3D &g12a_fclk_div3_div.hw, + [CLKID_FCLK_DIV4_DIV] =3D &g12a_fclk_div4_div.hw, + [CLKID_FCLK_DIV5_DIV] =3D &g12a_fclk_div5_div.hw, + [CLKID_FCLK_DIV7_DIV] =3D &g12a_fclk_div7_div.hw, + [CLKID_FCLK_DIV2P5_DIV] =3D &g12a_fclk_div2p5_div.hw, + [CLKID_HIFI_PLL] =3D &g12a_hifi_pll.hw, + [CLKID_VCLK2_VENCI0] =3D &g12a_vclk2_venci0.hw, + [CLKID_VCLK2_VENCI1] =3D &g12a_vclk2_venci1.hw, + [CLKID_VCLK2_VENCP0] =3D &g12a_vclk2_vencp0.hw, + [CLKID_VCLK2_VENCP1] =3D &g12a_vclk2_vencp1.hw, + [CLKID_VCLK2_VENCT0] =3D &g12a_vclk2_venct0.hw, + [CLKID_VCLK2_VENCT1] =3D &g12a_vclk2_venct1.hw, + [CLKID_VCLK2_OTHER] =3D &g12a_vclk2_other.hw, + [CLKID_VCLK2_ENCI] =3D &g12a_vclk2_enci.hw, + [CLKID_VCLK2_ENCP] =3D &g12a_vclk2_encp.hw, + [CLKID_DAC_CLK] =3D &g12a_dac_clk.hw, + [CLKID_AOCLK] =3D &g12a_aoclk_gate.hw, + [CLKID_IEC958] =3D &g12a_iec958_gate.hw, + [CLKID_ENC480P] =3D &g12a_enc480p.hw, + [CLKID_RNG1] =3D &g12a_rng1.hw, + [CLKID_VCLK2_ENCT] =3D &g12a_vclk2_enct.hw, + [CLKID_VCLK2_ENCL] =3D &g12a_vclk2_encl.hw, + [CLKID_VCLK2_VENCLMMC] =3D &g12a_vclk2_venclmmc.hw, + [CLKID_VCLK2_VENCL] =3D &g12a_vclk2_vencl.hw, + [CLKID_VCLK2_OTHER1] =3D &g12a_vclk2_other1.hw, + [CLKID_FIXED_PLL_DCO] =3D &g12a_fixed_pll_dco.hw, + [CLKID_SYS_PLL_DCO] =3D &g12a_sys_pll_dco.hw, + [CLKID_GP0_PLL_DCO] =3D &g12a_gp0_pll_dco.hw, + [CLKID_HIFI_PLL_DCO] =3D &g12a_hifi_pll_dco.hw, + [CLKID_DMA] =3D &g12a_dma.hw, + [CLKID_EFUSE] =3D &g12a_efuse.hw, + [CLKID_ROM_BOOT] =3D &g12a_rom_boot.hw, + [CLKID_RESET_SEC] =3D &g12a_reset_sec.hw, + [CLKID_SEC_AHB_APB3] =3D &g12a_sec_ahb_apb3.hw, + [CLKID_MPLL_PREDIV] =3D &g12a_mpll_prediv.hw, + [CLKID_VPU_0_SEL] =3D &g12a_vpu_0_sel.hw, + [CLKID_VPU_0_DIV] =3D &g12a_vpu_0_div.hw, + [CLKID_VPU_0] =3D &g12a_vpu_0.hw, + [CLKID_VPU_1_SEL] =3D &g12a_vpu_1_sel.hw, + [CLKID_VPU_1_DIV] =3D &g12a_vpu_1_div.hw, + [CLKID_VPU_1] =3D &g12a_vpu_1.hw, + [CLKID_VPU] =3D &g12a_vpu.hw, + [CLKID_VAPB_0_SEL] =3D &g12a_vapb_0_sel.hw, + [CLKID_VAPB_0_DIV] =3D &g12a_vapb_0_div.hw, + [CLKID_VAPB_0] =3D &g12a_vapb_0.hw, + [CLKID_VAPB_1_SEL] =3D &g12a_vapb_1_sel.hw, + [CLKID_VAPB_1_DIV] =3D &g12a_vapb_1_div.hw, + [CLKID_VAPB_1] =3D &g12a_vapb_1.hw, + [CLKID_VAPB_SEL] =3D &g12a_vapb_sel.hw, + [CLKID_VAPB] =3D &g12a_vapb.hw, + [CLKID_HDMI_PLL_DCO] =3D &g12a_hdmi_pll_dco.hw, + [CLKID_HDMI_PLL_OD] =3D &g12a_hdmi_pll_od.hw, + [CLKID_HDMI_PLL_OD2] =3D &g12a_hdmi_pll_od2.hw, + [CLKID_HDMI_PLL] =3D &g12a_hdmi_pll.hw, + [CLKID_VID_PLL] =3D &g12a_vid_pll_div.hw, + [CLKID_VID_PLL_SEL] =3D &g12a_vid_pll_sel.hw, + [CLKID_VID_PLL_DIV] =3D &g12a_vid_pll.hw, + [CLKID_VCLK_SEL] =3D &g12a_vclk_sel.hw, + [CLKID_VCLK2_SEL] =3D &g12a_vclk2_sel.hw, + [CLKID_VCLK_INPUT] =3D &g12a_vclk_input.hw, + [CLKID_VCLK2_INPUT] =3D &g12a_vclk2_input.hw, + [CLKID_VCLK_DIV] =3D &g12a_vclk_div.hw, + [CLKID_VCLK2_DIV] =3D &g12a_vclk2_div.hw, + [CLKID_VCLK] =3D &g12a_vclk.hw, + [CLKID_VCLK2] =3D &g12a_vclk2.hw, + [CLKID_VCLK_DIV1] =3D &g12a_vclk_div1.hw, + [CLKID_VCLK_DIV2_EN] =3D &g12a_vclk_div2_en.hw, + [CLKID_VCLK_DIV4_EN] =3D &g12a_vclk_div4_en.hw, + [CLKID_VCLK_DIV6_EN] =3D &g12a_vclk_div6_en.hw, + [CLKID_VCLK_DIV12_EN] =3D &g12a_vclk_div12_en.hw, + [CLKID_VCLK2_DIV1] =3D &g12a_vclk2_div1.hw, + [CLKID_VCLK2_DIV2_EN] =3D &g12a_vclk2_div2_en.hw, + [CLKID_VCLK2_DIV4_EN] =3D &g12a_vclk2_div4_en.hw, + [CLKID_VCLK2_DIV6_EN] =3D &g12a_vclk2_div6_en.hw, + [CLKID_VCLK2_DIV12_EN] =3D &g12a_vclk2_div12_en.hw, + [CLKID_VCLK_DIV2] =3D &g12a_vclk_div2.hw, + [CLKID_VCLK_DIV4] =3D &g12a_vclk_div4.hw, + [CLKID_VCLK_DIV6] =3D &g12a_vclk_div6.hw, + [CLKID_VCLK_DIV12] =3D &g12a_vclk_div12.hw, + [CLKID_VCLK2_DIV2] =3D &g12a_vclk2_div2.hw, + [CLKID_VCLK2_DIV4] =3D &g12a_vclk2_div4.hw, + [CLKID_VCLK2_DIV6] =3D &g12a_vclk2_div6.hw, + [CLKID_VCLK2_DIV12] =3D &g12a_vclk2_div12.hw, + [CLKID_CTS_ENCI_SEL] =3D &g12a_cts_enci_sel.hw, + [CLKID_CTS_ENCP_SEL] =3D &g12a_cts_encp_sel.hw, + [CLKID_CTS_VDAC_SEL] =3D &g12a_cts_vdac_sel.hw, + [CLKID_HDMI_TX_SEL] =3D &g12a_hdmi_tx_sel.hw, + [CLKID_CTS_ENCI] =3D &g12a_cts_enci.hw, + [CLKID_CTS_ENCP] =3D &g12a_cts_encp.hw, + [CLKID_CTS_VDAC] =3D &g12a_cts_vdac.hw, + [CLKID_HDMI_TX] =3D &g12a_hdmi_tx.hw, + [CLKID_HDMI_SEL] =3D &g12a_hdmi_sel.hw, + [CLKID_HDMI_DIV] =3D &g12a_hdmi_div.hw, + [CLKID_HDMI] =3D &g12a_hdmi.hw, + [CLKID_MALI_0_SEL] =3D &g12a_mali_0_sel.hw, + [CLKID_MALI_0_DIV] =3D &g12a_mali_0_div.hw, + [CLKID_MALI_0] =3D &g12a_mali_0.hw, + [CLKID_MALI_1_SEL] =3D &g12a_mali_1_sel.hw, + [CLKID_MALI_1_DIV] =3D &g12a_mali_1_div.hw, + [CLKID_MALI_1] =3D &g12a_mali_1.hw, + [CLKID_MALI] =3D &g12a_mali.hw, + [CLKID_MPLL_50M_DIV] =3D &g12a_mpll_50m_div.hw, + [CLKID_MPLL_50M] =3D &g12a_mpll_50m.hw, + [CLKID_SYS_PLL_DIV16_EN] =3D &g12a_sys_pll_div16_en.hw, + [CLKID_SYS_PLL_DIV16] =3D &g12a_sys_pll_div16.hw, + [CLKID_CPU_CLK_DYN0_SEL] =3D &g12a_cpu_clk_premux0.hw, + [CLKID_CPU_CLK_DYN0_DIV] =3D &g12a_cpu_clk_mux0_div.hw, + [CLKID_CPU_CLK_DYN0] =3D &g12a_cpu_clk_postmux0.hw, + [CLKID_CPU_CLK_DYN1_SEL] =3D &g12a_cpu_clk_premux1.hw, + [CLKID_CPU_CLK_DYN1_DIV] =3D &g12a_cpu_clk_mux1_div.hw, + [CLKID_CPU_CLK_DYN1] =3D &g12a_cpu_clk_postmux1.hw, + [CLKID_CPU_CLK_DYN] =3D &g12a_cpu_clk_dyn.hw, + [CLKID_CPU_CLK] =3D &g12a_cpu_clk.hw, + [CLKID_CPU_CLK_DIV16_EN] =3D &g12a_cpu_clk_div16_en.hw, + [CLKID_CPU_CLK_DIV16] =3D &g12a_cpu_clk_div16.hw, + [CLKID_CPU_CLK_APB_DIV] =3D &g12a_cpu_clk_apb_div.hw, + [CLKID_CPU_CLK_APB] =3D &g12a_cpu_clk_apb.hw, + [CLKID_CPU_CLK_ATB_DIV] =3D &g12a_cpu_clk_atb_div.hw, + [CLKID_CPU_CLK_ATB] =3D &g12a_cpu_clk_atb.hw, + [CLKID_CPU_CLK_AXI_DIV] =3D &g12a_cpu_clk_axi_div.hw, + [CLKID_CPU_CLK_AXI] =3D &g12a_cpu_clk_axi.hw, + [CLKID_CPU_CLK_TRACE_DIV] =3D &g12a_cpu_clk_trace_div.hw, + [CLKID_CPU_CLK_TRACE] =3D &g12a_cpu_clk_trace.hw, + [CLKID_PCIE_PLL_DCO] =3D &g12a_pcie_pll_dco.hw, + [CLKID_PCIE_PLL_DCO_DIV2] =3D &g12a_pcie_pll_dco_div2.hw, + [CLKID_PCIE_PLL_OD] =3D &g12a_pcie_pll_od.hw, + [CLKID_PCIE_PLL] =3D &g12a_pcie_pll.hw, + [CLKID_VDEC_1_SEL] =3D &g12a_vdec_1_sel.hw, + [CLKID_VDEC_1_DIV] =3D &g12a_vdec_1_div.hw, + [CLKID_VDEC_1] =3D &g12a_vdec_1.hw, + [CLKID_VDEC_HEVC_SEL] =3D &g12a_vdec_hevc_sel.hw, + [CLKID_VDEC_HEVC_DIV] =3D &g12a_vdec_hevc_div.hw, + [CLKID_VDEC_HEVC] =3D &g12a_vdec_hevc.hw, + [CLKID_VDEC_HEVCF_SEL] =3D &g12a_vdec_hevcf_sel.hw, + [CLKID_VDEC_HEVCF_DIV] =3D &g12a_vdec_hevcf_div.hw, + [CLKID_VDEC_HEVCF] =3D &g12a_vdec_hevcf.hw, + [CLKID_TS_DIV] =3D &g12a_ts_div.hw, + [CLKID_TS] =3D &g12a_ts.hw, + [CLKID_GP1_PLL_DCO] =3D &sm1_gp1_pll_dco.hw, + [CLKID_GP1_PLL] =3D &sm1_gp1_pll.hw, + [CLKID_DSU_CLK_DYN0_SEL] =3D &sm1_dsu_clk_premux0.hw, + [CLKID_DSU_CLK_DYN0_DIV] =3D &sm1_dsu_clk_premux1.hw, + [CLKID_DSU_CLK_DYN0] =3D &sm1_dsu_clk_mux0_div.hw, + [CLKID_DSU_CLK_DYN1_SEL] =3D &sm1_dsu_clk_postmux0.hw, + [CLKID_DSU_CLK_DYN1_DIV] =3D &sm1_dsu_clk_mux1_div.hw, + [CLKID_DSU_CLK_DYN1] =3D &sm1_dsu_clk_postmux1.hw, + [CLKID_DSU_CLK_DYN] =3D &sm1_dsu_clk_dyn.hw, + [CLKID_DSU_CLK_FINAL] =3D &sm1_dsu_final_clk.hw, + [CLKID_DSU_CLK] =3D &sm1_dsu_clk.hw, + [CLKID_CPU1_CLK] =3D &sm1_cpu1_clk.hw, + [CLKID_CPU2_CLK] =3D &sm1_cpu2_clk.hw, + [CLKID_CPU3_CLK] =3D &sm1_cpu3_clk.hw, + [CLKID_SPICC0_SCLK_SEL] =3D &g12a_spicc0_sclk_sel.hw, + [CLKID_SPICC0_SCLK_DIV] =3D &g12a_spicc0_sclk_div.hw, + [CLKID_SPICC0_SCLK] =3D &g12a_spicc0_sclk.hw, + [CLKID_SPICC1_SCLK_SEL] =3D &g12a_spicc1_sclk_sel.hw, + [CLKID_SPICC1_SCLK_DIV] =3D &g12a_spicc1_sclk_div.hw, + [CLKID_SPICC1_SCLK] =3D &g12a_spicc1_sclk.hw, + [CLKID_NNA_AXI_CLK_SEL] =3D &sm1_nna_axi_clk_sel.hw, + [CLKID_NNA_AXI_CLK_DIV] =3D &sm1_nna_axi_clk_div.hw, + [CLKID_NNA_AXI_CLK] =3D &sm1_nna_axi_clk.hw, + [CLKID_NNA_CORE_CLK_SEL] =3D &sm1_nna_core_clk_sel.hw, + [CLKID_NNA_CORE_CLK_DIV] =3D &sm1_nna_core_clk_div.hw, + [CLKID_NNA_CORE_CLK] =3D &sm1_nna_core_clk.hw, + [CLKID_MIPI_DSI_PXCLK_SEL] =3D &g12a_mipi_dsi_pxclk_sel.hw, + [CLKID_MIPI_DSI_PXCLK_DIV] =3D &g12a_mipi_dsi_pxclk_div.hw, + [CLKID_MIPI_DSI_PXCLK] =3D &g12a_mipi_dsi_pxclk.hw, }; =20 /* Convenience table to populate regmap in .probe */ @@ -5274,7 +5262,7 @@ static int meson_g12a_dvfs_setup_common(struct device= *dev, =20 static int meson_g12b_dvfs_setup(struct platform_device *pdev) { - struct clk_hw **hws =3D g12b_hw_onecell_data.hws; + struct clk_hw **hws =3D g12b_hw_clks; struct device *dev =3D &pdev->dev; struct clk *notifier_clk; struct clk_hw *xtal; @@ -5351,7 +5339,7 @@ static int meson_g12b_dvfs_setup(struct platform_devi= ce *pdev) =20 static int meson_g12a_dvfs_setup(struct platform_device *pdev) { - struct clk_hw **hws =3D g12a_hw_onecell_data.hws; + struct clk_hw **hws =3D g12a_hw_clks; struct device *dev =3D &pdev->dev; struct clk *notifier_clk; int ret; @@ -5413,7 +5401,10 @@ static const struct meson_g12a_data g12a_clkc_data = =3D { .eeclkc_data =3D { .regmap_clks =3D g12a_clk_regmaps, .regmap_clk_num =3D ARRAY_SIZE(g12a_clk_regmaps), - .hw_onecell_data =3D &g12a_hw_onecell_data, + .hw_clks =3D { + .hws =3D g12a_hw_clks, + .num =3D ARRAY_SIZE(g12a_hw_clks), + }, .init_regs =3D g12a_init_regs, .init_count =3D ARRAY_SIZE(g12a_init_regs), }, @@ -5424,7 +5415,10 @@ static const struct meson_g12a_data g12b_clkc_data = =3D { .eeclkc_data =3D { .regmap_clks =3D g12a_clk_regmaps, .regmap_clk_num =3D ARRAY_SIZE(g12a_clk_regmaps), - .hw_onecell_data =3D &g12b_hw_onecell_data, + .hw_clks =3D { + .hws =3D g12b_hw_clks, + .num =3D ARRAY_SIZE(g12b_hw_clks), + }, }, .dvfs_setup =3D meson_g12b_dvfs_setup, }; @@ -5433,7 +5427,10 @@ static const struct meson_g12a_data sm1_clkc_data = =3D { .eeclkc_data =3D { .regmap_clks =3D g12a_clk_regmaps, .regmap_clk_num =3D ARRAY_SIZE(g12a_clk_regmaps), - .hw_onecell_data =3D &sm1_hw_onecell_data, + .hw_clks =3D { + .hws =3D sm1_hw_clks, + .num =3D ARRAY_SIZE(sm1_hw_clks), + }, }, .dvfs_setup =3D meson_g12a_dvfs_setup, }; diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h index a97613df38b3..a70a0cba892b 100644 --- a/drivers/clk/meson/g12a.h +++ b/drivers/clk/meson/g12a.h @@ -266,8 +266,6 @@ #define CLKID_NNA_CORE_CLK_DIV 266 #define CLKID_MIPI_DSI_PXCLK_DIV 268 =20 -#define NR_CLKS 271 - /* include the CLKIDs that have been made part of the DT binding */ #include =20 diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 608e0e8ca49a..116fcb6ba160 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -2728,428 +2728,420 @@ static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &= gxbb_aiu_glue.hw); =20 /* Array of all clocks provided by this provider */ =20 -static struct clk_hw_onecell_data gxbb_hw_onecell_data =3D { - .hws =3D { - [CLKID_SYS_PLL] =3D &gxbb_sys_pll.hw, - [CLKID_HDMI_PLL] =3D &gxbb_hdmi_pll.hw, - [CLKID_FIXED_PLL] =3D &gxbb_fixed_pll.hw, - [CLKID_FCLK_DIV2] =3D &gxbb_fclk_div2.hw, - [CLKID_FCLK_DIV3] =3D &gxbb_fclk_div3.hw, - [CLKID_FCLK_DIV4] =3D &gxbb_fclk_div4.hw, - [CLKID_FCLK_DIV5] =3D &gxbb_fclk_div5.hw, - [CLKID_FCLK_DIV7] =3D &gxbb_fclk_div7.hw, - [CLKID_GP0_PLL] =3D &gxbb_gp0_pll.hw, - [CLKID_MPEG_SEL] =3D &gxbb_mpeg_clk_sel.hw, - [CLKID_MPEG_DIV] =3D &gxbb_mpeg_clk_div.hw, - [CLKID_CLK81] =3D &gxbb_clk81.hw, - [CLKID_MPLL0] =3D &gxbb_mpll0.hw, - [CLKID_MPLL1] =3D &gxbb_mpll1.hw, - [CLKID_MPLL2] =3D &gxbb_mpll2.hw, - [CLKID_DDR] =3D &gxbb_ddr.hw, - [CLKID_DOS] =3D &gxbb_dos.hw, - [CLKID_ISA] =3D &gxbb_isa.hw, - [CLKID_PL301] =3D &gxbb_pl301.hw, - [CLKID_PERIPHS] =3D &gxbb_periphs.hw, - [CLKID_SPICC] =3D &gxbb_spicc.hw, - [CLKID_I2C] =3D &gxbb_i2c.hw, - [CLKID_SAR_ADC] =3D &gxbb_sar_adc.hw, - [CLKID_SMART_CARD] =3D &gxbb_smart_card.hw, - [CLKID_RNG0] =3D &gxbb_rng0.hw, - [CLKID_UART0] =3D &gxbb_uart0.hw, - [CLKID_SDHC] =3D &gxbb_sdhc.hw, - [CLKID_STREAM] =3D &gxbb_stream.hw, - [CLKID_ASYNC_FIFO] =3D &gxbb_async_fifo.hw, - [CLKID_SDIO] =3D &gxbb_sdio.hw, - [CLKID_ABUF] =3D &gxbb_abuf.hw, - [CLKID_HIU_IFACE] =3D &gxbb_hiu_iface.hw, - [CLKID_ASSIST_MISC] =3D &gxbb_assist_misc.hw, - [CLKID_SPI] =3D &gxbb_spi.hw, - [CLKID_I2S_SPDIF] =3D &gxbb_i2s_spdif.hw, - [CLKID_ETH] =3D &gxbb_eth.hw, - [CLKID_DEMUX] =3D &gxbb_demux.hw, - [CLKID_AIU_GLUE] =3D &gxbb_aiu_glue.hw, - [CLKID_IEC958] =3D &gxbb_iec958.hw, - [CLKID_I2S_OUT] =3D &gxbb_i2s_out.hw, - [CLKID_AMCLK] =3D &gxbb_amclk.hw, - [CLKID_AIFIFO2] =3D &gxbb_aififo2.hw, - [CLKID_MIXER] =3D &gxbb_mixer.hw, - [CLKID_MIXER_IFACE] =3D &gxbb_mixer_iface.hw, - [CLKID_ADC] =3D &gxbb_adc.hw, - [CLKID_BLKMV] =3D &gxbb_blkmv.hw, - [CLKID_AIU] =3D &gxbb_aiu.hw, - [CLKID_UART1] =3D &gxbb_uart1.hw, - [CLKID_G2D] =3D &gxbb_g2d.hw, - [CLKID_USB0] =3D &gxbb_usb0.hw, - [CLKID_USB1] =3D &gxbb_usb1.hw, - [CLKID_RESET] =3D &gxbb_reset.hw, - [CLKID_NAND] =3D &gxbb_nand.hw, - [CLKID_DOS_PARSER] =3D &gxbb_dos_parser.hw, - [CLKID_USB] =3D &gxbb_usb.hw, - [CLKID_VDIN1] =3D &gxbb_vdin1.hw, - [CLKID_AHB_ARB0] =3D &gxbb_ahb_arb0.hw, - [CLKID_EFUSE] =3D &gxbb_efuse.hw, - [CLKID_BOOT_ROM] =3D &gxbb_boot_rom.hw, - [CLKID_AHB_DATA_BUS] =3D &gxbb_ahb_data_bus.hw, - [CLKID_AHB_CTRL_BUS] =3D &gxbb_ahb_ctrl_bus.hw, - [CLKID_HDMI_INTR_SYNC] =3D &gxbb_hdmi_intr_sync.hw, - [CLKID_HDMI_PCLK] =3D &gxbb_hdmi_pclk.hw, - [CLKID_USB1_DDR_BRIDGE] =3D &gxbb_usb1_ddr_bridge.hw, - [CLKID_USB0_DDR_BRIDGE] =3D &gxbb_usb0_ddr_bridge.hw, - [CLKID_MMC_PCLK] =3D &gxbb_mmc_pclk.hw, - [CLKID_DVIN] =3D &gxbb_dvin.hw, - [CLKID_UART2] =3D &gxbb_uart2.hw, - [CLKID_SANA] =3D &gxbb_sana.hw, - [CLKID_VPU_INTR] =3D &gxbb_vpu_intr.hw, - [CLKID_SEC_AHB_AHB3_BRIDGE] =3D &gxbb_sec_ahb_ahb3_bridge.hw, - [CLKID_CLK81_A53] =3D &gxbb_clk81_a53.hw, - [CLKID_VCLK2_VENCI0] =3D &gxbb_vclk2_venci0.hw, - [CLKID_VCLK2_VENCI1] =3D &gxbb_vclk2_venci1.hw, - [CLKID_VCLK2_VENCP0] =3D &gxbb_vclk2_vencp0.hw, - [CLKID_VCLK2_VENCP1] =3D &gxbb_vclk2_vencp1.hw, - [CLKID_GCLK_VENCI_INT0] =3D &gxbb_gclk_venci_int0.hw, - [CLKID_GCLK_VENCI_INT] =3D &gxbb_gclk_vencp_int.hw, - [CLKID_DAC_CLK] =3D &gxbb_dac_clk.hw, - [CLKID_AOCLK_GATE] =3D &gxbb_aoclk_gate.hw, - [CLKID_IEC958_GATE] =3D &gxbb_iec958_gate.hw, - [CLKID_ENC480P] =3D &gxbb_enc480p.hw, - [CLKID_RNG1] =3D &gxbb_rng1.hw, - [CLKID_GCLK_VENCI_INT1] =3D &gxbb_gclk_venci_int1.hw, - [CLKID_VCLK2_VENCLMCC] =3D &gxbb_vclk2_venclmcc.hw, - [CLKID_VCLK2_VENCL] =3D &gxbb_vclk2_vencl.hw, - [CLKID_VCLK_OTHER] =3D &gxbb_vclk_other.hw, - [CLKID_EDP] =3D &gxbb_edp.hw, - [CLKID_AO_MEDIA_CPU] =3D &gxbb_ao_media_cpu.hw, - [CLKID_AO_AHB_SRAM] =3D &gxbb_ao_ahb_sram.hw, - [CLKID_AO_AHB_BUS] =3D &gxbb_ao_ahb_bus.hw, - [CLKID_AO_IFACE] =3D &gxbb_ao_iface.hw, - [CLKID_AO_I2C] =3D &gxbb_ao_i2c.hw, - [CLKID_SD_EMMC_A] =3D &gxbb_emmc_a.hw, - [CLKID_SD_EMMC_B] =3D &gxbb_emmc_b.hw, - [CLKID_SD_EMMC_C] =3D &gxbb_emmc_c.hw, - [CLKID_SAR_ADC_CLK] =3D &gxbb_sar_adc_clk.hw, - [CLKID_SAR_ADC_SEL] =3D &gxbb_sar_adc_clk_sel.hw, - [CLKID_SAR_ADC_DIV] =3D &gxbb_sar_adc_clk_div.hw, - [CLKID_MALI_0_SEL] =3D &gxbb_mali_0_sel.hw, - [CLKID_MALI_0_DIV] =3D &gxbb_mali_0_div.hw, - [CLKID_MALI_0] =3D &gxbb_mali_0.hw, - [CLKID_MALI_1_SEL] =3D &gxbb_mali_1_sel.hw, - [CLKID_MALI_1_DIV] =3D &gxbb_mali_1_div.hw, - [CLKID_MALI_1] =3D &gxbb_mali_1.hw, - [CLKID_MALI] =3D &gxbb_mali.hw, - [CLKID_CTS_AMCLK] =3D &gxbb_cts_amclk.hw, - [CLKID_CTS_AMCLK_SEL] =3D &gxbb_cts_amclk_sel.hw, - [CLKID_CTS_AMCLK_DIV] =3D &gxbb_cts_amclk_div.hw, - [CLKID_CTS_MCLK_I958] =3D &gxbb_cts_mclk_i958.hw, - [CLKID_CTS_MCLK_I958_SEL] =3D &gxbb_cts_mclk_i958_sel.hw, - [CLKID_CTS_MCLK_I958_DIV] =3D &gxbb_cts_mclk_i958_div.hw, - [CLKID_CTS_I958] =3D &gxbb_cts_i958.hw, - [CLKID_32K_CLK] =3D &gxbb_32k_clk.hw, - [CLKID_32K_CLK_SEL] =3D &gxbb_32k_clk_sel.hw, - [CLKID_32K_CLK_DIV] =3D &gxbb_32k_clk_div.hw, - [CLKID_SD_EMMC_A_CLK0_SEL] =3D &gxbb_sd_emmc_a_clk0_sel.hw, - [CLKID_SD_EMMC_A_CLK0_DIV] =3D &gxbb_sd_emmc_a_clk0_div.hw, - [CLKID_SD_EMMC_A_CLK0] =3D &gxbb_sd_emmc_a_clk0.hw, - [CLKID_SD_EMMC_B_CLK0_SEL] =3D &gxbb_sd_emmc_b_clk0_sel.hw, - [CLKID_SD_EMMC_B_CLK0_DIV] =3D &gxbb_sd_emmc_b_clk0_div.hw, - [CLKID_SD_EMMC_B_CLK0] =3D &gxbb_sd_emmc_b_clk0.hw, - [CLKID_SD_EMMC_C_CLK0_SEL] =3D &gxbb_sd_emmc_c_clk0_sel.hw, - [CLKID_SD_EMMC_C_CLK0_DIV] =3D &gxbb_sd_emmc_c_clk0_div.hw, - [CLKID_SD_EMMC_C_CLK0] =3D &gxbb_sd_emmc_c_clk0.hw, - [CLKID_VPU_0_SEL] =3D &gxbb_vpu_0_sel.hw, - [CLKID_VPU_0_DIV] =3D &gxbb_vpu_0_div.hw, - [CLKID_VPU_0] =3D &gxbb_vpu_0.hw, - [CLKID_VPU_1_SEL] =3D &gxbb_vpu_1_sel.hw, - [CLKID_VPU_1_DIV] =3D &gxbb_vpu_1_div.hw, - [CLKID_VPU_1] =3D &gxbb_vpu_1.hw, - [CLKID_VPU] =3D &gxbb_vpu.hw, - [CLKID_VAPB_0_SEL] =3D &gxbb_vapb_0_sel.hw, - [CLKID_VAPB_0_DIV] =3D &gxbb_vapb_0_div.hw, - [CLKID_VAPB_0] =3D &gxbb_vapb_0.hw, - [CLKID_VAPB_1_SEL] =3D &gxbb_vapb_1_sel.hw, - [CLKID_VAPB_1_DIV] =3D &gxbb_vapb_1_div.hw, - [CLKID_VAPB_1] =3D &gxbb_vapb_1.hw, - [CLKID_VAPB_SEL] =3D &gxbb_vapb_sel.hw, - [CLKID_VAPB] =3D &gxbb_vapb.hw, - [CLKID_HDMI_PLL_PRE_MULT] =3D &gxbb_hdmi_pll_pre_mult.hw, - [CLKID_MPLL0_DIV] =3D &gxbb_mpll0_div.hw, - [CLKID_MPLL1_DIV] =3D &gxbb_mpll1_div.hw, - [CLKID_MPLL2_DIV] =3D &gxbb_mpll2_div.hw, - [CLKID_MPLL_PREDIV] =3D &gxbb_mpll_prediv.hw, - [CLKID_FCLK_DIV2_DIV] =3D &gxbb_fclk_div2_div.hw, - [CLKID_FCLK_DIV3_DIV] =3D &gxbb_fclk_div3_div.hw, - [CLKID_FCLK_DIV4_DIV] =3D &gxbb_fclk_div4_div.hw, - [CLKID_FCLK_DIV5_DIV] =3D &gxbb_fclk_div5_div.hw, - [CLKID_FCLK_DIV7_DIV] =3D &gxbb_fclk_div7_div.hw, - [CLKID_VDEC_1_SEL] =3D &gxbb_vdec_1_sel.hw, - [CLKID_VDEC_1_DIV] =3D &gxbb_vdec_1_div.hw, - [CLKID_VDEC_1] =3D &gxbb_vdec_1.hw, - [CLKID_VDEC_HEVC_SEL] =3D &gxbb_vdec_hevc_sel.hw, - [CLKID_VDEC_HEVC_DIV] =3D &gxbb_vdec_hevc_div.hw, - [CLKID_VDEC_HEVC] =3D &gxbb_vdec_hevc.hw, - [CLKID_GEN_CLK_SEL] =3D &gxbb_gen_clk_sel.hw, - [CLKID_GEN_CLK_DIV] =3D &gxbb_gen_clk_div.hw, - [CLKID_GEN_CLK] =3D &gxbb_gen_clk.hw, - [CLKID_FIXED_PLL_DCO] =3D &gxbb_fixed_pll_dco.hw, - [CLKID_HDMI_PLL_DCO] =3D &gxbb_hdmi_pll_dco.hw, - [CLKID_HDMI_PLL_OD] =3D &gxbb_hdmi_pll_od.hw, - [CLKID_HDMI_PLL_OD2] =3D &gxbb_hdmi_pll_od2.hw, - [CLKID_SYS_PLL_DCO] =3D &gxbb_sys_pll_dco.hw, - [CLKID_GP0_PLL_DCO] =3D &gxbb_gp0_pll_dco.hw, - [CLKID_VID_PLL_DIV] =3D &gxbb_vid_pll_div.hw, - [CLKID_VID_PLL_SEL] =3D &gxbb_vid_pll_sel.hw, - [CLKID_VID_PLL] =3D &gxbb_vid_pll.hw, - [CLKID_VCLK_SEL] =3D &gxbb_vclk_sel.hw, - [CLKID_VCLK2_SEL] =3D &gxbb_vclk2_sel.hw, - [CLKID_VCLK_INPUT] =3D &gxbb_vclk_input.hw, - [CLKID_VCLK2_INPUT] =3D &gxbb_vclk2_input.hw, - [CLKID_VCLK_DIV] =3D &gxbb_vclk_div.hw, - [CLKID_VCLK2_DIV] =3D &gxbb_vclk2_div.hw, - [CLKID_VCLK] =3D &gxbb_vclk.hw, - [CLKID_VCLK2] =3D &gxbb_vclk2.hw, - [CLKID_VCLK_DIV1] =3D &gxbb_vclk_div1.hw, - [CLKID_VCLK_DIV2_EN] =3D &gxbb_vclk_div2_en.hw, - [CLKID_VCLK_DIV2] =3D &gxbb_vclk_div2.hw, - [CLKID_VCLK_DIV4_EN] =3D &gxbb_vclk_div4_en.hw, - [CLKID_VCLK_DIV4] =3D &gxbb_vclk_div4.hw, - [CLKID_VCLK_DIV6_EN] =3D &gxbb_vclk_div6_en.hw, - [CLKID_VCLK_DIV6] =3D &gxbb_vclk_div6.hw, - [CLKID_VCLK_DIV12_EN] =3D &gxbb_vclk_div12_en.hw, - [CLKID_VCLK_DIV12] =3D &gxbb_vclk_div12.hw, - [CLKID_VCLK2_DIV1] =3D &gxbb_vclk2_div1.hw, - [CLKID_VCLK2_DIV2_EN] =3D &gxbb_vclk2_div2_en.hw, - [CLKID_VCLK2_DIV2] =3D &gxbb_vclk2_div2.hw, - [CLKID_VCLK2_DIV4_EN] =3D &gxbb_vclk2_div4_en.hw, - [CLKID_VCLK2_DIV4] =3D &gxbb_vclk2_div4.hw, - [CLKID_VCLK2_DIV6_EN] =3D &gxbb_vclk2_div6_en.hw, - [CLKID_VCLK2_DIV6] =3D &gxbb_vclk2_div6.hw, - [CLKID_VCLK2_DIV12_EN] =3D &gxbb_vclk2_div12_en.hw, - [CLKID_VCLK2_DIV12] =3D &gxbb_vclk2_div12.hw, - [CLKID_CTS_ENCI_SEL] =3D &gxbb_cts_enci_sel.hw, - [CLKID_CTS_ENCP_SEL] =3D &gxbb_cts_encp_sel.hw, - [CLKID_CTS_VDAC_SEL] =3D &gxbb_cts_vdac_sel.hw, - [CLKID_HDMI_TX_SEL] =3D &gxbb_hdmi_tx_sel.hw, - [CLKID_CTS_ENCI] =3D &gxbb_cts_enci.hw, - [CLKID_CTS_ENCP] =3D &gxbb_cts_encp.hw, - [CLKID_CTS_VDAC] =3D &gxbb_cts_vdac.hw, - [CLKID_HDMI_TX] =3D &gxbb_hdmi_tx.hw, - [CLKID_HDMI_SEL] =3D &gxbb_hdmi_sel.hw, - [CLKID_HDMI_DIV] =3D &gxbb_hdmi_div.hw, - [CLKID_HDMI] =3D &gxbb_hdmi.hw, - [NR_CLKS] =3D NULL, - }, - .num =3D NR_CLKS, -}; - -static struct clk_hw_onecell_data gxl_hw_onecell_data =3D { - .hws =3D { - [CLKID_SYS_PLL] =3D &gxbb_sys_pll.hw, - [CLKID_HDMI_PLL] =3D &gxl_hdmi_pll.hw, - [CLKID_FIXED_PLL] =3D &gxbb_fixed_pll.hw, - [CLKID_FCLK_DIV2] =3D &gxbb_fclk_div2.hw, - [CLKID_FCLK_DIV3] =3D &gxbb_fclk_div3.hw, - [CLKID_FCLK_DIV4] =3D &gxbb_fclk_div4.hw, - [CLKID_FCLK_DIV5] =3D &gxbb_fclk_div5.hw, - [CLKID_FCLK_DIV7] =3D &gxbb_fclk_div7.hw, - [CLKID_GP0_PLL] =3D &gxbb_gp0_pll.hw, - [CLKID_MPEG_SEL] =3D &gxbb_mpeg_clk_sel.hw, - [CLKID_MPEG_DIV] =3D &gxbb_mpeg_clk_div.hw, - [CLKID_CLK81] =3D &gxbb_clk81.hw, - [CLKID_MPLL0] =3D &gxbb_mpll0.hw, - [CLKID_MPLL1] =3D &gxbb_mpll1.hw, - [CLKID_MPLL2] =3D &gxbb_mpll2.hw, - [CLKID_DDR] =3D &gxbb_ddr.hw, - [CLKID_DOS] =3D &gxbb_dos.hw, - [CLKID_ISA] =3D &gxbb_isa.hw, - [CLKID_PL301] =3D &gxbb_pl301.hw, - [CLKID_PERIPHS] =3D &gxbb_periphs.hw, - [CLKID_SPICC] =3D &gxbb_spicc.hw, - [CLKID_I2C] =3D &gxbb_i2c.hw, - [CLKID_SAR_ADC] =3D &gxbb_sar_adc.hw, - [CLKID_SMART_CARD] =3D &gxbb_smart_card.hw, - [CLKID_RNG0] =3D &gxbb_rng0.hw, - [CLKID_UART0] =3D &gxbb_uart0.hw, - [CLKID_SDHC] =3D &gxbb_sdhc.hw, - [CLKID_STREAM] =3D &gxbb_stream.hw, - [CLKID_ASYNC_FIFO] =3D &gxbb_async_fifo.hw, - [CLKID_SDIO] =3D &gxbb_sdio.hw, - [CLKID_ABUF] =3D &gxbb_abuf.hw, - [CLKID_HIU_IFACE] =3D &gxbb_hiu_iface.hw, - [CLKID_ASSIST_MISC] =3D &gxbb_assist_misc.hw, - [CLKID_SPI] =3D &gxbb_spi.hw, - [CLKID_I2S_SPDIF] =3D &gxbb_i2s_spdif.hw, - [CLKID_ETH] =3D &gxbb_eth.hw, - [CLKID_DEMUX] =3D &gxbb_demux.hw, - [CLKID_AIU_GLUE] =3D &gxbb_aiu_glue.hw, - [CLKID_IEC958] =3D &gxbb_iec958.hw, - [CLKID_I2S_OUT] =3D &gxbb_i2s_out.hw, - [CLKID_AMCLK] =3D &gxbb_amclk.hw, - [CLKID_AIFIFO2] =3D &gxbb_aififo2.hw, - [CLKID_MIXER] =3D &gxbb_mixer.hw, - [CLKID_MIXER_IFACE] =3D &gxbb_mixer_iface.hw, - [CLKID_ADC] =3D &gxbb_adc.hw, - [CLKID_BLKMV] =3D &gxbb_blkmv.hw, - [CLKID_AIU] =3D &gxbb_aiu.hw, - [CLKID_UART1] =3D &gxbb_uart1.hw, - [CLKID_G2D] =3D &gxbb_g2d.hw, - [CLKID_USB0] =3D &gxbb_usb0.hw, - [CLKID_USB1] =3D &gxbb_usb1.hw, - [CLKID_RESET] =3D &gxbb_reset.hw, - [CLKID_NAND] =3D &gxbb_nand.hw, - [CLKID_DOS_PARSER] =3D &gxbb_dos_parser.hw, - [CLKID_USB] =3D &gxbb_usb.hw, - [CLKID_VDIN1] =3D &gxbb_vdin1.hw, - [CLKID_AHB_ARB0] =3D &gxbb_ahb_arb0.hw, - [CLKID_EFUSE] =3D &gxbb_efuse.hw, - [CLKID_BOOT_ROM] =3D &gxbb_boot_rom.hw, - [CLKID_AHB_DATA_BUS] =3D &gxbb_ahb_data_bus.hw, - [CLKID_AHB_CTRL_BUS] =3D &gxbb_ahb_ctrl_bus.hw, - [CLKID_HDMI_INTR_SYNC] =3D &gxbb_hdmi_intr_sync.hw, - [CLKID_HDMI_PCLK] =3D &gxbb_hdmi_pclk.hw, - [CLKID_USB1_DDR_BRIDGE] =3D &gxbb_usb1_ddr_bridge.hw, - [CLKID_USB0_DDR_BRIDGE] =3D &gxbb_usb0_ddr_bridge.hw, - [CLKID_MMC_PCLK] =3D &gxbb_mmc_pclk.hw, - [CLKID_DVIN] =3D &gxbb_dvin.hw, - [CLKID_UART2] =3D &gxbb_uart2.hw, - [CLKID_SANA] =3D &gxbb_sana.hw, - [CLKID_VPU_INTR] =3D &gxbb_vpu_intr.hw, - [CLKID_SEC_AHB_AHB3_BRIDGE] =3D &gxbb_sec_ahb_ahb3_bridge.hw, - [CLKID_CLK81_A53] =3D &gxbb_clk81_a53.hw, - [CLKID_VCLK2_VENCI0] =3D &gxbb_vclk2_venci0.hw, - [CLKID_VCLK2_VENCI1] =3D &gxbb_vclk2_venci1.hw, - [CLKID_VCLK2_VENCP0] =3D &gxbb_vclk2_vencp0.hw, - [CLKID_VCLK2_VENCP1] =3D &gxbb_vclk2_vencp1.hw, - [CLKID_GCLK_VENCI_INT0] =3D &gxbb_gclk_venci_int0.hw, - [CLKID_GCLK_VENCI_INT] =3D &gxbb_gclk_vencp_int.hw, - [CLKID_DAC_CLK] =3D &gxbb_dac_clk.hw, - [CLKID_AOCLK_GATE] =3D &gxbb_aoclk_gate.hw, - [CLKID_IEC958_GATE] =3D &gxbb_iec958_gate.hw, - [CLKID_ENC480P] =3D &gxbb_enc480p.hw, - [CLKID_RNG1] =3D &gxbb_rng1.hw, - [CLKID_GCLK_VENCI_INT1] =3D &gxbb_gclk_venci_int1.hw, - [CLKID_VCLK2_VENCLMCC] =3D &gxbb_vclk2_venclmcc.hw, - [CLKID_VCLK2_VENCL] =3D &gxbb_vclk2_vencl.hw, - [CLKID_VCLK_OTHER] =3D &gxbb_vclk_other.hw, - [CLKID_EDP] =3D &gxbb_edp.hw, - [CLKID_AO_MEDIA_CPU] =3D &gxbb_ao_media_cpu.hw, - [CLKID_AO_AHB_SRAM] =3D &gxbb_ao_ahb_sram.hw, - [CLKID_AO_AHB_BUS] =3D &gxbb_ao_ahb_bus.hw, - [CLKID_AO_IFACE] =3D &gxbb_ao_iface.hw, - [CLKID_AO_I2C] =3D &gxbb_ao_i2c.hw, - [CLKID_SD_EMMC_A] =3D &gxbb_emmc_a.hw, - [CLKID_SD_EMMC_B] =3D &gxbb_emmc_b.hw, - [CLKID_SD_EMMC_C] =3D &gxbb_emmc_c.hw, - [CLKID_SAR_ADC_CLK] =3D &gxbb_sar_adc_clk.hw, - [CLKID_SAR_ADC_SEL] =3D &gxbb_sar_adc_clk_sel.hw, - [CLKID_SAR_ADC_DIV] =3D &gxbb_sar_adc_clk_div.hw, - [CLKID_MALI_0_SEL] =3D &gxbb_mali_0_sel.hw, - [CLKID_MALI_0_DIV] =3D &gxbb_mali_0_div.hw, - [CLKID_MALI_0] =3D &gxbb_mali_0.hw, - [CLKID_MALI_1_SEL] =3D &gxbb_mali_1_sel.hw, - [CLKID_MALI_1_DIV] =3D &gxbb_mali_1_div.hw, - [CLKID_MALI_1] =3D &gxbb_mali_1.hw, - [CLKID_MALI] =3D &gxbb_mali.hw, - [CLKID_CTS_AMCLK] =3D &gxbb_cts_amclk.hw, - [CLKID_CTS_AMCLK_SEL] =3D &gxbb_cts_amclk_sel.hw, - [CLKID_CTS_AMCLK_DIV] =3D &gxbb_cts_amclk_div.hw, - [CLKID_CTS_MCLK_I958] =3D &gxbb_cts_mclk_i958.hw, - [CLKID_CTS_MCLK_I958_SEL] =3D &gxbb_cts_mclk_i958_sel.hw, - [CLKID_CTS_MCLK_I958_DIV] =3D &gxbb_cts_mclk_i958_div.hw, - [CLKID_CTS_I958] =3D &gxbb_cts_i958.hw, - [CLKID_32K_CLK] =3D &gxbb_32k_clk.hw, - [CLKID_32K_CLK_SEL] =3D &gxbb_32k_clk_sel.hw, - [CLKID_32K_CLK_DIV] =3D &gxbb_32k_clk_div.hw, - [CLKID_SD_EMMC_A_CLK0_SEL] =3D &gxbb_sd_emmc_a_clk0_sel.hw, - [CLKID_SD_EMMC_A_CLK0_DIV] =3D &gxbb_sd_emmc_a_clk0_div.hw, - [CLKID_SD_EMMC_A_CLK0] =3D &gxbb_sd_emmc_a_clk0.hw, - [CLKID_SD_EMMC_B_CLK0_SEL] =3D &gxbb_sd_emmc_b_clk0_sel.hw, - [CLKID_SD_EMMC_B_CLK0_DIV] =3D &gxbb_sd_emmc_b_clk0_div.hw, - [CLKID_SD_EMMC_B_CLK0] =3D &gxbb_sd_emmc_b_clk0.hw, - [CLKID_SD_EMMC_C_CLK0_SEL] =3D &gxbb_sd_emmc_c_clk0_sel.hw, - [CLKID_SD_EMMC_C_CLK0_DIV] =3D &gxbb_sd_emmc_c_clk0_div.hw, - [CLKID_SD_EMMC_C_CLK0] =3D &gxbb_sd_emmc_c_clk0.hw, - [CLKID_VPU_0_SEL] =3D &gxbb_vpu_0_sel.hw, - [CLKID_VPU_0_DIV] =3D &gxbb_vpu_0_div.hw, - [CLKID_VPU_0] =3D &gxbb_vpu_0.hw, - [CLKID_VPU_1_SEL] =3D &gxbb_vpu_1_sel.hw, - [CLKID_VPU_1_DIV] =3D &gxbb_vpu_1_div.hw, - [CLKID_VPU_1] =3D &gxbb_vpu_1.hw, - [CLKID_VPU] =3D &gxbb_vpu.hw, - [CLKID_VAPB_0_SEL] =3D &gxbb_vapb_0_sel.hw, - [CLKID_VAPB_0_DIV] =3D &gxbb_vapb_0_div.hw, - [CLKID_VAPB_0] =3D &gxbb_vapb_0.hw, - [CLKID_VAPB_1_SEL] =3D &gxbb_vapb_1_sel.hw, - [CLKID_VAPB_1_DIV] =3D &gxbb_vapb_1_div.hw, - [CLKID_VAPB_1] =3D &gxbb_vapb_1.hw, - [CLKID_VAPB_SEL] =3D &gxbb_vapb_sel.hw, - [CLKID_VAPB] =3D &gxbb_vapb.hw, - [CLKID_MPLL0_DIV] =3D &gxl_mpll0_div.hw, - [CLKID_MPLL1_DIV] =3D &gxbb_mpll1_div.hw, - [CLKID_MPLL2_DIV] =3D &gxbb_mpll2_div.hw, - [CLKID_MPLL_PREDIV] =3D &gxbb_mpll_prediv.hw, - [CLKID_FCLK_DIV2_DIV] =3D &gxbb_fclk_div2_div.hw, - [CLKID_FCLK_DIV3_DIV] =3D &gxbb_fclk_div3_div.hw, - [CLKID_FCLK_DIV4_DIV] =3D &gxbb_fclk_div4_div.hw, - [CLKID_FCLK_DIV5_DIV] =3D &gxbb_fclk_div5_div.hw, - [CLKID_FCLK_DIV7_DIV] =3D &gxbb_fclk_div7_div.hw, - [CLKID_VDEC_1_SEL] =3D &gxbb_vdec_1_sel.hw, - [CLKID_VDEC_1_DIV] =3D &gxbb_vdec_1_div.hw, - [CLKID_VDEC_1] =3D &gxbb_vdec_1.hw, - [CLKID_VDEC_HEVC_SEL] =3D &gxbb_vdec_hevc_sel.hw, - [CLKID_VDEC_HEVC_DIV] =3D &gxbb_vdec_hevc_div.hw, - [CLKID_VDEC_HEVC] =3D &gxbb_vdec_hevc.hw, - [CLKID_GEN_CLK_SEL] =3D &gxbb_gen_clk_sel.hw, - [CLKID_GEN_CLK_DIV] =3D &gxbb_gen_clk_div.hw, - [CLKID_GEN_CLK] =3D &gxbb_gen_clk.hw, - [CLKID_FIXED_PLL_DCO] =3D &gxbb_fixed_pll_dco.hw, - [CLKID_HDMI_PLL_DCO] =3D &gxl_hdmi_pll_dco.hw, - [CLKID_HDMI_PLL_OD] =3D &gxl_hdmi_pll_od.hw, - [CLKID_HDMI_PLL_OD2] =3D &gxl_hdmi_pll_od2.hw, - [CLKID_SYS_PLL_DCO] =3D &gxbb_sys_pll_dco.hw, - [CLKID_GP0_PLL_DCO] =3D &gxl_gp0_pll_dco.hw, - [CLKID_VID_PLL_DIV] =3D &gxbb_vid_pll_div.hw, - [CLKID_VID_PLL_SEL] =3D &gxbb_vid_pll_sel.hw, - [CLKID_VID_PLL] =3D &gxbb_vid_pll.hw, - [CLKID_VCLK_SEL] =3D &gxbb_vclk_sel.hw, - [CLKID_VCLK2_SEL] =3D &gxbb_vclk2_sel.hw, - [CLKID_VCLK_INPUT] =3D &gxbb_vclk_input.hw, - [CLKID_VCLK2_INPUT] =3D &gxbb_vclk2_input.hw, - [CLKID_VCLK_DIV] =3D &gxbb_vclk_div.hw, - [CLKID_VCLK2_DIV] =3D &gxbb_vclk2_div.hw, - [CLKID_VCLK] =3D &gxbb_vclk.hw, - [CLKID_VCLK2] =3D &gxbb_vclk2.hw, - [CLKID_VCLK_DIV1] =3D &gxbb_vclk_div1.hw, - [CLKID_VCLK_DIV2_EN] =3D &gxbb_vclk_div2_en.hw, - [CLKID_VCLK_DIV2] =3D &gxbb_vclk_div2.hw, - [CLKID_VCLK_DIV4_EN] =3D &gxbb_vclk_div4_en.hw, - [CLKID_VCLK_DIV4] =3D &gxbb_vclk_div4.hw, - [CLKID_VCLK_DIV6_EN] =3D &gxbb_vclk_div6_en.hw, - [CLKID_VCLK_DIV6] =3D &gxbb_vclk_div6.hw, - [CLKID_VCLK_DIV12_EN] =3D &gxbb_vclk_div12_en.hw, - [CLKID_VCLK_DIV12] =3D &gxbb_vclk_div12.hw, - [CLKID_VCLK2_DIV1] =3D &gxbb_vclk2_div1.hw, - [CLKID_VCLK2_DIV2_EN] =3D &gxbb_vclk2_div2_en.hw, - [CLKID_VCLK2_DIV2] =3D &gxbb_vclk2_div2.hw, - [CLKID_VCLK2_DIV4_EN] =3D &gxbb_vclk2_div4_en.hw, - [CLKID_VCLK2_DIV4] =3D &gxbb_vclk2_div4.hw, - [CLKID_VCLK2_DIV6_EN] =3D &gxbb_vclk2_div6_en.hw, - [CLKID_VCLK2_DIV6] =3D &gxbb_vclk2_div6.hw, - [CLKID_VCLK2_DIV12_EN] =3D &gxbb_vclk2_div12_en.hw, - [CLKID_VCLK2_DIV12] =3D &gxbb_vclk2_div12.hw, - [CLKID_CTS_ENCI_SEL] =3D &gxbb_cts_enci_sel.hw, - [CLKID_CTS_ENCP_SEL] =3D &gxbb_cts_encp_sel.hw, - [CLKID_CTS_VDAC_SEL] =3D &gxbb_cts_vdac_sel.hw, - [CLKID_HDMI_TX_SEL] =3D &gxbb_hdmi_tx_sel.hw, - [CLKID_CTS_ENCI] =3D &gxbb_cts_enci.hw, - [CLKID_CTS_ENCP] =3D &gxbb_cts_encp.hw, - [CLKID_CTS_VDAC] =3D &gxbb_cts_vdac.hw, - [CLKID_HDMI_TX] =3D &gxbb_hdmi_tx.hw, - [CLKID_HDMI_SEL] =3D &gxbb_hdmi_sel.hw, - [CLKID_HDMI_DIV] =3D &gxbb_hdmi_div.hw, - [CLKID_HDMI] =3D &gxbb_hdmi.hw, - [CLKID_ACODEC] =3D &gxl_acodec.hw, - [NR_CLKS] =3D NULL, - }, - .num =3D NR_CLKS, +static struct clk_hw *gxbb_hw_clks[] =3D { + [CLKID_SYS_PLL] =3D &gxbb_sys_pll.hw, + [CLKID_HDMI_PLL] =3D &gxbb_hdmi_pll.hw, + [CLKID_FIXED_PLL] =3D &gxbb_fixed_pll.hw, + [CLKID_FCLK_DIV2] =3D &gxbb_fclk_div2.hw, + [CLKID_FCLK_DIV3] =3D &gxbb_fclk_div3.hw, + [CLKID_FCLK_DIV4] =3D &gxbb_fclk_div4.hw, + [CLKID_FCLK_DIV5] =3D &gxbb_fclk_div5.hw, + [CLKID_FCLK_DIV7] =3D &gxbb_fclk_div7.hw, + [CLKID_GP0_PLL] =3D &gxbb_gp0_pll.hw, + [CLKID_MPEG_SEL] =3D &gxbb_mpeg_clk_sel.hw, + [CLKID_MPEG_DIV] =3D &gxbb_mpeg_clk_div.hw, + [CLKID_CLK81] =3D &gxbb_clk81.hw, + [CLKID_MPLL0] =3D &gxbb_mpll0.hw, + [CLKID_MPLL1] =3D &gxbb_mpll1.hw, + [CLKID_MPLL2] =3D &gxbb_mpll2.hw, + [CLKID_DDR] =3D &gxbb_ddr.hw, + [CLKID_DOS] =3D &gxbb_dos.hw, + [CLKID_ISA] =3D &gxbb_isa.hw, + [CLKID_PL301] =3D &gxbb_pl301.hw, + [CLKID_PERIPHS] =3D &gxbb_periphs.hw, + [CLKID_SPICC] =3D &gxbb_spicc.hw, + [CLKID_I2C] =3D &gxbb_i2c.hw, + [CLKID_SAR_ADC] =3D &gxbb_sar_adc.hw, + [CLKID_SMART_CARD] =3D &gxbb_smart_card.hw, + [CLKID_RNG0] =3D &gxbb_rng0.hw, + [CLKID_UART0] =3D &gxbb_uart0.hw, + [CLKID_SDHC] =3D &gxbb_sdhc.hw, + [CLKID_STREAM] =3D &gxbb_stream.hw, + [CLKID_ASYNC_FIFO] =3D &gxbb_async_fifo.hw, + [CLKID_SDIO] =3D &gxbb_sdio.hw, + [CLKID_ABUF] =3D &gxbb_abuf.hw, + [CLKID_HIU_IFACE] =3D &gxbb_hiu_iface.hw, + [CLKID_ASSIST_MISC] =3D &gxbb_assist_misc.hw, + [CLKID_SPI] =3D &gxbb_spi.hw, + [CLKID_I2S_SPDIF] =3D &gxbb_i2s_spdif.hw, + [CLKID_ETH] =3D &gxbb_eth.hw, + [CLKID_DEMUX] =3D &gxbb_demux.hw, + [CLKID_AIU_GLUE] =3D &gxbb_aiu_glue.hw, + [CLKID_IEC958] =3D &gxbb_iec958.hw, + [CLKID_I2S_OUT] =3D &gxbb_i2s_out.hw, + [CLKID_AMCLK] =3D &gxbb_amclk.hw, + [CLKID_AIFIFO2] =3D &gxbb_aififo2.hw, + [CLKID_MIXER] =3D &gxbb_mixer.hw, + [CLKID_MIXER_IFACE] =3D &gxbb_mixer_iface.hw, + [CLKID_ADC] =3D &gxbb_adc.hw, + [CLKID_BLKMV] =3D &gxbb_blkmv.hw, + [CLKID_AIU] =3D &gxbb_aiu.hw, + [CLKID_UART1] =3D &gxbb_uart1.hw, + [CLKID_G2D] =3D &gxbb_g2d.hw, + [CLKID_USB0] =3D &gxbb_usb0.hw, + [CLKID_USB1] =3D &gxbb_usb1.hw, + [CLKID_RESET] =3D &gxbb_reset.hw, + [CLKID_NAND] =3D &gxbb_nand.hw, + [CLKID_DOS_PARSER] =3D &gxbb_dos_parser.hw, + [CLKID_USB] =3D &gxbb_usb.hw, + [CLKID_VDIN1] =3D &gxbb_vdin1.hw, + [CLKID_AHB_ARB0] =3D &gxbb_ahb_arb0.hw, + [CLKID_EFUSE] =3D &gxbb_efuse.hw, + [CLKID_BOOT_ROM] =3D &gxbb_boot_rom.hw, + [CLKID_AHB_DATA_BUS] =3D &gxbb_ahb_data_bus.hw, + [CLKID_AHB_CTRL_BUS] =3D &gxbb_ahb_ctrl_bus.hw, + [CLKID_HDMI_INTR_SYNC] =3D &gxbb_hdmi_intr_sync.hw, + [CLKID_HDMI_PCLK] =3D &gxbb_hdmi_pclk.hw, + [CLKID_USB1_DDR_BRIDGE] =3D &gxbb_usb1_ddr_bridge.hw, + [CLKID_USB0_DDR_BRIDGE] =3D &gxbb_usb0_ddr_bridge.hw, + [CLKID_MMC_PCLK] =3D &gxbb_mmc_pclk.hw, + [CLKID_DVIN] =3D &gxbb_dvin.hw, + [CLKID_UART2] =3D &gxbb_uart2.hw, + [CLKID_SANA] =3D &gxbb_sana.hw, + [CLKID_VPU_INTR] =3D &gxbb_vpu_intr.hw, + [CLKID_SEC_AHB_AHB3_BRIDGE] =3D &gxbb_sec_ahb_ahb3_bridge.hw, + [CLKID_CLK81_A53] =3D &gxbb_clk81_a53.hw, + [CLKID_VCLK2_VENCI0] =3D &gxbb_vclk2_venci0.hw, + [CLKID_VCLK2_VENCI1] =3D &gxbb_vclk2_venci1.hw, + [CLKID_VCLK2_VENCP0] =3D &gxbb_vclk2_vencp0.hw, + [CLKID_VCLK2_VENCP1] =3D &gxbb_vclk2_vencp1.hw, + [CLKID_GCLK_VENCI_INT0] =3D &gxbb_gclk_venci_int0.hw, + [CLKID_GCLK_VENCI_INT] =3D &gxbb_gclk_vencp_int.hw, + [CLKID_DAC_CLK] =3D &gxbb_dac_clk.hw, + [CLKID_AOCLK_GATE] =3D &gxbb_aoclk_gate.hw, + [CLKID_IEC958_GATE] =3D &gxbb_iec958_gate.hw, + [CLKID_ENC480P] =3D &gxbb_enc480p.hw, + [CLKID_RNG1] =3D &gxbb_rng1.hw, + [CLKID_GCLK_VENCI_INT1] =3D &gxbb_gclk_venci_int1.hw, + [CLKID_VCLK2_VENCLMCC] =3D &gxbb_vclk2_venclmcc.hw, + [CLKID_VCLK2_VENCL] =3D &gxbb_vclk2_vencl.hw, + [CLKID_VCLK_OTHER] =3D &gxbb_vclk_other.hw, + [CLKID_EDP] =3D &gxbb_edp.hw, + [CLKID_AO_MEDIA_CPU] =3D &gxbb_ao_media_cpu.hw, + [CLKID_AO_AHB_SRAM] =3D &gxbb_ao_ahb_sram.hw, + [CLKID_AO_AHB_BUS] =3D &gxbb_ao_ahb_bus.hw, + [CLKID_AO_IFACE] =3D &gxbb_ao_iface.hw, + [CLKID_AO_I2C] =3D &gxbb_ao_i2c.hw, + [CLKID_SD_EMMC_A] =3D &gxbb_emmc_a.hw, + [CLKID_SD_EMMC_B] =3D &gxbb_emmc_b.hw, + [CLKID_SD_EMMC_C] =3D &gxbb_emmc_c.hw, + [CLKID_SAR_ADC_CLK] =3D &gxbb_sar_adc_clk.hw, + [CLKID_SAR_ADC_SEL] =3D &gxbb_sar_adc_clk_sel.hw, + [CLKID_SAR_ADC_DIV] =3D &gxbb_sar_adc_clk_div.hw, + [CLKID_MALI_0_SEL] =3D &gxbb_mali_0_sel.hw, + [CLKID_MALI_0_DIV] =3D &gxbb_mali_0_div.hw, + [CLKID_MALI_0] =3D &gxbb_mali_0.hw, + [CLKID_MALI_1_SEL] =3D &gxbb_mali_1_sel.hw, + [CLKID_MALI_1_DIV] =3D &gxbb_mali_1_div.hw, + [CLKID_MALI_1] =3D &gxbb_mali_1.hw, + [CLKID_MALI] =3D &gxbb_mali.hw, + [CLKID_CTS_AMCLK] =3D &gxbb_cts_amclk.hw, + [CLKID_CTS_AMCLK_SEL] =3D &gxbb_cts_amclk_sel.hw, + [CLKID_CTS_AMCLK_DIV] =3D &gxbb_cts_amclk_div.hw, + [CLKID_CTS_MCLK_I958] =3D &gxbb_cts_mclk_i958.hw, + [CLKID_CTS_MCLK_I958_SEL] =3D &gxbb_cts_mclk_i958_sel.hw, + [CLKID_CTS_MCLK_I958_DIV] =3D &gxbb_cts_mclk_i958_div.hw, + [CLKID_CTS_I958] =3D &gxbb_cts_i958.hw, + [CLKID_32K_CLK] =3D &gxbb_32k_clk.hw, + [CLKID_32K_CLK_SEL] =3D &gxbb_32k_clk_sel.hw, + [CLKID_32K_CLK_DIV] =3D &gxbb_32k_clk_div.hw, + [CLKID_SD_EMMC_A_CLK0_SEL] =3D &gxbb_sd_emmc_a_clk0_sel.hw, + [CLKID_SD_EMMC_A_CLK0_DIV] =3D &gxbb_sd_emmc_a_clk0_div.hw, + [CLKID_SD_EMMC_A_CLK0] =3D &gxbb_sd_emmc_a_clk0.hw, + [CLKID_SD_EMMC_B_CLK0_SEL] =3D &gxbb_sd_emmc_b_clk0_sel.hw, + [CLKID_SD_EMMC_B_CLK0_DIV] =3D &gxbb_sd_emmc_b_clk0_div.hw, + [CLKID_SD_EMMC_B_CLK0] =3D &gxbb_sd_emmc_b_clk0.hw, + [CLKID_SD_EMMC_C_CLK0_SEL] =3D &gxbb_sd_emmc_c_clk0_sel.hw, + [CLKID_SD_EMMC_C_CLK0_DIV] =3D &gxbb_sd_emmc_c_clk0_div.hw, + [CLKID_SD_EMMC_C_CLK0] =3D &gxbb_sd_emmc_c_clk0.hw, + [CLKID_VPU_0_SEL] =3D &gxbb_vpu_0_sel.hw, + [CLKID_VPU_0_DIV] =3D &gxbb_vpu_0_div.hw, + [CLKID_VPU_0] =3D &gxbb_vpu_0.hw, + [CLKID_VPU_1_SEL] =3D &gxbb_vpu_1_sel.hw, + [CLKID_VPU_1_DIV] =3D &gxbb_vpu_1_div.hw, + [CLKID_VPU_1] =3D &gxbb_vpu_1.hw, + [CLKID_VPU] =3D &gxbb_vpu.hw, + [CLKID_VAPB_0_SEL] =3D &gxbb_vapb_0_sel.hw, + [CLKID_VAPB_0_DIV] =3D &gxbb_vapb_0_div.hw, + [CLKID_VAPB_0] =3D &gxbb_vapb_0.hw, + [CLKID_VAPB_1_SEL] =3D &gxbb_vapb_1_sel.hw, + [CLKID_VAPB_1_DIV] =3D &gxbb_vapb_1_div.hw, + [CLKID_VAPB_1] =3D &gxbb_vapb_1.hw, + [CLKID_VAPB_SEL] =3D &gxbb_vapb_sel.hw, + [CLKID_VAPB] =3D &gxbb_vapb.hw, + [CLKID_HDMI_PLL_PRE_MULT] =3D &gxbb_hdmi_pll_pre_mult.hw, + [CLKID_MPLL0_DIV] =3D &gxbb_mpll0_div.hw, + [CLKID_MPLL1_DIV] =3D &gxbb_mpll1_div.hw, + [CLKID_MPLL2_DIV] =3D &gxbb_mpll2_div.hw, + [CLKID_MPLL_PREDIV] =3D &gxbb_mpll_prediv.hw, + [CLKID_FCLK_DIV2_DIV] =3D &gxbb_fclk_div2_div.hw, + [CLKID_FCLK_DIV3_DIV] =3D &gxbb_fclk_div3_div.hw, + [CLKID_FCLK_DIV4_DIV] =3D &gxbb_fclk_div4_div.hw, + [CLKID_FCLK_DIV5_DIV] =3D &gxbb_fclk_div5_div.hw, + [CLKID_FCLK_DIV7_DIV] =3D &gxbb_fclk_div7_div.hw, + [CLKID_VDEC_1_SEL] =3D &gxbb_vdec_1_sel.hw, + [CLKID_VDEC_1_DIV] =3D &gxbb_vdec_1_div.hw, + [CLKID_VDEC_1] =3D &gxbb_vdec_1.hw, + [CLKID_VDEC_HEVC_SEL] =3D &gxbb_vdec_hevc_sel.hw, + [CLKID_VDEC_HEVC_DIV] =3D &gxbb_vdec_hevc_div.hw, + [CLKID_VDEC_HEVC] =3D &gxbb_vdec_hevc.hw, + [CLKID_GEN_CLK_SEL] =3D &gxbb_gen_clk_sel.hw, + [CLKID_GEN_CLK_DIV] =3D &gxbb_gen_clk_div.hw, + [CLKID_GEN_CLK] =3D &gxbb_gen_clk.hw, + [CLKID_FIXED_PLL_DCO] =3D &gxbb_fixed_pll_dco.hw, + [CLKID_HDMI_PLL_DCO] =3D &gxbb_hdmi_pll_dco.hw, + [CLKID_HDMI_PLL_OD] =3D &gxbb_hdmi_pll_od.hw, + [CLKID_HDMI_PLL_OD2] =3D &gxbb_hdmi_pll_od2.hw, + [CLKID_SYS_PLL_DCO] =3D &gxbb_sys_pll_dco.hw, + [CLKID_GP0_PLL_DCO] =3D &gxbb_gp0_pll_dco.hw, + [CLKID_VID_PLL_DIV] =3D &gxbb_vid_pll_div.hw, + [CLKID_VID_PLL_SEL] =3D &gxbb_vid_pll_sel.hw, + [CLKID_VID_PLL] =3D &gxbb_vid_pll.hw, + [CLKID_VCLK_SEL] =3D &gxbb_vclk_sel.hw, + [CLKID_VCLK2_SEL] =3D &gxbb_vclk2_sel.hw, + [CLKID_VCLK_INPUT] =3D &gxbb_vclk_input.hw, + [CLKID_VCLK2_INPUT] =3D &gxbb_vclk2_input.hw, + [CLKID_VCLK_DIV] =3D &gxbb_vclk_div.hw, + [CLKID_VCLK2_DIV] =3D &gxbb_vclk2_div.hw, + [CLKID_VCLK] =3D &gxbb_vclk.hw, + [CLKID_VCLK2] =3D &gxbb_vclk2.hw, + [CLKID_VCLK_DIV1] =3D &gxbb_vclk_div1.hw, + [CLKID_VCLK_DIV2_EN] =3D &gxbb_vclk_div2_en.hw, + [CLKID_VCLK_DIV2] =3D &gxbb_vclk_div2.hw, + [CLKID_VCLK_DIV4_EN] =3D &gxbb_vclk_div4_en.hw, + [CLKID_VCLK_DIV4] =3D &gxbb_vclk_div4.hw, + [CLKID_VCLK_DIV6_EN] =3D &gxbb_vclk_div6_en.hw, + [CLKID_VCLK_DIV6] =3D &gxbb_vclk_div6.hw, + [CLKID_VCLK_DIV12_EN] =3D &gxbb_vclk_div12_en.hw, + [CLKID_VCLK_DIV12] =3D &gxbb_vclk_div12.hw, + [CLKID_VCLK2_DIV1] =3D &gxbb_vclk2_div1.hw, + [CLKID_VCLK2_DIV2_EN] =3D &gxbb_vclk2_div2_en.hw, + [CLKID_VCLK2_DIV2] =3D &gxbb_vclk2_div2.hw, + [CLKID_VCLK2_DIV4_EN] =3D &gxbb_vclk2_div4_en.hw, + [CLKID_VCLK2_DIV4] =3D &gxbb_vclk2_div4.hw, + [CLKID_VCLK2_DIV6_EN] =3D &gxbb_vclk2_div6_en.hw, + [CLKID_VCLK2_DIV6] =3D &gxbb_vclk2_div6.hw, + [CLKID_VCLK2_DIV12_EN] =3D &gxbb_vclk2_div12_en.hw, + [CLKID_VCLK2_DIV12] =3D &gxbb_vclk2_div12.hw, + [CLKID_CTS_ENCI_SEL] =3D &gxbb_cts_enci_sel.hw, + [CLKID_CTS_ENCP_SEL] =3D &gxbb_cts_encp_sel.hw, + [CLKID_CTS_VDAC_SEL] =3D &gxbb_cts_vdac_sel.hw, + [CLKID_HDMI_TX_SEL] =3D &gxbb_hdmi_tx_sel.hw, + [CLKID_CTS_ENCI] =3D &gxbb_cts_enci.hw, + [CLKID_CTS_ENCP] =3D &gxbb_cts_encp.hw, + [CLKID_CTS_VDAC] =3D &gxbb_cts_vdac.hw, + [CLKID_HDMI_TX] =3D &gxbb_hdmi_tx.hw, + [CLKID_HDMI_SEL] =3D &gxbb_hdmi_sel.hw, + [CLKID_HDMI_DIV] =3D &gxbb_hdmi_div.hw, + [CLKID_HDMI] =3D &gxbb_hdmi.hw, +}; + +static struct clk_hw *gxl_hw_clks[] =3D { + [CLKID_SYS_PLL] =3D &gxbb_sys_pll.hw, + [CLKID_HDMI_PLL] =3D &gxl_hdmi_pll.hw, + [CLKID_FIXED_PLL] =3D &gxbb_fixed_pll.hw, + [CLKID_FCLK_DIV2] =3D &gxbb_fclk_div2.hw, + [CLKID_FCLK_DIV3] =3D &gxbb_fclk_div3.hw, + [CLKID_FCLK_DIV4] =3D &gxbb_fclk_div4.hw, + [CLKID_FCLK_DIV5] =3D &gxbb_fclk_div5.hw, + [CLKID_FCLK_DIV7] =3D &gxbb_fclk_div7.hw, + [CLKID_GP0_PLL] =3D &gxbb_gp0_pll.hw, + [CLKID_MPEG_SEL] =3D &gxbb_mpeg_clk_sel.hw, + [CLKID_MPEG_DIV] =3D &gxbb_mpeg_clk_div.hw, + [CLKID_CLK81] =3D &gxbb_clk81.hw, + [CLKID_MPLL0] =3D &gxbb_mpll0.hw, + [CLKID_MPLL1] =3D &gxbb_mpll1.hw, + [CLKID_MPLL2] =3D &gxbb_mpll2.hw, + [CLKID_DDR] =3D &gxbb_ddr.hw, + [CLKID_DOS] =3D &gxbb_dos.hw, + [CLKID_ISA] =3D &gxbb_isa.hw, + [CLKID_PL301] =3D &gxbb_pl301.hw, + [CLKID_PERIPHS] =3D &gxbb_periphs.hw, + [CLKID_SPICC] =3D &gxbb_spicc.hw, + [CLKID_I2C] =3D &gxbb_i2c.hw, + [CLKID_SAR_ADC] =3D &gxbb_sar_adc.hw, + [CLKID_SMART_CARD] =3D &gxbb_smart_card.hw, + [CLKID_RNG0] =3D &gxbb_rng0.hw, + [CLKID_UART0] =3D &gxbb_uart0.hw, + [CLKID_SDHC] =3D &gxbb_sdhc.hw, + [CLKID_STREAM] =3D &gxbb_stream.hw, + [CLKID_ASYNC_FIFO] =3D &gxbb_async_fifo.hw, + [CLKID_SDIO] =3D &gxbb_sdio.hw, + [CLKID_ABUF] =3D &gxbb_abuf.hw, + [CLKID_HIU_IFACE] =3D &gxbb_hiu_iface.hw, + [CLKID_ASSIST_MISC] =3D &gxbb_assist_misc.hw, + [CLKID_SPI] =3D &gxbb_spi.hw, + [CLKID_I2S_SPDIF] =3D &gxbb_i2s_spdif.hw, + [CLKID_ETH] =3D &gxbb_eth.hw, + [CLKID_DEMUX] =3D &gxbb_demux.hw, + [CLKID_AIU_GLUE] =3D &gxbb_aiu_glue.hw, + [CLKID_IEC958] =3D &gxbb_iec958.hw, + [CLKID_I2S_OUT] =3D &gxbb_i2s_out.hw, + [CLKID_AMCLK] =3D &gxbb_amclk.hw, + [CLKID_AIFIFO2] =3D &gxbb_aififo2.hw, + [CLKID_MIXER] =3D &gxbb_mixer.hw, + [CLKID_MIXER_IFACE] =3D &gxbb_mixer_iface.hw, + [CLKID_ADC] =3D &gxbb_adc.hw, + [CLKID_BLKMV] =3D &gxbb_blkmv.hw, + [CLKID_AIU] =3D &gxbb_aiu.hw, + [CLKID_UART1] =3D &gxbb_uart1.hw, + [CLKID_G2D] =3D &gxbb_g2d.hw, + [CLKID_USB0] =3D &gxbb_usb0.hw, + [CLKID_USB1] =3D &gxbb_usb1.hw, + [CLKID_RESET] =3D &gxbb_reset.hw, + [CLKID_NAND] =3D &gxbb_nand.hw, + [CLKID_DOS_PARSER] =3D &gxbb_dos_parser.hw, + [CLKID_USB] =3D &gxbb_usb.hw, + [CLKID_VDIN1] =3D &gxbb_vdin1.hw, + [CLKID_AHB_ARB0] =3D &gxbb_ahb_arb0.hw, + [CLKID_EFUSE] =3D &gxbb_efuse.hw, + [CLKID_BOOT_ROM] =3D &gxbb_boot_rom.hw, + [CLKID_AHB_DATA_BUS] =3D &gxbb_ahb_data_bus.hw, + [CLKID_AHB_CTRL_BUS] =3D &gxbb_ahb_ctrl_bus.hw, + [CLKID_HDMI_INTR_SYNC] =3D &gxbb_hdmi_intr_sync.hw, + [CLKID_HDMI_PCLK] =3D &gxbb_hdmi_pclk.hw, + [CLKID_USB1_DDR_BRIDGE] =3D &gxbb_usb1_ddr_bridge.hw, + [CLKID_USB0_DDR_BRIDGE] =3D &gxbb_usb0_ddr_bridge.hw, + [CLKID_MMC_PCLK] =3D &gxbb_mmc_pclk.hw, + [CLKID_DVIN] =3D &gxbb_dvin.hw, + [CLKID_UART2] =3D &gxbb_uart2.hw, + [CLKID_SANA] =3D &gxbb_sana.hw, + [CLKID_VPU_INTR] =3D &gxbb_vpu_intr.hw, + [CLKID_SEC_AHB_AHB3_BRIDGE] =3D &gxbb_sec_ahb_ahb3_bridge.hw, + [CLKID_CLK81_A53] =3D &gxbb_clk81_a53.hw, + [CLKID_VCLK2_VENCI0] =3D &gxbb_vclk2_venci0.hw, + [CLKID_VCLK2_VENCI1] =3D &gxbb_vclk2_venci1.hw, + [CLKID_VCLK2_VENCP0] =3D &gxbb_vclk2_vencp0.hw, + [CLKID_VCLK2_VENCP1] =3D &gxbb_vclk2_vencp1.hw, + [CLKID_GCLK_VENCI_INT0] =3D &gxbb_gclk_venci_int0.hw, + [CLKID_GCLK_VENCI_INT] =3D &gxbb_gclk_vencp_int.hw, + [CLKID_DAC_CLK] =3D &gxbb_dac_clk.hw, + [CLKID_AOCLK_GATE] =3D &gxbb_aoclk_gate.hw, + [CLKID_IEC958_GATE] =3D &gxbb_iec958_gate.hw, + [CLKID_ENC480P] =3D &gxbb_enc480p.hw, + [CLKID_RNG1] =3D &gxbb_rng1.hw, + [CLKID_GCLK_VENCI_INT1] =3D &gxbb_gclk_venci_int1.hw, + [CLKID_VCLK2_VENCLMCC] =3D &gxbb_vclk2_venclmcc.hw, + [CLKID_VCLK2_VENCL] =3D &gxbb_vclk2_vencl.hw, + [CLKID_VCLK_OTHER] =3D &gxbb_vclk_other.hw, + [CLKID_EDP] =3D &gxbb_edp.hw, + [CLKID_AO_MEDIA_CPU] =3D &gxbb_ao_media_cpu.hw, + [CLKID_AO_AHB_SRAM] =3D &gxbb_ao_ahb_sram.hw, + [CLKID_AO_AHB_BUS] =3D &gxbb_ao_ahb_bus.hw, + [CLKID_AO_IFACE] =3D &gxbb_ao_iface.hw, + [CLKID_AO_I2C] =3D &gxbb_ao_i2c.hw, + [CLKID_SD_EMMC_A] =3D &gxbb_emmc_a.hw, + [CLKID_SD_EMMC_B] =3D &gxbb_emmc_b.hw, + [CLKID_SD_EMMC_C] =3D &gxbb_emmc_c.hw, + [CLKID_SAR_ADC_CLK] =3D &gxbb_sar_adc_clk.hw, + [CLKID_SAR_ADC_SEL] =3D &gxbb_sar_adc_clk_sel.hw, + [CLKID_SAR_ADC_DIV] =3D &gxbb_sar_adc_clk_div.hw, + [CLKID_MALI_0_SEL] =3D &gxbb_mali_0_sel.hw, + [CLKID_MALI_0_DIV] =3D &gxbb_mali_0_div.hw, + [CLKID_MALI_0] =3D &gxbb_mali_0.hw, + [CLKID_MALI_1_SEL] =3D &gxbb_mali_1_sel.hw, + [CLKID_MALI_1_DIV] =3D &gxbb_mali_1_div.hw, + [CLKID_MALI_1] =3D &gxbb_mali_1.hw, + [CLKID_MALI] =3D &gxbb_mali.hw, + [CLKID_CTS_AMCLK] =3D &gxbb_cts_amclk.hw, + [CLKID_CTS_AMCLK_SEL] =3D &gxbb_cts_amclk_sel.hw, + [CLKID_CTS_AMCLK_DIV] =3D &gxbb_cts_amclk_div.hw, + [CLKID_CTS_MCLK_I958] =3D &gxbb_cts_mclk_i958.hw, + [CLKID_CTS_MCLK_I958_SEL] =3D &gxbb_cts_mclk_i958_sel.hw, + [CLKID_CTS_MCLK_I958_DIV] =3D &gxbb_cts_mclk_i958_div.hw, + [CLKID_CTS_I958] =3D &gxbb_cts_i958.hw, + [CLKID_32K_CLK] =3D &gxbb_32k_clk.hw, + [CLKID_32K_CLK_SEL] =3D &gxbb_32k_clk_sel.hw, + [CLKID_32K_CLK_DIV] =3D &gxbb_32k_clk_div.hw, + [CLKID_SD_EMMC_A_CLK0_SEL] =3D &gxbb_sd_emmc_a_clk0_sel.hw, + [CLKID_SD_EMMC_A_CLK0_DIV] =3D &gxbb_sd_emmc_a_clk0_div.hw, + [CLKID_SD_EMMC_A_CLK0] =3D &gxbb_sd_emmc_a_clk0.hw, + [CLKID_SD_EMMC_B_CLK0_SEL] =3D &gxbb_sd_emmc_b_clk0_sel.hw, + [CLKID_SD_EMMC_B_CLK0_DIV] =3D &gxbb_sd_emmc_b_clk0_div.hw, + [CLKID_SD_EMMC_B_CLK0] =3D &gxbb_sd_emmc_b_clk0.hw, + [CLKID_SD_EMMC_C_CLK0_SEL] =3D &gxbb_sd_emmc_c_clk0_sel.hw, + [CLKID_SD_EMMC_C_CLK0_DIV] =3D &gxbb_sd_emmc_c_clk0_div.hw, + [CLKID_SD_EMMC_C_CLK0] =3D &gxbb_sd_emmc_c_clk0.hw, + [CLKID_VPU_0_SEL] =3D &gxbb_vpu_0_sel.hw, + [CLKID_VPU_0_DIV] =3D &gxbb_vpu_0_div.hw, + [CLKID_VPU_0] =3D &gxbb_vpu_0.hw, + [CLKID_VPU_1_SEL] =3D &gxbb_vpu_1_sel.hw, + [CLKID_VPU_1_DIV] =3D &gxbb_vpu_1_div.hw, + [CLKID_VPU_1] =3D &gxbb_vpu_1.hw, + [CLKID_VPU] =3D &gxbb_vpu.hw, + [CLKID_VAPB_0_SEL] =3D &gxbb_vapb_0_sel.hw, + [CLKID_VAPB_0_DIV] =3D &gxbb_vapb_0_div.hw, + [CLKID_VAPB_0] =3D &gxbb_vapb_0.hw, + [CLKID_VAPB_1_SEL] =3D &gxbb_vapb_1_sel.hw, + [CLKID_VAPB_1_DIV] =3D &gxbb_vapb_1_div.hw, + [CLKID_VAPB_1] =3D &gxbb_vapb_1.hw, + [CLKID_VAPB_SEL] =3D &gxbb_vapb_sel.hw, + [CLKID_VAPB] =3D &gxbb_vapb.hw, + [CLKID_MPLL0_DIV] =3D &gxl_mpll0_div.hw, + [CLKID_MPLL1_DIV] =3D &gxbb_mpll1_div.hw, + [CLKID_MPLL2_DIV] =3D &gxbb_mpll2_div.hw, + [CLKID_MPLL_PREDIV] =3D &gxbb_mpll_prediv.hw, + [CLKID_FCLK_DIV2_DIV] =3D &gxbb_fclk_div2_div.hw, + [CLKID_FCLK_DIV3_DIV] =3D &gxbb_fclk_div3_div.hw, + [CLKID_FCLK_DIV4_DIV] =3D &gxbb_fclk_div4_div.hw, + [CLKID_FCLK_DIV5_DIV] =3D &gxbb_fclk_div5_div.hw, + [CLKID_FCLK_DIV7_DIV] =3D &gxbb_fclk_div7_div.hw, + [CLKID_VDEC_1_SEL] =3D &gxbb_vdec_1_sel.hw, + [CLKID_VDEC_1_DIV] =3D &gxbb_vdec_1_div.hw, + [CLKID_VDEC_1] =3D &gxbb_vdec_1.hw, + [CLKID_VDEC_HEVC_SEL] =3D &gxbb_vdec_hevc_sel.hw, + [CLKID_VDEC_HEVC_DIV] =3D &gxbb_vdec_hevc_div.hw, + [CLKID_VDEC_HEVC] =3D &gxbb_vdec_hevc.hw, + [CLKID_GEN_CLK_SEL] =3D &gxbb_gen_clk_sel.hw, + [CLKID_GEN_CLK_DIV] =3D &gxbb_gen_clk_div.hw, + [CLKID_GEN_CLK] =3D &gxbb_gen_clk.hw, + [CLKID_FIXED_PLL_DCO] =3D &gxbb_fixed_pll_dco.hw, + [CLKID_HDMI_PLL_DCO] =3D &gxl_hdmi_pll_dco.hw, + [CLKID_HDMI_PLL_OD] =3D &gxl_hdmi_pll_od.hw, + [CLKID_HDMI_PLL_OD2] =3D &gxl_hdmi_pll_od2.hw, + [CLKID_SYS_PLL_DCO] =3D &gxbb_sys_pll_dco.hw, + [CLKID_GP0_PLL_DCO] =3D &gxl_gp0_pll_dco.hw, + [CLKID_VID_PLL_DIV] =3D &gxbb_vid_pll_div.hw, + [CLKID_VID_PLL_SEL] =3D &gxbb_vid_pll_sel.hw, + [CLKID_VID_PLL] =3D &gxbb_vid_pll.hw, + [CLKID_VCLK_SEL] =3D &gxbb_vclk_sel.hw, + [CLKID_VCLK2_SEL] =3D &gxbb_vclk2_sel.hw, + [CLKID_VCLK_INPUT] =3D &gxbb_vclk_input.hw, + [CLKID_VCLK2_INPUT] =3D &gxbb_vclk2_input.hw, + [CLKID_VCLK_DIV] =3D &gxbb_vclk_div.hw, + [CLKID_VCLK2_DIV] =3D &gxbb_vclk2_div.hw, + [CLKID_VCLK] =3D &gxbb_vclk.hw, + [CLKID_VCLK2] =3D &gxbb_vclk2.hw, + [CLKID_VCLK_DIV1] =3D &gxbb_vclk_div1.hw, + [CLKID_VCLK_DIV2_EN] =3D &gxbb_vclk_div2_en.hw, + [CLKID_VCLK_DIV2] =3D &gxbb_vclk_div2.hw, + [CLKID_VCLK_DIV4_EN] =3D &gxbb_vclk_div4_en.hw, + [CLKID_VCLK_DIV4] =3D &gxbb_vclk_div4.hw, + [CLKID_VCLK_DIV6_EN] =3D &gxbb_vclk_div6_en.hw, + [CLKID_VCLK_DIV6] =3D &gxbb_vclk_div6.hw, + [CLKID_VCLK_DIV12_EN] =3D &gxbb_vclk_div12_en.hw, + [CLKID_VCLK_DIV12] =3D &gxbb_vclk_div12.hw, + [CLKID_VCLK2_DIV1] =3D &gxbb_vclk2_div1.hw, + [CLKID_VCLK2_DIV2_EN] =3D &gxbb_vclk2_div2_en.hw, + [CLKID_VCLK2_DIV2] =3D &gxbb_vclk2_div2.hw, + [CLKID_VCLK2_DIV4_EN] =3D &gxbb_vclk2_div4_en.hw, + [CLKID_VCLK2_DIV4] =3D &gxbb_vclk2_div4.hw, + [CLKID_VCLK2_DIV6_EN] =3D &gxbb_vclk2_div6_en.hw, + [CLKID_VCLK2_DIV6] =3D &gxbb_vclk2_div6.hw, + [CLKID_VCLK2_DIV12_EN] =3D &gxbb_vclk2_div12_en.hw, + [CLKID_VCLK2_DIV12] =3D &gxbb_vclk2_div12.hw, + [CLKID_CTS_ENCI_SEL] =3D &gxbb_cts_enci_sel.hw, + [CLKID_CTS_ENCP_SEL] =3D &gxbb_cts_encp_sel.hw, + [CLKID_CTS_VDAC_SEL] =3D &gxbb_cts_vdac_sel.hw, + [CLKID_HDMI_TX_SEL] =3D &gxbb_hdmi_tx_sel.hw, + [CLKID_CTS_ENCI] =3D &gxbb_cts_enci.hw, + [CLKID_CTS_ENCP] =3D &gxbb_cts_encp.hw, + [CLKID_CTS_VDAC] =3D &gxbb_cts_vdac.hw, + [CLKID_HDMI_TX] =3D &gxbb_hdmi_tx.hw, + [CLKID_HDMI_SEL] =3D &gxbb_hdmi_sel.hw, + [CLKID_HDMI_DIV] =3D &gxbb_hdmi_div.hw, + [CLKID_HDMI] =3D &gxbb_hdmi.hw, + [CLKID_ACODEC] =3D &gxl_acodec.hw, }; =20 static struct clk_regmap *const gxbb_clk_regmaps[] =3D { @@ -3544,13 +3536,19 @@ static struct clk_regmap *const gxl_clk_regmaps[] = =3D { static const struct meson_eeclkc_data gxbb_clkc_data =3D { .regmap_clks =3D gxbb_clk_regmaps, .regmap_clk_num =3D ARRAY_SIZE(gxbb_clk_regmaps), - .hw_onecell_data =3D &gxbb_hw_onecell_data, + .hw_clks =3D { + .hws =3D gxbb_hw_clks, + .num =3D ARRAY_SIZE(gxbb_hw_clks), + }, }; =20 static const struct meson_eeclkc_data gxl_clkc_data =3D { .regmap_clks =3D gxl_clk_regmaps, .regmap_clk_num =3D ARRAY_SIZE(gxl_clk_regmaps), - .hw_onecell_data =3D &gxl_hw_onecell_data, + .hw_clks =3D { + .hws =3D gxl_hw_clks, + .num =3D ARRAY_SIZE(gxl_hw_clks), + }, }; =20 static const struct of_device_id clkc_match_table[] =3D { diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h index 1ee8cb7e2f5a..6751cda25986 100644 --- a/drivers/clk/meson/gxbb.h +++ b/drivers/clk/meson/gxbb.h @@ -188,8 +188,6 @@ #define CLKID_HDMI_SEL 203 #define CLKID_HDMI_DIV 204 =20 -#define NR_CLKS 207 - /* include the CLKIDs that have been made part of the DT binding */ #include =20 diff --git a/drivers/clk/meson/meson-eeclk.c b/drivers/clk/meson/meson-eecl= k.c index 0e5e6b57eb20..3ce9f702e63d 100644 --- a/drivers/clk/meson/meson-eeclk.c +++ b/drivers/clk/meson/meson-eeclk.c @@ -43,20 +43,19 @@ int meson_eeclkc_probe(struct platform_device *pdev) for (i =3D 0; i < data->regmap_clk_num; i++) data->regmap_clks[i]->map =3D map; =20 - for (i =3D 0; i < data->hw_onecell_data->num; i++) { + for (i =3D 0; i < data->hw_clks.num; i++) { /* array might be sparse */ - if (!data->hw_onecell_data->hws[i]) + if (!data->hw_clks.hws[i]) continue; =20 - ret =3D devm_clk_hw_register(dev, data->hw_onecell_data->hws[i]); + ret =3D devm_clk_hw_register(dev, data->hw_clks.hws[i]); if (ret) { dev_err(dev, "Clock registration failed\n"); return ret; } } =20 - return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, - data->hw_onecell_data); + return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->= hw_clks); } EXPORT_SYMBOL_GPL(meson_eeclkc_probe); MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/meson/meson-eeclk.h b/drivers/clk/meson/meson-eecl= k.h index 77316207bde1..37a48b75c660 100644 --- a/drivers/clk/meson/meson-eeclk.h +++ b/drivers/clk/meson/meson-eeclk.h @@ -9,6 +9,7 @@ =20 #include #include "clk-regmap.h" +#include "meson-clkc-utils.h" =20 struct platform_device; =20 @@ -17,7 +18,7 @@ struct meson_eeclkc_data { unsigned int regmap_clk_num; const struct reg_sequence *init_regs; unsigned int init_count; - struct clk_hw_onecell_data *hw_onecell_data; + struct meson_clk_hw_data hw_clks; }; =20 int meson_eeclkc_probe(struct platform_device *pdev); --=20 2.34.1