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Wed, 07 Jun 2023 03:56:26 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id i10-20020a05600c290a00b003f60faa4612sm1761879wmd.22.2023.06.07.03.56.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Jun 2023 03:56:25 -0700 (PDT) From: Neil Armstrong Date: Wed, 07 Jun 2023 12:56:14 +0200 Subject: [PATCH 03/18] clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230607-topic-amlogic-upstream-clkid-public-migration-v1-3-9676afa6b22c@linaro.org> References: <20230607-topic-amlogic-upstream-clkid-public-migration-v1-0-9676afa6b22c@linaro.org> In-Reply-To: <20230607-topic-amlogic-upstream-clkid-public-migration-v1-0-9676afa6b22c@linaro.org> To: Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The way hw_onecell_data is declared: struct clk_hw_onecell_data { unsigned int num; struct clk_hw *hws[]; }; makes it impossible to have the clk_hw table declared outside while using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible array member. Completely move out of hw_onecell_data and add a custom devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw in order to finally get rid on the NR_CLKS define. Signed-off-by: Neil Armstrong --- drivers/clk/meson/a1-peripherals.c | 343 +++++++++++++++++++--------------= ---- drivers/clk/meson/a1-peripherals.h | 1 - drivers/clk/meson/a1-pll.c | 57 ++++-- drivers/clk/meson/a1-pll.h | 1 - 4 files changed, 219 insertions(+), 183 deletions(-) diff --git a/drivers/clk/meson/a1-peripherals.c b/drivers/clk/meson/a1-peri= pherals.c index b320134fefeb..094246cb5f6c 100644 --- a/drivers/clk/meson/a1-peripherals.c +++ b/drivers/clk/meson/a1-peripherals.c @@ -1866,165 +1866,161 @@ static MESON_GATE(rom, AXI_CLK_EN, 11); static MESON_GATE(prod_i2c, AXI_CLK_EN, 12); =20 /* Array of all clocks registered by this provider */ -static struct clk_hw_onecell_data a1_periphs_clks =3D { - .hws =3D { - [CLKID_XTAL_IN] =3D &xtal_in.hw, - [CLKID_FIXPLL_IN] =3D &fixpll_in.hw, - [CLKID_USB_PHY_IN] =3D &usb_phy_in.hw, - [CLKID_USB_CTRL_IN] =3D &usb_ctrl_in.hw, - [CLKID_HIFIPLL_IN] =3D &hifipll_in.hw, - [CLKID_SYSPLL_IN] =3D &syspll_in.hw, - [CLKID_DDS_IN] =3D &dds_in.hw, - [CLKID_SYS] =3D &sys.hw, - [CLKID_CLKTREE] =3D &clktree.hw, - [CLKID_RESET_CTRL] =3D &reset_ctrl.hw, - [CLKID_ANALOG_CTRL] =3D &analog_ctrl.hw, - [CLKID_PWR_CTRL] =3D &pwr_ctrl.hw, - [CLKID_PAD_CTRL] =3D &pad_ctrl.hw, - [CLKID_SYS_CTRL] =3D &sys_ctrl.hw, - [CLKID_TEMP_SENSOR] =3D &temp_sensor.hw, - [CLKID_AM2AXI_DIV] =3D &am2axi_dev.hw, - [CLKID_SPICC_B] =3D &spicc_b.hw, - [CLKID_SPICC_A] =3D &spicc_a.hw, - [CLKID_MSR] =3D &msr.hw, - [CLKID_AUDIO] =3D &audio.hw, - [CLKID_JTAG_CTRL] =3D &jtag_ctrl.hw, - [CLKID_SARADC_EN] =3D &saradc_en.hw, - [CLKID_PWM_EF] =3D &pwm_ef.hw, - [CLKID_PWM_CD] =3D &pwm_cd.hw, - [CLKID_PWM_AB] =3D &pwm_ab.hw, - [CLKID_CEC] =3D &cec.hw, - [CLKID_I2C_S] =3D &i2c_s.hw, - [CLKID_IR_CTRL] =3D &ir_ctrl.hw, - [CLKID_I2C_M_D] =3D &i2c_m_d.hw, - [CLKID_I2C_M_C] =3D &i2c_m_c.hw, - [CLKID_I2C_M_B] =3D &i2c_m_b.hw, - [CLKID_I2C_M_A] =3D &i2c_m_a.hw, - [CLKID_ACODEC] =3D &acodec.hw, - [CLKID_OTP] =3D &otp.hw, - [CLKID_SD_EMMC_A] =3D &sd_emmc_a.hw, - [CLKID_USB_PHY] =3D &usb_phy.hw, - [CLKID_USB_CTRL] =3D &usb_ctrl.hw, - [CLKID_SYS_DSPB] =3D &sys_dspb.hw, - [CLKID_SYS_DSPA] =3D &sys_dspa.hw, - [CLKID_DMA] =3D &dma.hw, - [CLKID_IRQ_CTRL] =3D &irq_ctrl.hw, - [CLKID_NIC] =3D &nic.hw, - [CLKID_GIC] =3D &gic.hw, - [CLKID_UART_C] =3D &uart_c.hw, - [CLKID_UART_B] =3D &uart_b.hw, - [CLKID_UART_A] =3D &uart_a.hw, - [CLKID_SYS_PSRAM] =3D &sys_psram.hw, - [CLKID_RSA] =3D &rsa.hw, - [CLKID_CORESIGHT] =3D &coresight.hw, - [CLKID_AM2AXI_VAD] =3D &am2axi_vad.hw, - [CLKID_AUDIO_VAD] =3D &audio_vad.hw, - [CLKID_AXI_DMC] =3D &axi_dmc.hw, - [CLKID_AXI_PSRAM] =3D &axi_psram.hw, - [CLKID_RAMB] =3D &ramb.hw, - [CLKID_RAMA] =3D &rama.hw, - [CLKID_AXI_SPIFC] =3D &axi_spifc.hw, - [CLKID_AXI_NIC] =3D &axi_nic.hw, - [CLKID_AXI_DMA] =3D &axi_dma.hw, - [CLKID_CPU_CTRL] =3D &cpu_ctrl.hw, - [CLKID_ROM] =3D &rom.hw, - [CLKID_PROC_I2C] =3D &prod_i2c.hw, - [CLKID_DSPA_SEL] =3D &dspa_sel.hw, - [CLKID_DSPB_SEL] =3D &dspb_sel.hw, - [CLKID_DSPA_EN] =3D &dspa_en.hw, - [CLKID_DSPA_EN_NIC] =3D &dspa_en_nic.hw, - [CLKID_DSPB_EN] =3D &dspb_en.hw, - [CLKID_DSPB_EN_NIC] =3D &dspb_en_nic.hw, - [CLKID_RTC] =3D &rtc.hw, - [CLKID_CECA_32K] =3D &ceca_32k_out.hw, - [CLKID_CECB_32K] =3D &cecb_32k_out.hw, - [CLKID_24M] =3D &clk_24m.hw, - [CLKID_12M] =3D &clk_12m.hw, - [CLKID_FCLK_DIV2_DIVN] =3D &fclk_div2_divn.hw, - [CLKID_GEN] =3D &gen.hw, - [CLKID_SARADC_SEL] =3D &saradc_sel.hw, - [CLKID_SARADC] =3D &saradc.hw, - [CLKID_PWM_A] =3D &pwm_a.hw, - [CLKID_PWM_B] =3D &pwm_b.hw, - [CLKID_PWM_C] =3D &pwm_c.hw, - [CLKID_PWM_D] =3D &pwm_d.hw, - [CLKID_PWM_E] =3D &pwm_e.hw, - [CLKID_PWM_F] =3D &pwm_f.hw, - [CLKID_SPICC] =3D &spicc.hw, - [CLKID_TS] =3D &ts.hw, - [CLKID_SPIFC] =3D &spifc.hw, - [CLKID_USB_BUS] =3D &usb_bus.hw, - [CLKID_SD_EMMC] =3D &sd_emmc.hw, - [CLKID_PSRAM] =3D &psram.hw, - [CLKID_DMC] =3D &dmc.hw, - [CLKID_SYS_A_SEL] =3D &sys_a_sel.hw, - [CLKID_SYS_A_DIV] =3D &sys_a_div.hw, - [CLKID_SYS_A] =3D &sys_a.hw, - [CLKID_SYS_B_SEL] =3D &sys_b_sel.hw, - [CLKID_SYS_B_DIV] =3D &sys_b_div.hw, - [CLKID_SYS_B] =3D &sys_b.hw, - [CLKID_DSPA_A_SEL] =3D &dspa_a_sel.hw, - [CLKID_DSPA_A_DIV] =3D &dspa_a_div.hw, - [CLKID_DSPA_A] =3D &dspa_a.hw, - [CLKID_DSPA_B_SEL] =3D &dspa_b_sel.hw, - [CLKID_DSPA_B_DIV] =3D &dspa_b_div.hw, - [CLKID_DSPA_B] =3D &dspa_b.hw, - [CLKID_DSPB_A_SEL] =3D &dspb_a_sel.hw, - [CLKID_DSPB_A_DIV] =3D &dspb_a_div.hw, - [CLKID_DSPB_A] =3D &dspb_a.hw, - [CLKID_DSPB_B_SEL] =3D &dspb_b_sel.hw, - [CLKID_DSPB_B_DIV] =3D &dspb_b_div.hw, - [CLKID_DSPB_B] =3D &dspb_b.hw, - [CLKID_RTC_32K_IN] =3D &rtc_32k_in.hw, - [CLKID_RTC_32K_DIV] =3D &rtc_32k_div.hw, - [CLKID_RTC_32K_XTAL] =3D &rtc_32k_xtal.hw, - [CLKID_RTC_32K_SEL] =3D &rtc_32k_sel.hw, - [CLKID_CECB_32K_IN] =3D &cecb_32k_in.hw, - [CLKID_CECB_32K_DIV] =3D &cecb_32k_div.hw, - [CLKID_CECB_32K_SEL_PRE] =3D &cecb_32k_sel_pre.hw, - [CLKID_CECB_32K_SEL] =3D &cecb_32k_sel.hw, - [CLKID_CECA_32K_IN] =3D &ceca_32k_in.hw, - [CLKID_CECA_32K_DIV] =3D &ceca_32k_div.hw, - [CLKID_CECA_32K_SEL_PRE] =3D &ceca_32k_sel_pre.hw, - [CLKID_CECA_32K_SEL] =3D &ceca_32k_sel.hw, - [CLKID_DIV2_PRE] =3D &fclk_div2_divn_pre.hw, - [CLKID_24M_DIV2] =3D &clk_24m_div2.hw, - [CLKID_GEN_SEL] =3D &gen_sel.hw, - [CLKID_GEN_DIV] =3D &gen_div.hw, - [CLKID_SARADC_DIV] =3D &saradc_div.hw, - [CLKID_PWM_A_SEL] =3D &pwm_a_sel.hw, - [CLKID_PWM_A_DIV] =3D &pwm_a_div.hw, - [CLKID_PWM_B_SEL] =3D &pwm_b_sel.hw, - [CLKID_PWM_B_DIV] =3D &pwm_b_div.hw, - [CLKID_PWM_C_SEL] =3D &pwm_c_sel.hw, - [CLKID_PWM_C_DIV] =3D &pwm_c_div.hw, - [CLKID_PWM_D_SEL] =3D &pwm_d_sel.hw, - [CLKID_PWM_D_DIV] =3D &pwm_d_div.hw, - [CLKID_PWM_E_SEL] =3D &pwm_e_sel.hw, - [CLKID_PWM_E_DIV] =3D &pwm_e_div.hw, - [CLKID_PWM_F_SEL] =3D &pwm_f_sel.hw, - [CLKID_PWM_F_DIV] =3D &pwm_f_div.hw, - [CLKID_SPICC_SEL] =3D &spicc_sel.hw, - [CLKID_SPICC_DIV] =3D &spicc_div.hw, - [CLKID_SPICC_SEL2] =3D &spicc_sel2.hw, - [CLKID_TS_DIV] =3D &ts_div.hw, - [CLKID_SPIFC_SEL] =3D &spifc_sel.hw, - [CLKID_SPIFC_DIV] =3D &spifc_div.hw, - [CLKID_SPIFC_SEL2] =3D &spifc_sel2.hw, - [CLKID_USB_BUS_SEL] =3D &usb_bus_sel.hw, - [CLKID_USB_BUS_DIV] =3D &usb_bus_div.hw, - [CLKID_SD_EMMC_SEL] =3D &sd_emmc_sel.hw, - [CLKID_SD_EMMC_DIV] =3D &sd_emmc_div.hw, - [CLKID_SD_EMMC_SEL2] =3D &sd_emmc_sel2.hw, - [CLKID_PSRAM_SEL] =3D &psram_sel.hw, - [CLKID_PSRAM_DIV] =3D &psram_div.hw, - [CLKID_PSRAM_SEL2] =3D &psram_sel2.hw, - [CLKID_DMC_SEL] =3D &dmc_sel.hw, - [CLKID_DMC_DIV] =3D &dmc_div.hw, - [CLKID_DMC_SEL2] =3D &dmc_sel2.hw, - [NR_CLKS] =3D NULL, - }, - .num =3D NR_CLKS, +static struct clk_hw *a1_periphs_hw_clks[] =3D { + [CLKID_XTAL_IN] =3D &xtal_in.hw, + [CLKID_FIXPLL_IN] =3D &fixpll_in.hw, + [CLKID_USB_PHY_IN] =3D &usb_phy_in.hw, + [CLKID_USB_CTRL_IN] =3D &usb_ctrl_in.hw, + [CLKID_HIFIPLL_IN] =3D &hifipll_in.hw, + [CLKID_SYSPLL_IN] =3D &syspll_in.hw, + [CLKID_DDS_IN] =3D &dds_in.hw, + [CLKID_SYS] =3D &sys.hw, + [CLKID_CLKTREE] =3D &clktree.hw, + [CLKID_RESET_CTRL] =3D &reset_ctrl.hw, + [CLKID_ANALOG_CTRL] =3D &analog_ctrl.hw, + [CLKID_PWR_CTRL] =3D &pwr_ctrl.hw, + [CLKID_PAD_CTRL] =3D &pad_ctrl.hw, + [CLKID_SYS_CTRL] =3D &sys_ctrl.hw, + [CLKID_TEMP_SENSOR] =3D &temp_sensor.hw, + [CLKID_AM2AXI_DIV] =3D &am2axi_dev.hw, + [CLKID_SPICC_B] =3D &spicc_b.hw, + [CLKID_SPICC_A] =3D &spicc_a.hw, + [CLKID_MSR] =3D &msr.hw, + [CLKID_AUDIO] =3D &audio.hw, + [CLKID_JTAG_CTRL] =3D &jtag_ctrl.hw, + [CLKID_SARADC_EN] =3D &saradc_en.hw, + [CLKID_PWM_EF] =3D &pwm_ef.hw, + [CLKID_PWM_CD] =3D &pwm_cd.hw, + [CLKID_PWM_AB] =3D &pwm_ab.hw, + [CLKID_CEC] =3D &cec.hw, + [CLKID_I2C_S] =3D &i2c_s.hw, + [CLKID_IR_CTRL] =3D &ir_ctrl.hw, + [CLKID_I2C_M_D] =3D &i2c_m_d.hw, + [CLKID_I2C_M_C] =3D &i2c_m_c.hw, + [CLKID_I2C_M_B] =3D &i2c_m_b.hw, + [CLKID_I2C_M_A] =3D &i2c_m_a.hw, + [CLKID_ACODEC] =3D &acodec.hw, + [CLKID_OTP] =3D &otp.hw, + [CLKID_SD_EMMC_A] =3D &sd_emmc_a.hw, + [CLKID_USB_PHY] =3D &usb_phy.hw, + [CLKID_USB_CTRL] =3D &usb_ctrl.hw, + [CLKID_SYS_DSPB] =3D &sys_dspb.hw, + [CLKID_SYS_DSPA] =3D &sys_dspa.hw, + [CLKID_DMA] =3D &dma.hw, + [CLKID_IRQ_CTRL] =3D &irq_ctrl.hw, + [CLKID_NIC] =3D &nic.hw, + [CLKID_GIC] =3D &gic.hw, + [CLKID_UART_C] =3D &uart_c.hw, + [CLKID_UART_B] =3D &uart_b.hw, + [CLKID_UART_A] =3D &uart_a.hw, + [CLKID_SYS_PSRAM] =3D &sys_psram.hw, + [CLKID_RSA] =3D &rsa.hw, + [CLKID_CORESIGHT] =3D &coresight.hw, + [CLKID_AM2AXI_VAD] =3D &am2axi_vad.hw, + [CLKID_AUDIO_VAD] =3D &audio_vad.hw, + [CLKID_AXI_DMC] =3D &axi_dmc.hw, + [CLKID_AXI_PSRAM] =3D &axi_psram.hw, + [CLKID_RAMB] =3D &ramb.hw, + [CLKID_RAMA] =3D &rama.hw, + [CLKID_AXI_SPIFC] =3D &axi_spifc.hw, + [CLKID_AXI_NIC] =3D &axi_nic.hw, + [CLKID_AXI_DMA] =3D &axi_dma.hw, + [CLKID_CPU_CTRL] =3D &cpu_ctrl.hw, + [CLKID_ROM] =3D &rom.hw, + [CLKID_PROC_I2C] =3D &prod_i2c.hw, + [CLKID_DSPA_SEL] =3D &dspa_sel.hw, + [CLKID_DSPB_SEL] =3D &dspb_sel.hw, + [CLKID_DSPA_EN] =3D &dspa_en.hw, + [CLKID_DSPA_EN_NIC] =3D &dspa_en_nic.hw, + [CLKID_DSPB_EN] =3D &dspb_en.hw, + [CLKID_DSPB_EN_NIC] =3D &dspb_en_nic.hw, + [CLKID_RTC] =3D &rtc.hw, + [CLKID_CECA_32K] =3D &ceca_32k_out.hw, + [CLKID_CECB_32K] =3D &cecb_32k_out.hw, + [CLKID_24M] =3D &clk_24m.hw, + [CLKID_12M] =3D &clk_12m.hw, + [CLKID_FCLK_DIV2_DIVN] =3D &fclk_div2_divn.hw, + [CLKID_GEN] =3D &gen.hw, + [CLKID_SARADC_SEL] =3D &saradc_sel.hw, + [CLKID_SARADC] =3D &saradc.hw, + [CLKID_PWM_A] =3D &pwm_a.hw, + [CLKID_PWM_B] =3D &pwm_b.hw, + [CLKID_PWM_C] =3D &pwm_c.hw, + [CLKID_PWM_D] =3D &pwm_d.hw, + [CLKID_PWM_E] =3D &pwm_e.hw, + [CLKID_PWM_F] =3D &pwm_f.hw, + [CLKID_SPICC] =3D &spicc.hw, + [CLKID_TS] =3D &ts.hw, + [CLKID_SPIFC] =3D &spifc.hw, + [CLKID_USB_BUS] =3D &usb_bus.hw, + [CLKID_SD_EMMC] =3D &sd_emmc.hw, + [CLKID_PSRAM] =3D &psram.hw, + [CLKID_DMC] =3D &dmc.hw, + [CLKID_SYS_A_SEL] =3D &sys_a_sel.hw, + [CLKID_SYS_A_DIV] =3D &sys_a_div.hw, + [CLKID_SYS_A] =3D &sys_a.hw, + [CLKID_SYS_B_SEL] =3D &sys_b_sel.hw, + [CLKID_SYS_B_DIV] =3D &sys_b_div.hw, + [CLKID_SYS_B] =3D &sys_b.hw, + [CLKID_DSPA_A_SEL] =3D &dspa_a_sel.hw, + [CLKID_DSPA_A_DIV] =3D &dspa_a_div.hw, + [CLKID_DSPA_A] =3D &dspa_a.hw, + [CLKID_DSPA_B_SEL] =3D &dspa_b_sel.hw, + [CLKID_DSPA_B_DIV] =3D &dspa_b_div.hw, + [CLKID_DSPA_B] =3D &dspa_b.hw, + [CLKID_DSPB_A_SEL] =3D &dspb_a_sel.hw, + [CLKID_DSPB_A_DIV] =3D &dspb_a_div.hw, + [CLKID_DSPB_A] =3D &dspb_a.hw, + [CLKID_DSPB_B_SEL] =3D &dspb_b_sel.hw, + [CLKID_DSPB_B_DIV] =3D &dspb_b_div.hw, + [CLKID_DSPB_B] =3D &dspb_b.hw, + [CLKID_RTC_32K_IN] =3D &rtc_32k_in.hw, + [CLKID_RTC_32K_DIV] =3D &rtc_32k_div.hw, + [CLKID_RTC_32K_XTAL] =3D &rtc_32k_xtal.hw, + [CLKID_RTC_32K_SEL] =3D &rtc_32k_sel.hw, + [CLKID_CECB_32K_IN] =3D &cecb_32k_in.hw, + [CLKID_CECB_32K_DIV] =3D &cecb_32k_div.hw, + [CLKID_CECB_32K_SEL_PRE] =3D &cecb_32k_sel_pre.hw, + [CLKID_CECB_32K_SEL] =3D &cecb_32k_sel.hw, + [CLKID_CECA_32K_IN] =3D &ceca_32k_in.hw, + [CLKID_CECA_32K_DIV] =3D &ceca_32k_div.hw, + [CLKID_CECA_32K_SEL_PRE] =3D &ceca_32k_sel_pre.hw, + [CLKID_CECA_32K_SEL] =3D &ceca_32k_sel.hw, + [CLKID_DIV2_PRE] =3D &fclk_div2_divn_pre.hw, + [CLKID_24M_DIV2] =3D &clk_24m_div2.hw, + [CLKID_GEN_SEL] =3D &gen_sel.hw, + [CLKID_GEN_DIV] =3D &gen_div.hw, + [CLKID_SARADC_DIV] =3D &saradc_div.hw, + [CLKID_PWM_A_SEL] =3D &pwm_a_sel.hw, + [CLKID_PWM_A_DIV] =3D &pwm_a_div.hw, + [CLKID_PWM_B_SEL] =3D &pwm_b_sel.hw, + [CLKID_PWM_B_DIV] =3D &pwm_b_div.hw, + [CLKID_PWM_C_SEL] =3D &pwm_c_sel.hw, + [CLKID_PWM_C_DIV] =3D &pwm_c_div.hw, + [CLKID_PWM_D_SEL] =3D &pwm_d_sel.hw, + [CLKID_PWM_D_DIV] =3D &pwm_d_div.hw, + [CLKID_PWM_E_SEL] =3D &pwm_e_sel.hw, + [CLKID_PWM_E_DIV] =3D &pwm_e_div.hw, + [CLKID_PWM_F_SEL] =3D &pwm_f_sel.hw, + [CLKID_PWM_F_DIV] =3D &pwm_f_div.hw, + [CLKID_SPICC_SEL] =3D &spicc_sel.hw, + [CLKID_SPICC_DIV] =3D &spicc_div.hw, + [CLKID_SPICC_SEL2] =3D &spicc_sel2.hw, + [CLKID_TS_DIV] =3D &ts_div.hw, + [CLKID_SPIFC_SEL] =3D &spifc_sel.hw, + [CLKID_SPIFC_DIV] =3D &spifc_div.hw, + [CLKID_SPIFC_SEL2] =3D &spifc_sel2.hw, + [CLKID_USB_BUS_SEL] =3D &usb_bus_sel.hw, + [CLKID_USB_BUS_DIV] =3D &usb_bus_div.hw, + [CLKID_SD_EMMC_SEL] =3D &sd_emmc_sel.hw, + [CLKID_SD_EMMC_DIV] =3D &sd_emmc_div.hw, + [CLKID_SD_EMMC_SEL2] =3D &sd_emmc_sel2.hw, + [CLKID_PSRAM_SEL] =3D &psram_sel.hw, + [CLKID_PSRAM_DIV] =3D &psram_div.hw, + [CLKID_PSRAM_SEL2] =3D &psram_sel2.hw, + [CLKID_DMC_SEL] =3D &dmc_sel.hw, + [CLKID_DMC_DIV] =3D &dmc_div.hw, + [CLKID_DMC_SEL2] =3D &dmc_sel2.hw, }; =20 /* Convenience table to populate regmap in .probe */ @@ -2190,6 +2186,29 @@ static struct regmap_config a1_periphs_regmap_cfg = =3D { .reg_stride =3D 4, }; =20 +struct meson_a1_periphs_clks { + struct clk_hw **hw_clks; + unsigned int hw_clk_num; +}; + +static struct meson_a1_periphs_clks a1_periphs_clks =3D { + .hw_clks =3D a1_periphs_hw_clks, + .hw_clk_num =3D ARRAY_SIZE(a1_periphs_hw_clks), +}; + +static struct clk_hw *meson_a1_periphs_hw_get(struct of_phandle_args *clks= pec, void *clk_data) +{ + const struct meson_a1_periphs_clks *data =3D clk_data; + unsigned int idx =3D clkspec->args[0]; + + if (idx >=3D data->hw_clk_num) { + pr_err("%s: invalid index %u\n", __func__, idx); + return ERR_PTR(-EINVAL); + } + + return data->hw_clks[idx]; +} + static int meson_a1_periphs_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -2211,15 +2230,15 @@ static int meson_a1_periphs_probe(struct platform_d= evice *pdev) for (i =3D 0; i < ARRAY_SIZE(a1_periphs_regmaps); i++) a1_periphs_regmaps[i]->map =3D map; =20 - for (clkid =3D 0; clkid < a1_periphs_clks.num; clkid++) { - err =3D devm_clk_hw_register(dev, a1_periphs_clks.hws[clkid]); + for (clkid =3D 0; clkid < a1_periphs_clks.hw_clk_num; clkid++) { + err =3D devm_clk_hw_register(dev, a1_periphs_clks.hw_clks[clkid]); if (err) return dev_err_probe(dev, err, "clock[%d] registration failed\n", clkid); } =20 - return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + return devm_of_clk_add_hw_provider(dev, meson_a1_periphs_hw_get, &a1_periphs_clks); } =20 diff --git a/drivers/clk/meson/a1-peripherals.h b/drivers/clk/meson/a1-peri= pherals.h index 526fc9ba5c9f..4d60456a95a9 100644 --- a/drivers/clk/meson/a1-peripherals.h +++ b/drivers/clk/meson/a1-peripherals.h @@ -108,6 +108,5 @@ #define CLKID_DMC_SEL 151 #define CLKID_DMC_DIV 152 #define CLKID_DMC_SEL2 153 -#define NR_CLKS 154 =20 #endif /* __A1_PERIPHERALS_H */ diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c index bd2f1d1ec6e4..25d102dc8a5d 100644 --- a/drivers/clk/meson/a1-pll.c +++ b/drivers/clk/meson/a1-pll.c @@ -268,22 +268,18 @@ static struct clk_regmap fclk_div7 =3D { }; =20 /* Array of all clocks registered by this provider */ -static struct clk_hw_onecell_data a1_pll_clks =3D { - .hws =3D { - [CLKID_FIXED_PLL_DCO] =3D &fixed_pll_dco.hw, - [CLKID_FIXED_PLL] =3D &fixed_pll.hw, - [CLKID_FCLK_DIV2_DIV] =3D &fclk_div2_div.hw, - [CLKID_FCLK_DIV3_DIV] =3D &fclk_div3_div.hw, - [CLKID_FCLK_DIV5_DIV] =3D &fclk_div5_div.hw, - [CLKID_FCLK_DIV7_DIV] =3D &fclk_div7_div.hw, - [CLKID_FCLK_DIV2] =3D &fclk_div2.hw, - [CLKID_FCLK_DIV3] =3D &fclk_div3.hw, - [CLKID_FCLK_DIV5] =3D &fclk_div5.hw, - [CLKID_FCLK_DIV7] =3D &fclk_div7.hw, - [CLKID_HIFI_PLL] =3D &hifi_pll.hw, - [NR_PLL_CLKS] =3D NULL, - }, - .num =3D NR_PLL_CLKS, +static struct clk_hw *a1_pll_hw_clks[] =3D { + [CLKID_FIXED_PLL_DCO] =3D &fixed_pll_dco.hw, + [CLKID_FIXED_PLL] =3D &fixed_pll.hw, + [CLKID_FCLK_DIV2_DIV] =3D &fclk_div2_div.hw, + [CLKID_FCLK_DIV3_DIV] =3D &fclk_div3_div.hw, + [CLKID_FCLK_DIV5_DIV] =3D &fclk_div5_div.hw, + [CLKID_FCLK_DIV7_DIV] =3D &fclk_div7_div.hw, + [CLKID_FCLK_DIV2] =3D &fclk_div2.hw, + [CLKID_FCLK_DIV3] =3D &fclk_div3.hw, + [CLKID_FCLK_DIV5] =3D &fclk_div5.hw, + [CLKID_FCLK_DIV7] =3D &fclk_div7.hw, + [CLKID_HIFI_PLL] =3D &hifi_pll.hw, }; =20 static struct clk_regmap *const a1_pll_regmaps[] =3D { @@ -302,6 +298,29 @@ static struct regmap_config a1_pll_regmap_cfg =3D { .reg_stride =3D 4, }; =20 +struct meson_a1_pll_clks { + struct clk_hw **hw_clks; + unsigned int hw_clk_num; +}; + +static struct meson_a1_pll_clks a1_pll_clks =3D { + .hw_clks =3D a1_pll_hw_clks, + .hw_clk_num =3D ARRAY_SIZE(a1_pll_hw_clks), +}; + +static struct clk_hw *meson_a1_pll_hw_get(struct of_phandle_args *clkspec,= void *clk_data) +{ + const struct meson_a1_pll_clks *data =3D clk_data; + unsigned int idx =3D clkspec->args[0]; + + if (idx >=3D data->hw_clk_num) { + pr_err("%s: invalid index %u\n", __func__, idx); + return ERR_PTR(-EINVAL); + } + + return data->hw_clks[idx]; +} + static int meson_a1_pll_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -324,15 +343,15 @@ static int meson_a1_pll_probe(struct platform_device = *pdev) a1_pll_regmaps[i]->map =3D map; =20 /* Register clocks */ - for (clkid =3D 0; clkid < a1_pll_clks.num; clkid++) { - err =3D devm_clk_hw_register(dev, a1_pll_clks.hws[clkid]); + for (clkid =3D 0; clkid < a1_pll_clks.hw_clk_num; clkid++) { + err =3D devm_clk_hw_register(dev, a1_pll_clks.hw_clks[clkid]); if (err) return dev_err_probe(dev, err, "clock[%d] registration failed\n", clkid); } =20 - return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + return devm_of_clk_add_hw_provider(dev, meson_a1_pll_hw_get, &a1_pll_clks); } =20 diff --git a/drivers/clk/meson/a1-pll.h b/drivers/clk/meson/a1-pll.h index 29726651b056..82570759e6a2 100644 --- a/drivers/clk/meson/a1-pll.h +++ b/drivers/clk/meson/a1-pll.h @@ -42,6 +42,5 @@ #define CLKID_FCLK_DIV3_DIV 3 #define CLKID_FCLK_DIV5_DIV 4 #define CLKID_FCLK_DIV7_DIV 5 -#define NR_PLL_CLKS 11 =20 #endif /* __A1_PLL_H */ --=20 2.34.1