From nobody Sun Feb 8 10:33:48 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB578C77B7A for ; Tue, 6 Jun 2023 15:38:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237575AbjFFPif (ORCPT ); Tue, 6 Jun 2023 11:38:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231700AbjFFPic (ORCPT ); Tue, 6 Jun 2023 11:38:32 -0400 Received: from finn.localdomain (finn.gateworks.com [108.161.129.64]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA089139; Tue, 6 Jun 2023 08:38:30 -0700 (PDT) Received: from 068-189-091-139.biz.spectrum.com ([68.189.91.139] helo=tharvey.pdc.gateworks.com) by finn.localdomain with esmtp (Exim 4.93) (envelope-from ) id 1q6YlJ-0067oT-EH; Tue, 06 Jun 2023 15:38:21 +0000 From: Tim Harvey To: linux-arm-kernel@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Tim Harvey Subject: [PATCH] arm64: dts: imx8mm-venice-gw7904: enable UART1 hardware flow control Date: Tue, 6 Jun 2023 08:38:19 -0700 Message-Id: <20230606153819.1449257-1-tharvey@gateworks.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" On the GW7904 uart1 can use UART3_TX/RX for hardware flow control which was the desired default configuration. Remove uart3 and configure uart1 for hardware flow control. Signed-off-by: Tim Harvey --- .../dts/freescale/imx8mm-venice-gw7904.dts | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts b/arch/= arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts index 93088fa1c3b9..c12e3f4f800f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts @@ -636,6 +636,8 @@ &pgc_mipi { &uart1 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_uart1>; + cts-gpios =3D <&gpio5 26 GPIO_ACTIVE_LOW>; + rts-gpios =3D <&gpio5 27 GPIO_ACTIVE_LOW>; status =3D "okay"; }; =20 @@ -646,13 +648,6 @@ &uart2 { status =3D "okay"; }; =20 -/* off-board RS232 */ -&uart3 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_uart3>; - status =3D "okay"; -}; - &usbotg1 { dr_mode =3D "host"; disable-over-current; @@ -814,6 +809,8 @@ pinctrl_uart1: uart1grp { fsl,pins =3D < MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x140 /* CTS# in */ + MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x140 /* RTS# out */ >; }; =20 @@ -824,13 +821,6 @@ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 >; }; =20 - pinctrl_uart3: uart3grp { - fsl,pins =3D < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 - >; - }; - pinctrl_usdhc2: usdhc2grp { fsl,pins =3D < MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 --=20 2.25.1